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Implement insns.dat in human readable form
[nasm/avx512.git] / disasm.c
blobe9d1763e2b32ae4bf1afe407ba129f9d18ccb7d5
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2010 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
36 */
37
38 #include "compiler.h"
39
40 #include <stdio.h>
41 #include <string.h>
42 #include <limits.h>
43 #include <inttypes.h>
44
45 #include "nasm.h"
46 #include "disasm.h"
47 #include "sync.h"
48 #include "insns.h"
49 #include "tables.h"
50 #include "regdis.h"
51
52 /*
53 * Flags that go into the `segment' field of `insn' structures
54 * during disassembly.
55 */
56 #define SEG_RELATIVE 1
57 #define SEG_32BIT 2
58 #define SEG_RMREG 4
59 #define SEG_DISP8 8
60 #define SEG_DISP16 16
61 #define SEG_DISP32 32
62 #define SEG_NODISP 64
63 #define SEG_SIGNED 128
64 #define SEG_64BIT 256
65
66 /*
67 * Prefix information
68 */
69 struct prefix_info {
70 uint8_t osize; /* Operand size */
71 uint8_t asize; /* Address size */
72 uint8_t osp; /* Operand size prefix present */
73 uint8_t asp; /* Address size prefix present */
74 uint8_t rep; /* Rep prefix present */
75 uint8_t seg; /* Segment override prefix present */
76 uint8_t wait; /* WAIT "prefix" present */
77 uint8_t lock; /* Lock prefix present */
78 uint8_t vex[3]; /* VEX prefix present */
79 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
80 uint8_t vex_m; /* VEX.M field */
81 uint8_t vex_v;
82 uint8_t vex_lp; /* VEX.LP fields */
83 uint32_t rex; /* REX prefix present */
84 };
85
86 #define getu8(x) (*(uint8_t *)(x))
87 #if X86_MEMORY
88 /* Littleendian CPU which can handle unaligned references */
89 #define getu16(x) (*(uint16_t *)(x))
90 #define getu32(x) (*(uint32_t *)(x))
91 #define getu64(x) (*(uint64_t *)(x))
92 #else
93 static uint16_t getu16(uint8_t *data)
94 {
95 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
96 }
97 static uint32_t getu32(uint8_t *data)
98 {
99 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
100 }
101 static uint64_t getu64(uint8_t *data)
102 {
103 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
104 }
105 #endif
106
107 #define gets8(x) ((int8_t)getu8(x))
108 #define gets16(x) ((int16_t)getu16(x))
109 #define gets32(x) ((int32_t)getu32(x))
110 #define gets64(x) ((int64_t)getu64(x))
111
112 /* Important: regval must already have been adjusted for rex extensions */
113 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
114 {
115 if (!(regflags & (REGISTER|REGMEM)))
116 return 0; /* Registers not permissible?! */
117
118 regflags |= REGISTER;
119
120 if (!(REG_AL & ~regflags))
121 return R_AL;
122 if (!(REG_AX & ~regflags))
123 return R_AX;
124 if (!(REG_EAX & ~regflags))
125 return R_EAX;
126 if (!(REG_RAX & ~regflags))
127 return R_RAX;
128 if (!(REG_DL & ~regflags))
129 return R_DL;
130 if (!(REG_DX & ~regflags))
131 return R_DX;
132 if (!(REG_EDX & ~regflags))
133 return R_EDX;
134 if (!(REG_RDX & ~regflags))
135 return R_RDX;
136 if (!(REG_CL & ~regflags))
137 return R_CL;
138 if (!(REG_CX & ~regflags))
139 return R_CX;
140 if (!(REG_ECX & ~regflags))
141 return R_ECX;
142 if (!(REG_RCX & ~regflags))
143 return R_RCX;
144 if (!(FPU0 & ~regflags))
145 return R_ST0;
146 if (!(XMM0 & ~regflags))
147 return R_XMM0;
148 if (!(YMM0 & ~regflags))
149 return R_YMM0;
150 if (!(REG_CS & ~regflags))
151 return (regval == 1) ? R_CS : 0;
152 if (!(REG_DESS & ~regflags))
153 return (regval == 0 || regval == 2
154 || regval == 3 ? nasm_rd_sreg[regval] : 0);
155 if (!(REG_FSGS & ~regflags))
156 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
157 if (!(REG_SEG67 & ~regflags))
158 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
159
160 /* All the entries below look up regval in an 16-entry array */
161 if (regval < 0 || regval > 15)
162 return 0;
163
164 if (!(REG8 & ~regflags)) {
165 if (rex & (REX_P|REX_NH))
166 return nasm_rd_reg8_rex[regval];
167 else
168 return nasm_rd_reg8[regval];
169 }
170 if (!(REG16 & ~regflags))
171 return nasm_rd_reg16[regval];
172 if (!(REG32 & ~regflags))
173 return nasm_rd_reg32[regval];
174 if (!(REG64 & ~regflags))
175 return nasm_rd_reg64[regval];
176 if (!(REG_SREG & ~regflags))
177 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
178 if (!(REG_CREG & ~regflags))
179 return nasm_rd_creg[regval];
180 if (!(REG_DREG & ~regflags))
181 return nasm_rd_dreg[regval];
182 if (!(REG_TREG & ~regflags)) {
183 if (regval > 7)
184 return 0; /* TR registers are ill-defined with rex */
185 return nasm_rd_treg[regval];
186 }
187 if (!(FPUREG & ~regflags))
188 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
189 if (!(MMXREG & ~regflags))
190 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
191 if (!(XMMREG & ~regflags))
192 return nasm_rd_xmmreg[regval];
193 if (!(YMMREG & ~regflags))
194 return nasm_rd_ymmreg[regval];
195
196 return 0;
197 }
198
199 /*
200 * Process an effective address (ModRM) specification.
201 */
202 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
203 int segsize, enum ea_type type,
204 operand *op, insn *ins)
205 {
206 int mod, rm, scale, index, base;
207 int rex;
208 uint8_t sib = 0;
209
210 mod = (modrm >> 6) & 03;
211 rm = modrm & 07;
212
213 if (mod != 3 && asize != 16 && rm == 4)
214 sib = *data++;
215
216 rex = ins->rex;
217
218 if (mod == 3) { /* pure register version */
219 op->basereg = rm+(rex & REX_B ? 8 : 0);
220 op->segment |= SEG_RMREG;
221 return data;
222 }
223
224 op->disp_size = 0;
225 op->eaflags = 0;
226
227 if (asize == 16) {
228 /*
229 * <mod> specifies the displacement size (none, byte or
230 * word), and <rm> specifies the register combination.
231 * Exception: mod=0,rm=6 does not specify [BP] as one might
232 * expect, but instead specifies [disp16].
233 */
234
235 if (type != EA_SCALAR)
236 return NULL;
237
238 op->indexreg = op->basereg = -1;
239 op->scale = 1; /* always, in 16 bits */
240 switch (rm) {
241 case 0:
242 op->basereg = R_BX;
243 op->indexreg = R_SI;
244 break;
245 case 1:
246 op->basereg = R_BX;
247 op->indexreg = R_DI;
248 break;
249 case 2:
250 op->basereg = R_BP;
251 op->indexreg = R_SI;
252 break;
253 case 3:
254 op->basereg = R_BP;
255 op->indexreg = R_DI;
256 break;
257 case 4:
258 op->basereg = R_SI;
259 break;
260 case 5:
261 op->basereg = R_DI;
262 break;
263 case 6:
264 op->basereg = R_BP;
265 break;
266 case 7:
267 op->basereg = R_BX;
268 break;
269 }
270 if (rm == 6 && mod == 0) { /* special case */
271 op->basereg = -1;
272 if (segsize != 16)
273 op->disp_size = 16;
274 mod = 2; /* fake disp16 */
275 }
276 switch (mod) {
277 case 0:
278 op->segment |= SEG_NODISP;
279 break;
280 case 1:
281 op->segment |= SEG_DISP8;
282 op->offset = (int8_t)*data++;
283 break;
284 case 2:
285 op->segment |= SEG_DISP16;
286 op->offset = *data++;
287 op->offset |= ((unsigned)*data++) << 8;
288 break;
289 }
290 return data;
291 } else {
292 /*
293 * Once again, <mod> specifies displacement size (this time
294 * none, byte or *dword*), while <rm> specifies the base
295 * register. Again, [EBP] is missing, replaced by a pure
296 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
297 * and RIP-relative addressing in 64-bit mode.
298 *
299 * However, rm=4
300 * indicates not a single base register, but instead the
301 * presence of a SIB byte...
302 */
303 int a64 = asize == 64;
304
305 op->indexreg = -1;
306
307 if (a64)
308 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
309 else
310 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
311
312 if (rm == 5 && mod == 0) {
313 if (segsize == 64) {
314 op->eaflags |= EAF_REL;
315 op->segment |= SEG_RELATIVE;
316 mod = 2; /* fake disp32 */
317 }
318
319 if (asize != 64)
320 op->disp_size = asize;
321
322 op->basereg = -1;
323 mod = 2; /* fake disp32 */
324 }
325
326
327 if (rm == 4) { /* process SIB */
328 scale = (sib >> 6) & 03;
329 index = (sib >> 3) & 07;
330 base = sib & 07;
331
332 op->scale = 1 << scale;
333
334 if (index == 4 && !(rex & REX_X))
335 op->indexreg = -1; /* ESP/RSP cannot be an index */
336 else if (type == EA_XMMVSIB)
337 op->indexreg = nasm_rd_xmmreg[index | ((rex & REX_X) ? 8 : 0)];
338 else if (type == EA_YMMVSIB)
339 op->indexreg = nasm_rd_ymmreg[index | ((rex & REX_X) ? 8 : 0)];
340 else if (a64)
341 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
342 else
343 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
344
345 if (base == 5 && mod == 0) {
346 op->basereg = -1;
347 mod = 2; /* Fake disp32 */
348 } else if (a64)
349 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
350 else
351 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
352
353 if (segsize == 16)
354 op->disp_size = 32;
355 } else if (type != EA_SCALAR) {
356 /* Can't have VSIB without SIB */
357 return NULL;
358 }
359
360 switch (mod) {
361 case 0:
362 op->segment |= SEG_NODISP;
363 break;
364 case 1:
365 op->segment |= SEG_DISP8;
366 op->offset = gets8(data);
367 data++;
368 break;
369 case 2:
370 op->segment |= SEG_DISP32;
371 op->offset = gets32(data);
372 data += 4;
373 break;
374 }
375 return data;
376 }
377 }
378
379 /*
380 * Determine whether the instruction template in t corresponds to the data
381 * stream in data. Return the number of bytes matched if so.
382 */
383 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
384
385 static int matches(const struct itemplate *t, uint8_t *data,
386 const struct prefix_info *prefix, int segsize, insn *ins)
387 {
388 uint8_t *r = (uint8_t *)(t->code);
389 uint8_t *origdata = data;
390 bool a_used = false, o_used = false;
391 enum prefixes drep = 0;
392 enum prefixes dwait = 0;
393 uint8_t lock = prefix->lock;
394 int osize = prefix->osize;
395 int asize = prefix->asize;
396 int i, c;
397 int op1, op2;
398 struct operand *opx, *opy;
399 uint8_t opex = 0;
400 int s_field_for = -1; /* No 144/154 series code encountered */
401 bool vex_ok = false;
402 int regmask = (segsize == 64) ? 15 : 7;
403 enum ea_type eat = EA_SCALAR;
404
405 for (i = 0; i < MAX_OPERANDS; i++) {
406 ins->oprs[i].segment = ins->oprs[i].disp_size =
407 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
408 }
409 ins->condition = -1;
410 ins->rex = prefix->rex;
411 memset(ins->prefixes, 0, sizeof ins->prefixes);
412
413 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
414 return false;
415
416 if (prefix->rep == 0xF2)
417 drep = P_REPNE;
418 else if (prefix->rep == 0xF3)
419 drep = P_REP;
420
421 dwait = prefix->wait ? P_WAIT : 0;
422
423 while ((c = *r++) != 0) {
424 op1 = (c & 3) + ((opex & 1) << 2);
425 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
426 opx = &ins->oprs[op1];
427 opy = &ins->oprs[op2];
428 opex = 0;
429
430 switch (c) {
431 case 01:
432 case 02:
433 case 03:
434 case 04:
435 while (c--)
436 if (*r++ != *data++)
437 return false;
438 break;
439
440 case 05:
441 case 06:
442 case 07:
443 opex = c;
444 break;
445
446 case4(010):
447 {
448 int t = *r++, d = *data++;
449 if (d < t || d > t + 7)
450 return false;
451 else {
452 opx->basereg = (d-t)+
453 (ins->rex & REX_B ? 8 : 0);
454 opx->segment |= SEG_RMREG;
455 }
456 break;
457 }
458
459 case4(014):
460 case4(0274):
461 opx->offset = (int8_t)*data++;
462 opx->segment |= SEG_SIGNED;
463 break;
464
465 case4(020):
466 opx->offset = *data++;
467 break;
468
469 case4(024):
470 opx->offset = *data++;
471 break;
472
473 case4(030):
474 opx->offset = getu16(data);
475 data += 2;
476 break;
477
478 case4(034):
479 if (osize == 32) {
480 opx->offset = getu32(data);
481 data += 4;
482 } else {
483 opx->offset = getu16(data);
484 data += 2;
485 }
486 if (segsize != asize)
487 opx->disp_size = asize;
488 break;
489
490 case4(040):
491 case4(0254):
492 opx->offset = getu32(data);
493 data += 4;
494 break;
495
496 case4(044):
497 switch (asize) {
498 case 16:
499 opx->offset = getu16(data);
500 data += 2;
501 if (segsize != 16)
502 opx->disp_size = 16;
503 break;
504 case 32:
505 opx->offset = getu32(data);
506 data += 4;
507 if (segsize == 16)
508 opx->disp_size = 32;
509 break;
510 case 64:
511 opx->offset = getu64(data);
512 opx->disp_size = 64;
513 data += 8;
514 break;
515 }
516 break;
517
518 case4(050):
519 opx->offset = gets8(data++);
520 opx->segment |= SEG_RELATIVE;
521 break;
522
523 case4(054):
524 opx->offset = getu64(data);
525 data += 8;
526 break;
527
528 case4(060):
529 opx->offset = gets16(data);
530 data += 2;
531 opx->segment |= SEG_RELATIVE;
532 opx->segment &= ~SEG_32BIT;
533 break;
534
535 case4(064):
536 opx->segment |= SEG_RELATIVE;
537 if (osize == 16) {
538 opx->offset = gets16(data);
539 data += 2;
540 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
541 } else if (osize == 32) {
542 opx->offset = gets32(data);
543 data += 4;
544 opx->segment &= ~SEG_64BIT;
545 opx->segment |= SEG_32BIT;
546 }
547 if (segsize != osize) {
548 opx->type =
549 (opx->type & ~SIZE_MASK)
550 | ((osize == 16) ? BITS16 : BITS32);
551 }
552 break;
553
554 case4(070):
555 opx->offset = gets32(data);
556 data += 4;
557 opx->segment |= SEG_32BIT | SEG_RELATIVE;
558 break;
559
560 case4(0100):
561 case4(0110):
562 case4(0120):
563 case4(0130):
564 {
565 int modrm = *data++;
566 opx->segment |= SEG_RMREG;
567 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
568 if (!data)
569 return false;
570 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
571 break;
572 }
573
574 case4(0140):
575 if (s_field_for == op1) {
576 opx->offset = gets8(data);
577 data++;
578 } else {
579 opx->offset = getu16(data);
580 data += 2;
581 }
582 break;
583
584 case4(0144):
585 case4(0154):
586 s_field_for = (*data & 0x02) ? op1 : -1;
587 if ((*data++ & ~0x02) != *r++)
588 return false;
589 break;
590
591 case4(0150):
592 if (s_field_for == op1) {
593 opx->offset = gets8(data);
594 data++;
595 } else {
596 opx->offset = getu32(data);
597 data += 4;
598 }
599 break;
600
601 case 0172:
602 {
603 uint8_t ximm = *data++;
604 c = *r++;
605 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
606 ins->oprs[c >> 3].segment |= SEG_RMREG;
607 ins->oprs[c & 7].offset = ximm & 15;
608 }
609 break;
610
611 case 0173:
612 {
613 uint8_t ximm = *data++;
614 c = *r++;
615
616 if ((c ^ ximm) & 15)
617 return false;
618
619 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
620 ins->oprs[c >> 4].segment |= SEG_RMREG;
621 }
622 break;
623
624 case4(0174):
625 {
626 uint8_t ximm = *data++;
627
628 opx->basereg = (ximm >> 4) & regmask;
629 opx->segment |= SEG_RMREG;
630 }
631 break;
632
633 case4(0200):
634 case4(0204):
635 case4(0210):
636 case4(0214):
637 case4(0220):
638 case4(0224):
639 case4(0230):
640 case4(0234):
641 {
642 int modrm = *data++;
643 if (((modrm >> 3) & 07) != (c & 07))
644 return false; /* spare field doesn't match up */
645 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
646 if (!data)
647 return false;
648 break;
649 }
650
651 case4(0250):
652 if (s_field_for == op1) {
653 opx->offset = gets8(data);
654 data++;
655 } else {
656 opx->offset = gets32(data);
657 data += 4;
658 }
659 break;
660
661 case4(0260):
662 case 0270:
663 {
664 int vexm = *r++;
665 int vexwlp = *r++;
666
667 ins->rex |= REX_V;
668 if ((prefix->rex & (REX_V|REX_P)) != REX_V)
669 return false;
670
671 if ((vexm & 0x1f) != prefix->vex_m)
672 return false;
673
674 switch (vexwlp & 060) {
675 case 000:
676 if (prefix->rex & REX_W)
677 return false;
678 break;
679 case 020:
680 if (!(prefix->rex & REX_W))
681 return false;
682 ins->rex &= ~REX_W;
683 break;
684 case 040: /* VEX.W is a don't care */
685 ins->rex &= ~REX_W;
686 break;
687 case 060:
688 break;
689 }
690
691 /* The 010 bit of vexwlp is set if VEX.L is ignored */
692 if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07))
693 return false;
694
695 if (c == 0270) {
696 if (prefix->vex_v != 0)
697 return false;
698 } else {
699 opx->segment |= SEG_RMREG;
700 opx->basereg = prefix->vex_v;
701 }
702 vex_ok = true;
703 break;
704 }
705
706 case 0310:
707 if (asize != 16)
708 return false;
709 else
710 a_used = true;
711 break;
712
713 case 0311:
714 if (asize != 32)
715 return false;
716 else
717 a_used = true;
718 break;
719
720 case 0312:
721 if (asize != segsize)
722 return false;
723 else
724 a_used = true;
725 break;
726
727 case 0313:
728 if (asize != 64)
729 return false;
730 else
731 a_used = true;
732 break;
733
734 case 0314:
735 if (prefix->rex & REX_B)
736 return false;
737 break;
738
739 case 0315:
740 if (prefix->rex & REX_X)
741 return false;
742 break;
743
744 case 0316:
745 if (prefix->rex & REX_R)
746 return false;
747 break;
748
749 case 0317:
750 if (prefix->rex & REX_W)
751 return false;
752 break;
753
754 case 0320:
755 if (osize != 16)
756 return false;
757 else
758 o_used = true;
759 break;
760
761 case 0321:
762 if (osize != 32)
763 return false;
764 else
765 o_used = true;
766 break;
767
768 case 0322:
769 if (osize != (segsize == 16) ? 16 : 32)
770 return false;
771 else
772 o_used = true;
773 break;
774
775 case 0323:
776 ins->rex |= REX_W; /* 64-bit only instruction */
777 osize = 64;
778 o_used = true;
779 break;
780
781 case 0324:
782 if (osize != 64)
783 return false;
784 o_used = true;
785 break;
786
787 case 0325:
788 ins->rex |= REX_NH;
789 break;
790
791 case 0330:
792 {
793 int t = *r++, d = *data++;
794 if (d < t || d > t + 15)
795 return false;
796 else
797 ins->condition = d - t;
798 break;
799 }
800
801 case 0331:
802 if (prefix->rep)
803 return false;
804 break;
805
806 case 0332:
807 if (prefix->rep != 0xF2)
808 return false;
809 drep = 0;
810 break;
811
812 case 0333:
813 if (prefix->rep != 0xF3)
814 return false;
815 drep = 0;
816 break;
817
818 case 0334:
819 if (lock) {
820 ins->rex |= REX_R;
821 lock = 0;
822 }
823 break;
824
825 case 0335:
826 if (drep == P_REP)
827 drep = P_REPE;
828 break;
829
830 case 0336:
831 case 0337:
832 break;
833
834 case 0340:
835 return false;
836
837 case 0341:
838 if (prefix->wait != 0x9B)
839 return false;
840 dwait = 0;
841 break;
842
843 case4(0344):
844 ins->oprs[0].basereg = (*data++ >> 3) & 7;
845 break;
846
847 case 0360:
848 if (prefix->osp || prefix->rep)
849 return false;
850 break;
851
852 case 0361:
853 if (!prefix->osp || prefix->rep)
854 return false;
855 o_used = true;
856 break;
857
858 case 0362:
859 if (prefix->osp || prefix->rep != 0xf2)
860 return false;
861 drep = 0;
862 break;
863
864 case 0363:
865 if (prefix->osp || prefix->rep != 0xf3)
866 return false;
867 drep = 0;
868 break;
869
870 case 0364:
871 if (prefix->osp)
872 return false;
873 break;
874
875 case 0365:
876 if (prefix->asp)
877 return false;
878 break;
879
880 case 0366:
881 if (!prefix->osp)
882 return false;
883 o_used = true;
884 break;
885
886 case 0367:
887 if (!prefix->asp)
888 return false;
889 a_used = true;
890 break;
891
892 case 0374:
893 eat = EA_XMMVSIB;
894 break;
895
896 case 0375:
897 eat = EA_YMMVSIB;
898 break;
899
900 default:
901 return false; /* Unknown code */
902 }
903 }
904
905 if (!vex_ok && (ins->rex & REX_V))
906 return false;
907
908 /* REX cannot be combined with VEX */
909 if ((ins->rex & REX_V) && (prefix->rex & REX_P))
910 return false;
911
912 /*
913 * Check for unused rep or a/o prefixes.
914 */
915 for (i = 0; i < t->operands; i++) {
916 if (ins->oprs[i].segment != SEG_RMREG)
917 a_used = true;
918 }
919
920 if (lock) {
921 if (ins->prefixes[PPS_LREP])
922 return false;
923 ins->prefixes[PPS_LREP] = P_LOCK;
924 }
925 if (drep) {
926 if (ins->prefixes[PPS_LREP])
927 return false;
928 ins->prefixes[PPS_LREP] = drep;
929 }
930 ins->prefixes[PPS_WAIT] = dwait;
931 if (!o_used) {
932 if (osize != ((segsize == 16) ? 16 : 32)) {
933 enum prefixes pfx = 0;
934
935 switch (osize) {
936 case 16:
937 pfx = P_O16;
938 break;
939 case 32:
940 pfx = P_O32;
941 break;
942 case 64:
943 pfx = P_O64;
944 break;
945 }
946
947 if (ins->prefixes[PPS_OSIZE])
948 return false;
949 ins->prefixes[PPS_OSIZE] = pfx;
950 }
951 }
952 if (!a_used && asize != segsize) {
953 if (ins->prefixes[PPS_ASIZE])
954 return false;
955 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
956 }
957
958 /* Fix: check for redundant REX prefixes */
959
960 return data - origdata;
961 }
962
963 /* Condition names for disassembly, sorted by x86 code */
964 static const char * const condition_name[16] = {
965 "o", "no", "c", "nc", "z", "nz", "na", "a",
966 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
967 };
968
969 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
970 int32_t offset, int autosync, uint32_t prefer)
971 {
972 const struct itemplate * const *p, * const *best_p;
973 const struct disasm_index *ix;
974 uint8_t *dp;
975 int length, best_length = 0;
976 char *segover;
977 int i, slen, colon, n;
978 uint8_t *origdata;
979 int works;
980 insn tmp_ins, ins;
981 uint32_t goodness, best;
982 int best_pref;
983 struct prefix_info prefix;
984 bool end_prefix;
985
986 memset(&ins, 0, sizeof ins);
987
988 /*
989 * Scan for prefixes.
990 */
991 memset(&prefix, 0, sizeof prefix);
992 prefix.asize = segsize;
993 prefix.osize = (segsize == 64) ? 32 : segsize;
994 segover = NULL;
995 origdata = data;
996
997 ix = itable;
998
999 end_prefix = false;
1000 while (!end_prefix) {
1001 switch (*data) {
1002 case 0xF2:
1003 case 0xF3:
1004 prefix.rep = *data++;
1005 break;
1006
1007 case 0x9B:
1008 prefix.wait = *data++;
1009 break;
1010
1011 case 0xF0:
1012 prefix.lock = *data++;
1013 break;
1014
1015 case 0x2E:
1016 segover = "cs", prefix.seg = *data++;
1017 break;
1018 case 0x36:
1019 segover = "ss", prefix.seg = *data++;
1020 break;
1021 case 0x3E:
1022 segover = "ds", prefix.seg = *data++;
1023 break;
1024 case 0x26:
1025 segover = "es", prefix.seg = *data++;
1026 break;
1027 case 0x64:
1028 segover = "fs", prefix.seg = *data++;
1029 break;
1030 case 0x65:
1031 segover = "gs", prefix.seg = *data++;
1032 break;
1033
1034 case 0x66:
1035 prefix.osize = (segsize == 16) ? 32 : 16;
1036 prefix.osp = *data++;
1037 break;
1038 case 0x67:
1039 prefix.asize = (segsize == 32) ? 16 : 32;
1040 prefix.asp = *data++;
1041 break;
1042
1043 case 0xC4:
1044 case 0xC5:
1045 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1046 prefix.vex[0] = *data++;
1047 prefix.vex[1] = *data++;
1048
1049 prefix.rex = REX_V;
1050 prefix.vex_c = RV_VEX;
1051
1052 if (prefix.vex[0] == 0xc4) {
1053 prefix.vex[2] = *data++;
1054 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1055 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1056 prefix.vex_m = prefix.vex[1] & 0x1f;
1057 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1058 prefix.vex_lp = prefix.vex[2] & 7;
1059 } else {
1060 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1061 prefix.vex_m = 1;
1062 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1063 prefix.vex_lp = prefix.vex[1] & 7;
1064 }
1065
1066 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3];
1067 }
1068 end_prefix = true;
1069 break;
1070
1071 case 0x8F:
1072 if ((data[1] & 030) != 0 &&
1073 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1074 prefix.vex[0] = *data++;
1075 prefix.vex[1] = *data++;
1076 prefix.vex[2] = *data++;
1077
1078 prefix.rex = REX_V;
1079 prefix.vex_c = RV_XOP;
1080
1081 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1082 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1083 prefix.vex_m = prefix.vex[1] & 0x1f;
1084 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1085 prefix.vex_lp = prefix.vex[2] & 7;
1086
1087 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp & 3];
1088 }
1089 end_prefix = true;
1090 break;
1091
1092 case REX_P + 0x0:
1093 case REX_P + 0x1:
1094 case REX_P + 0x2:
1095 case REX_P + 0x3:
1096 case REX_P + 0x4:
1097 case REX_P + 0x5:
1098 case REX_P + 0x6:
1099 case REX_P + 0x7:
1100 case REX_P + 0x8:
1101 case REX_P + 0x9:
1102 case REX_P + 0xA:
1103 case REX_P + 0xB:
1104 case REX_P + 0xC:
1105 case REX_P + 0xD:
1106 case REX_P + 0xE:
1107 case REX_P + 0xF:
1108 if (segsize == 64) {
1109 prefix.rex = *data++;
1110 if (prefix.rex & REX_W)
1111 prefix.osize = 64;
1112 }
1113 end_prefix = true;
1114 break;
1115
1116 default:
1117 end_prefix = true;
1118 break;
1119 }
1120 }
1121
1122 best = -1; /* Worst possible */
1123 best_p = NULL;
1124 best_pref = INT_MAX;
1125
1126 if (!ix)
1127 return 0; /* No instruction table at all... */
1128
1129 dp = data;
1130 ix += *dp++;
1131 while (ix->n == -1) {
1132 ix = (const struct disasm_index *)ix->p + *dp++;
1133 }
1134
1135 p = (const struct itemplate * const *)ix->p;
1136 for (n = ix->n; n; n--, p++) {
1137 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1138 works = true;
1139 /*
1140 * Final check to make sure the types of r/m match up.
1141 * XXX: Need to make sure this is actually correct.
1142 */
1143 for (i = 0; i < (*p)->operands; i++) {
1144 if (!((*p)->opd[i] & SAME_AS) &&
1145 (
1146 /* If it's a mem-only EA but we have a
1147 register, die. */
1148 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1149 is_class(MEMORY, (*p)->opd[i])) ||
1150 /* If it's a reg-only EA but we have a memory
1151 ref, die. */
1152 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1153 !(REG_EA & ~(*p)->opd[i]) &&
1154 !((*p)->opd[i] & REG_SMASK)) ||
1155 /* Register type mismatch (eg FS vs REG_DESS):
1156 die. */
1157 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1158 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1159 !whichreg((*p)->opd[i],
1160 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1161 )) {
1162 works = false;
1163 break;
1164 }
1165 }
1166
1167 /*
1168 * Note: we always prefer instructions which incorporate
1169 * prefixes in the instructions themselves. This is to allow
1170 * e.g. PAUSE to be preferred to REP NOP, and deal with
1171 * MMX/SSE instructions where prefixes are used to select
1172 * between MMX and SSE register sets or outright opcode
1173 * selection.
1174 */
1175 if (works) {
1176 int i, nprefix;
1177 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1178 nprefix = 0;
1179 for (i = 0; i < MAXPREFIX; i++)
1180 if (tmp_ins.prefixes[i])
1181 nprefix++;
1182 if (nprefix < best_pref ||
1183 (nprefix == best_pref && goodness < best)) {
1184 /* This is the best one found so far */
1185 best = goodness;
1186 best_p = p;
1187 best_pref = nprefix;
1188 best_length = length;
1189 ins = tmp_ins;
1190 }
1191 }
1192 }
1193 }
1194
1195 if (!best_p)
1196 return 0; /* no instruction was matched */
1197
1198 /* Pick the best match */
1199 p = best_p;
1200 length = best_length;
1201
1202 slen = 0;
1203
1204 /* TODO: snprintf returns the value that the string would have if
1205 * the buffer were long enough, and not the actual length of
1206 * the returned string, so each instance of using the return
1207 * value of snprintf should actually be checked to assure that
1208 * the return value is "sane." Maybe a macro wrapper could
1209 * be used for that purpose.
1210 */
1211 for (i = 0; i < MAXPREFIX; i++) {
1212 const char *prefix = prefix_name(ins.prefixes[i]);
1213 if (prefix)
1214 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1215 }
1216
1217 i = (*p)->opcode;
1218 if (i >= FIRST_COND_OPCODE)
1219 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1220 nasm_insn_names[i], condition_name[ins.condition]);
1221 else
1222 slen += snprintf(output + slen, outbufsize - slen, "%s",
1223 nasm_insn_names[i]);
1224
1225 colon = false;
1226 length += data - origdata; /* fix up for prefixes */
1227 for (i = 0; i < (*p)->operands; i++) {
1228 opflags_t t = (*p)->opd[i];
1229 const operand *o = &ins.oprs[i];
1230 int64_t offs;
1231
1232 if (t & SAME_AS) {
1233 o = &ins.oprs[t & ~SAME_AS];
1234 t = (*p)->opd[t & ~SAME_AS];
1235 }
1236
1237 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1238
1239 offs = o->offset;
1240 if (o->segment & SEG_RELATIVE) {
1241 offs += offset + length;
1242 /*
1243 * sort out wraparound
1244 */
1245 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1246 offs &= 0xffff;
1247 else if (segsize != 64)
1248 offs &= 0xffffffff;
1249
1250 /*
1251 * add sync marker, if autosync is on
1252 */
1253 if (autosync)
1254 add_sync(offs, 0L);
1255 }
1256
1257 if (t & COLON)
1258 colon = true;
1259 else
1260 colon = false;
1261
1262 if ((t & (REGISTER | FPUREG)) ||
1263 (o->segment & SEG_RMREG)) {
1264 enum reg_enum reg;
1265 reg = whichreg(t, o->basereg, ins.rex);
1266 if (t & TO)
1267 slen += snprintf(output + slen, outbufsize - slen, "to ");
1268 slen += snprintf(output + slen, outbufsize - slen, "%s",
1269 nasm_reg_names[reg-EXPR_REG_START]);
1270 } else if (!(UNITY & ~t)) {
1271 output[slen++] = '1';
1272 } else if (t & IMMEDIATE) {
1273 if (t & BITS8) {
1274 slen +=
1275 snprintf(output + slen, outbufsize - slen, "byte ");
1276 if (o->segment & SEG_SIGNED) {
1277 if (offs < 0) {
1278 offs *= -1;
1279 output[slen++] = '-';
1280 } else
1281 output[slen++] = '+';
1282 }
1283 } else if (t & BITS16) {
1284 slen +=
1285 snprintf(output + slen, outbufsize - slen, "word ");
1286 } else if (t & BITS32) {
1287 slen +=
1288 snprintf(output + slen, outbufsize - slen, "dword ");
1289 } else if (t & BITS64) {
1290 slen +=
1291 snprintf(output + slen, outbufsize - slen, "qword ");
1292 } else if (t & NEAR) {
1293 slen +=
1294 snprintf(output + slen, outbufsize - slen, "near ");
1295 } else if (t & SHORT) {
1296 slen +=
1297 snprintf(output + slen, outbufsize - slen, "short ");
1298 }
1299 slen +=
1300 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1301 offs);
1302 } else if (!(MEM_OFFS & ~t)) {
1303 slen +=
1304 snprintf(output + slen, outbufsize - slen,
1305 "[%s%s%s0x%"PRIx64"]",
1306 (segover ? segover : ""),
1307 (segover ? ":" : ""),
1308 (o->disp_size == 64 ? "qword " :
1309 o->disp_size == 32 ? "dword " :
1310 o->disp_size == 16 ? "word " : ""), offs);
1311 segover = NULL;
1312 } else if (is_class(REGMEM, t)) {
1313 int started = false;
1314 if (t & BITS8)
1315 slen +=
1316 snprintf(output + slen, outbufsize - slen, "byte ");
1317 if (t & BITS16)
1318 slen +=
1319 snprintf(output + slen, outbufsize - slen, "word ");
1320 if (t & BITS32)
1321 slen +=
1322 snprintf(output + slen, outbufsize - slen, "dword ");
1323 if (t & BITS64)
1324 slen +=
1325 snprintf(output + slen, outbufsize - slen, "qword ");
1326 if (t & BITS80)
1327 slen +=
1328 snprintf(output + slen, outbufsize - slen, "tword ");
1329 if (t & BITS128)
1330 slen +=
1331 snprintf(output + slen, outbufsize - slen, "oword ");
1332 if (t & BITS256)
1333 slen +=
1334 snprintf(output + slen, outbufsize - slen, "yword ");
1335 if (t & FAR)
1336 slen += snprintf(output + slen, outbufsize - slen, "far ");
1337 if (t & NEAR)
1338 slen +=
1339 snprintf(output + slen, outbufsize - slen, "near ");
1340 output[slen++] = '[';
1341 if (o->disp_size)
1342 slen += snprintf(output + slen, outbufsize - slen, "%s",
1343 (o->disp_size == 64 ? "qword " :
1344 o->disp_size == 32 ? "dword " :
1345 o->disp_size == 16 ? "word " :
1346 ""));
1347 if (o->eaflags & EAF_REL)
1348 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1349 if (segover) {
1350 slen +=
1351 snprintf(output + slen, outbufsize - slen, "%s:",
1352 segover);
1353 segover = NULL;
1354 }
1355 if (o->basereg != -1) {
1356 slen += snprintf(output + slen, outbufsize - slen, "%s",
1357 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1358 started = true;
1359 }
1360 if (o->indexreg != -1) {
1361 if (started)
1362 output[slen++] = '+';
1363 slen += snprintf(output + slen, outbufsize - slen, "%s",
1364 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1365 if (o->scale > 1)
1366 slen +=
1367 snprintf(output + slen, outbufsize - slen, "*%d",
1368 o->scale);
1369 started = true;
1370 }
1371
1372
1373 if (o->segment & SEG_DISP8) {
1374 const char *prefix;
1375 uint8_t offset = offs;
1376 if ((int8_t)offset < 0) {
1377 prefix = "-";
1378 offset = -offset;
1379 } else {
1380 prefix = "+";
1381 }
1382 slen +=
1383 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1384 prefix, offset);
1385 } else if (o->segment & SEG_DISP16) {
1386 const char *prefix;
1387 uint16_t offset = offs;
1388 if ((int16_t)offset < 0 && started) {
1389 offset = -offset;
1390 prefix = "-";
1391 } else {
1392 prefix = started ? "+" : "";
1393 }
1394 slen +=
1395 snprintf(output + slen, outbufsize - slen,
1396 "%s0x%"PRIx16"", prefix, offset);
1397 } else if (o->segment & SEG_DISP32) {
1398 if (prefix.asize == 64) {
1399 const char *prefix;
1400 uint64_t offset = (int64_t)(int32_t)offs;
1401 if ((int32_t)offs < 0 && started) {
1402 offset = -offset;
1403 prefix = "-";
1404 } else {
1405 prefix = started ? "+" : "";
1406 }
1407 slen +=
1408 snprintf(output + slen, outbufsize - slen,
1409 "%s0x%"PRIx64"", prefix, offset);
1410 } else {
1411 const char *prefix;
1412 uint32_t offset = offs;
1413 if ((int32_t) offset < 0 && started) {
1414 offset = -offset;
1415 prefix = "-";
1416 } else {
1417 prefix = started ? "+" : "";
1418 }
1419 slen +=
1420 snprintf(output + slen, outbufsize - slen,
1421 "%s0x%"PRIx32"", prefix, offset);
1422 }
1423 }
1424 output[slen++] = ']';
1425 } else {
1426 slen +=
1427 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1428 i);
1429 }
1430 }
1431 output[slen] = '\0';
1432 if (segover) { /* unused segment override */
1433 char *p = output;
1434 int count = slen + 1;
1435 while (count--)
1436 p[count + 3] = p[count];
1437 strncpy(output, segover, 2);
1438 output[2] = ' ';
1439 }
1440 return length;
1441 }
1442
1443 /*
1444 * This is called when we don't have a complete instruction. If it
1445 * is a standalone *single-byte* prefix show it as such, otherwise
1446 * print it as a literal.
1447 */
1448 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1449 {
1450 uint8_t byte = *data;
1451 const char *str = NULL;
1452
1453 switch (byte) {
1454 case 0xF2:
1455 str = "repne";
1456 break;
1457 case 0xF3:
1458 str = "rep";
1459 break;
1460 case 0x9B:
1461 str = "wait";
1462 break;
1463 case 0xF0:
1464 str = "lock";
1465 break;
1466 case 0x2E:
1467 str = "cs";
1468 break;
1469 case 0x36:
1470 str = "ss";
1471 break;
1472 case 0x3E:
1473 str = "ss";
1474 break;
1475 case 0x26:
1476 str = "es";
1477 break;
1478 case 0x64:
1479 str = "fs";
1480 break;
1481 case 0x65:
1482 str = "gs";
1483 break;
1484 case 0x66:
1485 str = (segsize == 16) ? "o32" : "o16";
1486 break;
1487 case 0x67:
1488 str = (segsize == 32) ? "a16" : "a32";
1489 break;
1490 case REX_P + 0x0:
1491 case REX_P + 0x1:
1492 case REX_P + 0x2:
1493 case REX_P + 0x3:
1494 case REX_P + 0x4:
1495 case REX_P + 0x5:
1496 case REX_P + 0x6:
1497 case REX_P + 0x7:
1498 case REX_P + 0x8:
1499 case REX_P + 0x9:
1500 case REX_P + 0xA:
1501 case REX_P + 0xB:
1502 case REX_P + 0xC:
1503 case REX_P + 0xD:
1504 case REX_P + 0xE:
1505 case REX_P + 0xF:
1506 if (segsize == 64) {
1507 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1508 (byte == REX_P) ? "" : ".",
1509 (byte & REX_W) ? "w" : "",
1510 (byte & REX_R) ? "r" : "",
1511 (byte & REX_X) ? "x" : "",
1512 (byte & REX_B) ? "b" : "");
1513 break;
1514 }
1515 /* else fall through */
1516 default:
1517 snprintf(output, outbufsize, "db 0x%02x", byte);
1518 break;
1519 }
1520
1521 if (str)
1522 snprintf(output, outbufsize, "%s", str);
1523
1524 return 1;
1525 }
Adding AVX-512 features