opflags.h

   1 /* ----------------------------------------------------------------------- *
   2  *
   3  *   Copyright 1996-2009 The NASM Authors - All Rights Reserved
   4  *   See the file AUTHORS included with the NASM distribution for
   5  *   the specific copyright holders.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following
   9  *   conditions are met:
  10  *
  11  *   * Redistributions of source code must retain the above copyright
  12  *     notice, this list of conditions and the following disclaimer.
  13  *   * Redistributions in binary form must reproduce the above
  14  *     copyright notice, this list of conditions and the following
  15  *     disclaimer in the documentation and/or other materials provided
  16  *     with the distribution.
  17  *
  18  *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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  20  *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  21  *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  22  *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  23  *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  29  *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  30  *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * ----------------------------------------------------------------------- */
  33
  34 /*
  35  * opflags.h - operand flags
  36  */
  37
  38 #ifndef NASM_OPFLAGS_H
  39 #define NASM_OPFLAGS_H
  40
  41 #include "compiler.h"
  42
  43 /*
  44  * Here we define the operand types. These are implemented as bit
  45  * masks, since some are subsets of others; e.g. AX in a MOV
  46  * instruction is a special operand type, whereas AX in other
  47  * contexts is just another 16-bit register. (Also, consider CL in
  48  * shift instructions, DX in OUT, etc.)
  49  *
  50  * The basic concept here is that
  51  *    (class & ~operand) == 0
  52  *
  53  * if and only if "operand" belongs to class type "class".
  54  *
  55  * The bits are assigned as follows:
  56  *
  57  * Bits 0-7, 23, 29: sizes
  58  *  0:  8 bits (BYTE)
  59  *  1: 16 bits (WORD)
  60  *  2: 32 bits (DWORD)
  61  *  3: 64 bits (QWORD)
  62  *  4: 80 bits (TWORD)
  63  *  5: FAR
  64  *  6: NEAR
  65  *  7: SHORT
  66  * 23: 256 bits (YWORD)
  67  * 29: 128 bits (OWORD)
  68  *
  69  * Bits 8-10 modifiers
  70  *  8: TO
  71  *  9: COLON
  72  * 10: STRICT
  73  *
  74  * Bits 12-15: type of operand
  75  * 12: REGISTER
  76  * 13: IMMEDIATE
  77  * 14: MEMORY (always has REGMEM attribute as well)
  78  * 15: REGMEM (valid EA operand)
  79  *
  80  * Bits 11, 16-19, 28: subclasses
  81  * With REG_CDT:
  82  * 16: REG_CREG (CRx)
  83  * 17: REG_DREG (DRx)
  84  * 18: REG_TREG (TRx)
  85
  86  * With REG_GPR:
  87  * 16: REG_ACCUM  (AL, AX, EAX, RAX)
  88  * 17: REG_COUNT  (CL, CX, ECX, RCX)
  89  * 18: REG_DATA   (DL, DX, EDX, RDX)
  90  * 19: REG_HIGH   (AH, CH, DH, BH)
  91  * 28: REG_NOTACC (not REG_ACCUM)
  92  *
  93  * With REG_SREG:
  94  * 16: REG_CS
  95  * 17: REG_DESS (DS, ES, SS)
  96  * 18: REG_FSGS
  97  * 19: REG_SEG67
  98  *
  99  * With FPUREG:
 100  * 16: FPU0
 101  *
 102  * With XMMREG:
 103  * 16: XMM0
 104  *
 105  * With YMMREG:
 106  * 16: YMM0
 107  *
 108  * With MEMORY:
 109  * 16: MEM_OFFS (this is a simple offset)
 110  * 17: IP_REL (IP-relative offset)
 111  *
 112  * With IMMEDIATE:
 113  * 16: UNITY (1)
 114  * 17: BYTENESS16 (-128..127)
 115  * 18: BYTENESS32 (-128..127)
 116  * 19: BYTENESS64 (-128..127)
 117  * 28: SDWORD64 (-2^31..2^31-1)
 118  * 11: UDWORD64 (0..2^32-1)
 119  *
 120  * Bits 20-22, 24-27: register classes
 121  * 20: REG_CDT (CRx, DRx, TRx)
 122  * 21: RM_GPR (REG_GPR) (integer register)
 123  * 22: REG_SREG
 124  * 24: FPUREG
 125  * 25: RM_MMX (MMXREG)
 126  * 26: RM_XMM (XMMREG)
 127  * 27: RM_YMM (YMMREG)
 128  *
 129  * 30: SAME_AS
 130  * Special flag only used in instruction patterns; means this operand
 131  * has to be identical to another operand.  Currently only supported
 132  * for registers.
 133  */
 134
 135 typedef uint32_t opflags_t;
 136
 137 /* Size, and other attributes, of the operand */
 138 #define BITS8           0x00000001U
 139 #define BITS16          0x00000002U
 140 #define BITS32          0x00000004U
 141 #define BITS64          0x00000008U   /* x64 and FPU only */
 142 #define BITS80          0x00000010U   /* FPU only */
 143 #define BITS128         0x20000000U
 144 #define BITS256         0x00800000U
 145 #define FAR             0x00000020U   /* grotty: this means 16:16 or */
 146                                        /* 16:32, like in CALL/JMP */
 147 #define NEAR            0x00000040U
 148 #define SHORT           0x00000080U   /* and this means what it says :) */
 149
 150 #define SIZE_MASK       0x208000FFU   /* all the size attributes */
 151
 152 /* Modifiers */
 153 #define MODIFIER_MASK   0x00000700U
 154 #define TO              0x00000100U   /* reverse effect in FADD, FSUB &c */
 155 #define COLON           0x00000200U   /* operand is followed by a colon */
 156 #define STRICT          0x00000400U   /* do not optimize this operand */
 157
 158 /* Type of operand: memory reference, register, etc. */
 159 #define OPTYPE_MASK     0x0000f000U
 160 #define REGISTER        0x00001000U   /* register number in 'basereg' */
 161 #define IMMEDIATE       0x00002000U
 162 #define MEMORY          0x0000c000U
 163 #define REGMEM          0x00008000U   /* for r/m, ie EA, operands */
 164
 165 #define is_class(class, op)     (!((opflags_t)(class) & ~(opflags_t)(op)))
 166
 167 #define IS_SREG(op)             is_class(REG_SREG, nasm_reg_flags[(op)])
 168 #define IS_FSGS(op)             is_class(REG_FSGS, nasm_reg_flags[(op)])
 169
 170 /* Register classes */
 171 #define REG_EA          0x00009000U   /* 'normal' reg, qualifies as EA */
 172 #define RM_GPR          0x00208000U   /* integer operand */
 173 #define REG_GPR         0x00209000U   /* integer register */
 174 #define REG8            0x00209001U   /*  8-bit GPR  */
 175 #define REG16           0x00209002U   /* 16-bit GPR */
 176 #define REG32           0x00209004U   /* 32-bit GPR */
 177 #define REG64           0x00209008U   /* 64-bit GPR */
 178 #define FPUREG          0x01001000U   /* floating point stack registers */
 179 #define FPU0            0x01011000U   /* FPU stack register zero */
 180 #define RM_MMX          0x02008000U   /* MMX operand */
 181 #define MMXREG          0x02009000U   /* MMX register */
 182 #define RM_XMM          0x04008000U   /* XMM (SSE) operand */
 183 #define XMMREG          0x04009000U   /* XMM (SSE) register */
 184 #define XMM0            0x04019000U   /* XMM register zero */
 185 #define RM_YMM          0x08008000U   /* YMM (AVX) operand */
 186 #define YMMREG          0x08009000U   /* YMM (AVX) register */
 187 #define YMM0            0x08019000U   /* YMM register zero */
 188 #define REG_CDT         0x00101004U   /* CRn, DRn and TRn */
 189 #define REG_CREG        0x00111004U   /* CRn */
 190 #define REG_DREG        0x00121004U   /* DRn */
 191 #define REG_TREG        0x00141004U   /* TRn */
 192 #define REG_SREG        0x00401002U   /* any segment register */
 193 #define REG_CS          0x00411002U   /* CS */
 194 #define REG_DESS        0x00421002U   /* DS, ES, SS */
 195 #define REG_FSGS        0x00441002U   /* FS, GS */
 196 #define REG_SEG67       0x00481002U   /* Unimplemented segment registers */
 197
 198 #define REG_RIP         0x00801008U   /* RIP relative addressing */
 199 #define REG_EIP         0x00801004U   /* EIP relative addressing */
 200
 201 /* Special GPRs */
 202 #define REG_SMASK       0x100f0800U   /* a mask for the following */
 203 #define REG_ACCUM       0x00219000U   /* accumulator: AL, AX, EAX, RAX */
 204 #define REG_AL          0x00219001U
 205 #define REG_AX          0x00219002U
 206 #define REG_EAX         0x00219004U
 207 #define REG_RAX         0x00219008U
 208 #define REG_COUNT       0x10229000U   /* counter: CL, CX, ECX, RCX */
 209 #define REG_CL          0x10229001U
 210 #define REG_CX          0x10229002U
 211 #define REG_ECX         0x10229004U
 212 #define REG_RCX         0x10229008U
 213 #define REG_DL          0x10249001U   /* data: DL, DX, EDX, RDX */
 214 #define REG_DX          0x10249002U
 215 #define REG_EDX         0x10249004U
 216 #define REG_RDX         0x10249008U
 217 #define REG_HIGH        0x10289001U   /* high regs: AH, CH, DH, BH */
 218 #define REG_NOTACC      0x10000000U   /* non-accumulator register */
 219 #define REG8NA          0x10209001U   /*  8-bit non-acc GPR  */
 220 #define REG16NA         0x10209002U   /* 16-bit non-acc GPR */
 221 #define REG32NA         0x10209004U   /* 32-bit non-acc GPR */
 222 #define REG64NA         0x10209008U   /* 64-bit non-acc GPR */
 223
 224 /* special types of EAs */
 225 #define MEM_OFFS        0x0001c000U   /* simple [address] offset - absolute! */
 226 #define IP_REL          0x0002c000U   /* IP-relative offset */
 227
 228 /* memory which matches any type of r/m operand */
 229 #define MEMORY_ANY      (MEMORY|RM_GPR|RM_MMX|RM_XMM|RM_YMM)
 230
 231 /* special type of immediate operand */
 232 #define UNITY           0x00012000U   /* for shift/rotate instructions */
 233 #define SBYTE16         0x00022000U   /* for op r16,immediate instrs. */
 234 #define SBYTE32         0x00042000U   /* for op r32,immediate instrs. */
 235 #define SBYTE64         0x00082000U   /* for op r64,immediate instrs. */
 236 #define BYTENESS        0x000e0000U   /* for testing for byteness */
 237 #define SDWORD64        0x10002000U   /* for op r64,simm32 instrs. */
 238 #define UDWORD64        0x00002800U   /* for op r64,uimm32 instrs. */
 239
 240 /* special flags */
 241 #define SAME_AS         0x40000000U
 242
 243 #endif /* NASM_OPFLAGS_H */