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preproc: Convert tabs to spaces
[nasm/externdefs.git] / assemble.c
blob7ba38693d76d5d978cf61de190591847ae4e521c
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2014 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - the position of index register operand in MIB (BND insns)
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \172\ab - the register number from operand a in bits 7..4, with
64 * the 4-bit immediate from operand b in bits 3..0.
65 * \173\xab - the register number from operand a in bits 7..4, with
66 * the value b in bits 3..0.
67 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
68 * an arbitrary value in bits 3..0 (assembled as zero.)
69 * \2ab - a ModRM, calculated on EA in operand a, with the spare
70 * field equal to digit b.
71 *
72 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
73 * V field taken from operand 0..3.
74 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
75 * V field set to 1111b.
76 * EVEX prefixes are followed by the sequence:
77 * \cm\wlp\tup where cm is:
78 * cc 000 0mm
79 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
80 * and wlp is:
81 * 00 wwl lpp
82 * [l0] ll = 0 (.128, .lz)
83 * [l1] ll = 1 (.256)
84 * [l2] ll = 2 (.512)
85 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
86 *
87 * [w0] ww = 0 for W = 0
88 * [w1] ww = 1 for W = 1
89 * [wig] ww = 2 for W don't care (always assembled as 0)
90 * [ww] ww = 3 for W used as REX.W
91 *
92 * [p0] pp = 0 for no prefix
93 * [60] pp = 1 for legacy prefix 60
94 * [f3] pp = 2
95 * [f2] pp = 3
96 *
97 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
98 * (compressed displacement encoding)
99 *
100 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
101 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
102 * V field taken from operand 0..3.
103 * \270 - this instruction uses VEX/XOP rather than REX, with the
104 * V field set to 1111b.
105 *
106 * VEX/XOP prefixes are followed by the sequence:
107 * \tmm\wlp where mm is the M field; and wlp is:
108 * 00 wwl lpp
109 * [l0] ll = 0 for L = 0 (.128, .lz)
110 * [l1] ll = 1 for L = 1 (.256)
111 * [lig] ll = 2 for L don't care (always assembled as 0)
112 *
113 * [w0] ww = 0 for W = 0
114 * [w1 ] ww = 1 for W = 1
115 * [wig] ww = 2 for W don't care (always assembled as 0)
116 * [ww] ww = 3 for W used as REX.W
117 *
118 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
119 *
120 * \271 - instruction takes XRELEASE (F3) with or without lock
121 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
122 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
123 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
124 * to the operand size (if o16/o32/o64 present) or the bit size
125 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
126 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
127 * \312 - (disassembler only) invalid with non-default address size.
128 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
129 * \314 - (disassembler only) invalid with REX.B
130 * \315 - (disassembler only) invalid with REX.X
131 * \316 - (disassembler only) invalid with REX.R
132 * \317 - (disassembler only) invalid with REX.W
133 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
134 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
135 * \322 - indicates that this instruction is only valid when the
136 * operand size is the default (instruction to disassembler,
137 * generates no code in the assembler)
138 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
139 * \324 - indicates 64-bit operand size requiring REX prefix.
140 * \325 - instruction which always uses spl/bpl/sil/dil
141 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
142 disassembler only; for SSE instructions.
143 * \330 - a literal byte follows in the code stream, to be added
144 * to the condition code value of the instruction.
145 * \331 - instruction not valid with REP prefix. Hint for
146 * disassembler only; for SSE instructions.
147 * \332 - REP prefix (0xF2 byte) used as opcode extension.
148 * \333 - REP prefix (0xF3 byte) used as opcode extension.
149 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
150 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
151 * \336 - force a REP(E) prefix (0xF3) even if not specified.
152 * \337 - force a REPNE prefix (0xF2) even if not specified.
153 * \336-\337 are still listed as prefixes in the disassembler.
154 * \340 - reserve <operand 0> bytes of uninitialized storage.
155 * Operand 0 had better be a segmentless constant.
156 * \341 - this instruction needs a WAIT "prefix"
157 * \360 - no SSE prefix (== \364\331)
158 * \361 - 66 SSE prefix (== \366\331)
159 * \364 - operand-size prefix (0x66) not permitted
160 * \365 - address-size prefix (0x67) not permitted
161 * \366 - operand-size prefix (0x66) used as opcode extension
162 * \367 - address-size prefix (0x67) used as opcode extension
163 * \370,\371 - match only if operand 0 meets byte jump criteria.
164 * 370 is used for Jcc, 371 is used for JMP.
165 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
166 * used for conditional jump over longer jump
167 * \374 - this instruction takes an XMM VSIB memory EA
168 * \375 - this instruction takes an YMM VSIB memory EA
169 * \376 - this instruction takes an ZMM VSIB memory EA
170 */
171
172 #include "compiler.h"
173
174 #include <stdio.h>
175 #include <string.h>
176 #include <stdlib.h>
177 #include <inttypes.h>
178
179 #include "nasm.h"
180 #include "nasmlib.h"
181 #include "assemble.h"
182 #include "insns.h"
183 #include "tables.h"
184 #include "disp8.h"
185
186 enum match_result {
187 /*
188 * Matching errors. These should be sorted so that more specific
189 * errors come later in the sequence.
190 */
191 MERR_INVALOP,
192 MERR_OPSIZEMISSING,
193 MERR_OPSIZEMISMATCH,
194 MERR_BRNUMMISMATCH,
195 MERR_BADCPU,
196 MERR_BADMODE,
197 MERR_BADHLE,
198 MERR_ENCMISMATCH,
199 MERR_BADBND,
200 MERR_BADREPNE,
201 /*
202 * Matching success; the conditional ones first
203 */
204 MOK_JUMP, /* Matching OK but needs jmp_match() */
205 MOK_GOOD /* Matching unconditionally OK */
206 };
207
208 typedef struct {
209 enum ea_type type; /* what kind of EA is this? */
210 int sib_present; /* is a SIB byte necessary? */
211 int bytes; /* # of bytes of offset needed */
212 int size; /* lazy - this is sib+bytes+1 */
213 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
214 int8_t disp8; /* compressed displacement for EVEX */
215 } ea;
216
217 #define GEN_SIB(scale, index, base) \
218 (((scale) << 6) | ((index) << 3) | ((base)))
219
220 #define GEN_MODRM(mod, reg, rm) \
221 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
222
223 static iflag_t cpu; /* cpu level received from nasm.c */
224 static efunc errfunc;
225 static struct ofmt *outfmt;
226 static ListGen *list;
227
228 static int64_t calcsize(int32_t, int64_t, int, insn *,
229 const struct itemplate *);
230 static void gencode(int32_t segment, int64_t offset, int bits,
231 insn * ins, const struct itemplate *temp,
232 int64_t insn_end);
233 static enum match_result find_match(const struct itemplate **tempp,
234 insn *instruction,
235 int32_t segment, int64_t offset, int bits);
236 static enum match_result matches(const struct itemplate *, insn *, int bits);
237 static opflags_t regflag(const operand *);
238 static int32_t regval(const operand *);
239 static int rexflags(int, opflags_t, int);
240 static int op_rexflags(const operand *, int);
241 static int op_evexflags(const operand *, int, uint8_t);
242 static void add_asp(insn *, int);
243
244 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
245
246 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
247 {
248 return ins->prefixes[pos] == prefix;
249 }
250
251 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
252 {
253 if (ins->prefixes[pos])
254 errfunc(ERR_NONFATAL, "invalid %s prefix",
255 prefix_name(ins->prefixes[pos]));
256 }
257
258 static const char *size_name(int size)
259 {
260 switch (size) {
261 case 1:
262 return "byte";
263 case 2:
264 return "word";
265 case 4:
266 return "dword";
267 case 8:
268 return "qword";
269 case 10:
270 return "tword";
271 case 16:
272 return "oword";
273 case 32:
274 return "yword";
275 case 64:
276 return "zword";
277 default:
278 return "???";
279 }
280 }
281
282 static void warn_overflow(int pass, int size)
283 {
284 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
285 "%s data exceeds bounds", size_name(size));
286 }
287
288 static void warn_overflow_const(int64_t data, int size)
289 {
290 if (overflow_general(data, size))
291 warn_overflow(ERR_PASS1, size);
292 }
293
294 static void warn_overflow_opd(const struct operand *o, int size)
295 {
296 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
297 if (overflow_general(o->offset, size))
298 warn_overflow(ERR_PASS2, size);
299 }
300 }
301
302 /*
303 * This routine wrappers the real output format's output routine,
304 * in order to pass a copy of the data off to the listing file
305 * generator at the same time.
306 */
307 static void out(int64_t offset, int32_t segto, const void *data,
308 enum out_type type, uint64_t size,
309 int32_t segment, int32_t wrt)
310 {
311 static int32_t lineno = 0; /* static!!! */
312 static char *lnfname = NULL;
313 uint8_t p[8];
314
315 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
316 /*
317 * This is a non-relocated address, and we're going to
318 * convert it into RAWDATA format.
319 */
320 uint8_t *q = p;
321
322 size = abs((int)size);
323 if (size > 8) {
324 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
325 return;
326 }
327
328 WRITEADDR(q, *(int64_t *)data, size);
329 data = p;
330 type = OUT_RAWDATA;
331 }
332
333 list->output(offset, data, type, size);
334
335 /*
336 * this call to src_get determines when we call the
337 * debug-format-specific "linenum" function
338 * it updates lineno and lnfname to the current values
339 * returning 0 if "same as last time", -2 if lnfname
340 * changed, and the amount by which lineno changed,
341 * if it did. thus, these variables must be static
342 */
343
344 if (src_get(&lineno, &lnfname))
345 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
346
347 outfmt->output(segto, data, type, size, segment, wrt);
348 }
349
350 static void out_imm8(int64_t offset, int32_t segment,
351 struct operand *opx, int asize)
352 {
353 if (opx->segment != NO_SEG) {
354 uint64_t data = opx->offset;
355 out(offset, segment, &data, OUT_ADDRESS, asize, opx->segment, opx->wrt);
356 } else {
357 uint8_t byte = opx->offset;
358 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
359 }
360 }
361
362 static bool jmp_match(int32_t segment, int64_t offset, int bits,
363 insn * ins, const struct itemplate *temp)
364 {
365 int64_t isize;
366 const uint8_t *code = temp->code;
367 uint8_t c = code[0];
368 bool is_byte;
369
370 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
371 return false;
372 if (!optimizing)
373 return false;
374 if (optimizing < 0 && c == 0371)
375 return false;
376
377 isize = calcsize(segment, offset, bits, ins, temp);
378
379 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
380 /* Be optimistic in pass 1 */
381 return true;
382
383 if (ins->oprs[0].segment != segment)
384 return false;
385
386 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
387 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
388
389 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
390 /* jmp short (opcode eb) cannot be used with bnd prefix. */
391 ins->prefixes[PPS_REP] = P_none;
392 errfunc(ERR_WARNING | ERR_WARN_BND | ERR_PASS2 ,
393 "jmp short does not init bnd regs - bnd prefix dropped.");
394 }
395
396 return is_byte;
397 }
398
399 int64_t assemble(int32_t segment, int64_t offset, int bits, iflag_t cp,
400 insn * instruction, struct ofmt *output, efunc error,
401 ListGen * listgen)
402 {
403 const struct itemplate *temp;
404 int j;
405 enum match_result m;
406 int64_t insn_end;
407 int32_t itimes;
408 int64_t start = offset;
409 int64_t wsize; /* size for DB etc. */
410
411 errfunc = error; /* to pass to other functions */
412 cpu = cp;
413 outfmt = output; /* likewise */
414 list = listgen; /* and again */
415
416 wsize = idata_bytes(instruction->opcode);
417 if (wsize == -1)
418 return 0;
419
420 if (wsize) {
421 extop *e;
422 int32_t t = instruction->times;
423 if (t < 0)
424 errfunc(ERR_PANIC,
425 "instruction->times < 0 (%ld) in assemble()", t);
426
427 while (t--) { /* repeat TIMES times */
428 list_for_each(e, instruction->eops) {
429 if (e->type == EOT_DB_NUMBER) {
430 if (wsize > 8) {
431 errfunc(ERR_NONFATAL,
432 "integer supplied to a DT, DO or DY"
433 " instruction");
434 } else {
435 out(offset, segment, &e->offset,
436 OUT_ADDRESS, wsize, e->segment, e->wrt);
437 offset += wsize;
438 }
439 } else if (e->type == EOT_DB_STRING ||
440 e->type == EOT_DB_STRING_FREE) {
441 int align;
442
443 out(offset, segment, e->stringval,
444 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
445 align = e->stringlen % wsize;
446
447 if (align) {
448 align = wsize - align;
449 out(offset, segment, zero_buffer,
450 OUT_RAWDATA, align, NO_SEG, NO_SEG);
451 }
452 offset += e->stringlen + align;
453 }
454 }
455 if (t > 0 && t == instruction->times - 1) {
456 /*
457 * Dummy call to list->output to give the offset to the
458 * listing module.
459 */
460 list->output(offset, NULL, OUT_RAWDATA, 0);
461 list->uplevel(LIST_TIMES);
462 }
463 }
464 if (instruction->times > 1)
465 list->downlevel(LIST_TIMES);
466 return offset - start;
467 }
468
469 if (instruction->opcode == I_INCBIN) {
470 const char *fname = instruction->eops->stringval;
471 FILE *fp;
472
473 fp = fopen(fname, "rb");
474 if (!fp) {
475 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
476 fname);
477 } else if (fseek(fp, 0L, SEEK_END) < 0) {
478 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
479 fname);
480 fclose(fp);
481 } else {
482 static char buf[4096];
483 size_t t = instruction->times;
484 size_t base = 0;
485 size_t len;
486
487 len = ftell(fp);
488 if (instruction->eops->next) {
489 base = instruction->eops->next->offset;
490 len -= base;
491 if (instruction->eops->next->next &&
492 len > (size_t)instruction->eops->next->next->offset)
493 len = (size_t)instruction->eops->next->next->offset;
494 }
495 /*
496 * Dummy call to list->output to give the offset to the
497 * listing module.
498 */
499 list->output(offset, NULL, OUT_RAWDATA, 0);
500 list->uplevel(LIST_INCBIN);
501 while (t--) {
502 size_t l;
503
504 fseek(fp, base, SEEK_SET);
505 l = len;
506 while (l > 0) {
507 int32_t m;
508 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
509 if (!m) {
510 /*
511 * This shouldn't happen unless the file
512 * actually changes while we are reading
513 * it.
514 */
515 error(ERR_NONFATAL,
516 "`incbin': unexpected EOF while"
517 " reading file `%s'", fname);
518 t = 0; /* Try to exit cleanly */
519 break;
520 }
521 out(offset, segment, buf, OUT_RAWDATA, m,
522 NO_SEG, NO_SEG);
523 l -= m;
524 }
525 }
526 list->downlevel(LIST_INCBIN);
527 if (instruction->times > 1) {
528 /*
529 * Dummy call to list->output to give the offset to the
530 * listing module.
531 */
532 list->output(offset, NULL, OUT_RAWDATA, 0);
533 list->uplevel(LIST_TIMES);
534 list->downlevel(LIST_TIMES);
535 }
536 fclose(fp);
537 return instruction->times * len;
538 }
539 return 0; /* if we're here, there's an error */
540 }
541
542 /* Check to see if we need an address-size prefix */
543 add_asp(instruction, bits);
544
545 m = find_match(&temp, instruction, segment, offset, bits);
546
547 if (m == MOK_GOOD) {
548 /* Matches! */
549 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
550 itimes = instruction->times;
551 if (insn_size < 0) /* shouldn't be, on pass two */
552 error(ERR_PANIC, "errors made it through from pass one");
553 else
554 while (itimes--) {
555 for (j = 0; j < MAXPREFIX; j++) {
556 uint8_t c = 0;
557 switch (instruction->prefixes[j]) {
558 case P_WAIT:
559 c = 0x9B;
560 break;
561 case P_LOCK:
562 c = 0xF0;
563 break;
564 case P_REPNE:
565 case P_REPNZ:
566 case P_XACQUIRE:
567 case P_BND:
568 c = 0xF2;
569 break;
570 case P_REPE:
571 case P_REPZ:
572 case P_REP:
573 case P_XRELEASE:
574 c = 0xF3;
575 break;
576 case R_CS:
577 if (bits == 64) {
578 error(ERR_WARNING | ERR_PASS2,
579 "cs segment base generated, but will be ignored in 64-bit mode");
580 }
581 c = 0x2E;
582 break;
583 case R_DS:
584 if (bits == 64) {
585 error(ERR_WARNING | ERR_PASS2,
586 "ds segment base generated, but will be ignored in 64-bit mode");
587 }
588 c = 0x3E;
589 break;
590 case R_ES:
591 if (bits == 64) {
592 error(ERR_WARNING | ERR_PASS2,
593 "es segment base generated, but will be ignored in 64-bit mode");
594 }
595 c = 0x26;
596 break;
597 case R_FS:
598 c = 0x64;
599 break;
600 case R_GS:
601 c = 0x65;
602 break;
603 case R_SS:
604 if (bits == 64) {
605 error(ERR_WARNING | ERR_PASS2,
606 "ss segment base generated, but will be ignored in 64-bit mode");
607 }
608 c = 0x36;
609 break;
610 case R_SEGR6:
611 case R_SEGR7:
612 error(ERR_NONFATAL,
613 "segr6 and segr7 cannot be used as prefixes");
614 break;
615 case P_A16:
616 if (bits == 64) {
617 error(ERR_NONFATAL,
618 "16-bit addressing is not supported "
619 "in 64-bit mode");
620 } else if (bits != 16)
621 c = 0x67;
622 break;
623 case P_A32:
624 if (bits != 32)
625 c = 0x67;
626 break;
627 case P_A64:
628 if (bits != 64) {
629 error(ERR_NONFATAL,
630 "64-bit addressing is only supported "
631 "in 64-bit mode");
632 }
633 break;
634 case P_ASP:
635 c = 0x67;
636 break;
637 case P_O16:
638 if (bits != 16)
639 c = 0x66;
640 break;
641 case P_O32:
642 if (bits == 16)
643 c = 0x66;
644 break;
645 case P_O64:
646 /* REX.W */
647 break;
648 case P_OSP:
649 c = 0x66;
650 break;
651 case P_EVEX:
652 case P_VEX3:
653 case P_VEX2:
654 case P_NOBND:
655 case P_none:
656 break;
657 default:
658 error(ERR_PANIC, "invalid instruction prefix");
659 }
660 if (c != 0) {
661 out(offset, segment, &c, OUT_RAWDATA, 1,
662 NO_SEG, NO_SEG);
663 offset++;
664 }
665 }
666 insn_end = offset + insn_size;
667 gencode(segment, offset, bits, instruction,
668 temp, insn_end);
669 offset += insn_size;
670 if (itimes > 0 && itimes == instruction->times - 1) {
671 /*
672 * Dummy call to list->output to give the offset to the
673 * listing module.
674 */
675 list->output(offset, NULL, OUT_RAWDATA, 0);
676 list->uplevel(LIST_TIMES);
677 }
678 }
679 if (instruction->times > 1)
680 list->downlevel(LIST_TIMES);
681 return offset - start;
682 } else {
683 /* No match */
684 switch (m) {
685 case MERR_OPSIZEMISSING:
686 error(ERR_NONFATAL, "operation size not specified");
687 break;
688 case MERR_OPSIZEMISMATCH:
689 error(ERR_NONFATAL, "mismatch in operand sizes");
690 break;
691 case MERR_BRNUMMISMATCH:
692 error(ERR_NONFATAL,
693 "mismatch in the number of broadcasting elements");
694 break;
695 case MERR_BADCPU:
696 error(ERR_NONFATAL, "no instruction for this cpu level");
697 break;
698 case MERR_BADMODE:
699 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
700 bits);
701 break;
702 case MERR_ENCMISMATCH:
703 error(ERR_NONFATAL, "specific encoding scheme not available");
704 break;
705 case MERR_BADBND:
706 error(ERR_NONFATAL, "bnd prefix is not allowed");
707 break;
708 case MERR_BADREPNE:
709 error(ERR_NONFATAL, "%s prefix is not allowed",
710 (has_prefix(instruction, PPS_REP, P_REPNE) ?
711 "repne" : "repnz"));
712 break;
713 default:
714 error(ERR_NONFATAL,
715 "invalid combination of opcode and operands");
716 break;
717 }
718 }
719 return 0;
720 }
721
722 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflag_t cp,
723 insn * instruction, efunc error)
724 {
725 const struct itemplate *temp;
726 enum match_result m;
727
728 errfunc = error; /* to pass to other functions */
729 cpu = cp;
730
731 if (instruction->opcode == I_none)
732 return 0;
733
734 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
735 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
736 instruction->opcode == I_DT || instruction->opcode == I_DO ||
737 instruction->opcode == I_DY) {
738 extop *e;
739 int32_t isize, osize, wsize;
740
741 isize = 0;
742 wsize = idata_bytes(instruction->opcode);
743
744 list_for_each(e, instruction->eops) {
745 int32_t align;
746
747 osize = 0;
748 if (e->type == EOT_DB_NUMBER) {
749 osize = 1;
750 warn_overflow_const(e->offset, wsize);
751 } else if (e->type == EOT_DB_STRING ||
752 e->type == EOT_DB_STRING_FREE)
753 osize = e->stringlen;
754
755 align = (-osize) % wsize;
756 if (align < 0)
757 align += wsize;
758 isize += osize + align;
759 }
760 return isize * instruction->times;
761 }
762
763 if (instruction->opcode == I_INCBIN) {
764 const char *fname = instruction->eops->stringval;
765 FILE *fp;
766 int64_t val = 0;
767 size_t len;
768
769 fp = fopen(fname, "rb");
770 if (!fp)
771 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
772 fname);
773 else if (fseek(fp, 0L, SEEK_END) < 0)
774 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
775 fname);
776 else {
777 len = ftell(fp);
778 if (instruction->eops->next) {
779 len -= instruction->eops->next->offset;
780 if (instruction->eops->next->next &&
781 len > (size_t)instruction->eops->next->next->offset) {
782 len = (size_t)instruction->eops->next->next->offset;
783 }
784 }
785 val = instruction->times * len;
786 }
787 if (fp)
788 fclose(fp);
789 return val;
790 }
791
792 /* Check to see if we need an address-size prefix */
793 add_asp(instruction, bits);
794
795 m = find_match(&temp, instruction, segment, offset, bits);
796 if (m == MOK_GOOD) {
797 /* we've matched an instruction. */
798 int64_t isize;
799 int j;
800
801 isize = calcsize(segment, offset, bits, instruction, temp);
802 if (isize < 0)
803 return -1;
804 for (j = 0; j < MAXPREFIX; j++) {
805 switch (instruction->prefixes[j]) {
806 case P_A16:
807 if (bits != 16)
808 isize++;
809 break;
810 case P_A32:
811 if (bits != 32)
812 isize++;
813 break;
814 case P_O16:
815 if (bits != 16)
816 isize++;
817 break;
818 case P_O32:
819 if (bits == 16)
820 isize++;
821 break;
822 case P_A64:
823 case P_O64:
824 case P_EVEX:
825 case P_VEX3:
826 case P_VEX2:
827 case P_NOBND:
828 case P_none:
829 break;
830 default:
831 isize++;
832 break;
833 }
834 }
835 return isize * instruction->times;
836 } else {
837 return -1; /* didn't match any instruction */
838 }
839 }
840
841 static void bad_hle_warn(const insn * ins, uint8_t hleok)
842 {
843 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
844 enum whatwarn { w_none, w_lock, w_inval } ww;
845 static const enum whatwarn warn[2][4] =
846 {
847 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
848 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
849 };
850 unsigned int n;
851
852 n = (unsigned int)rep_pfx - P_XACQUIRE;
853 if (n > 1)
854 return; /* Not XACQUIRE/XRELEASE */
855
856 ww = warn[n][hleok];
857 if (!is_class(MEMORY, ins->oprs[0].type))
858 ww = w_inval; /* HLE requires operand 0 to be memory */
859
860 switch (ww) {
861 case w_none:
862 break;
863
864 case w_lock:
865 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
866 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
867 "%s with this instruction requires lock",
868 prefix_name(rep_pfx));
869 }
870 break;
871
872 case w_inval:
873 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
874 "%s invalid with this instruction",
875 prefix_name(rep_pfx));
876 break;
877 }
878 }
879
880 /* Common construct */
881 #define case3(x) case (x): case (x)+1: case (x)+2
882 #define case4(x) case3(x): case (x)+3
883
884 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
885 insn * ins, const struct itemplate *temp)
886 {
887 const uint8_t *codes = temp->code;
888 int64_t length = 0;
889 uint8_t c;
890 int rex_mask = ~0;
891 int op1, op2;
892 struct operand *opx;
893 uint8_t opex = 0;
894 enum ea_type eat;
895 uint8_t hleok = 0;
896 bool lockcheck = true;
897 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
898
899 ins->rex = 0; /* Ensure REX is reset */
900 eat = EA_SCALAR; /* Expect a scalar EA */
901 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
902
903 if (ins->prefixes[PPS_OSIZE] == P_O64)
904 ins->rex |= REX_W;
905
906 (void)segment; /* Don't warn that this parameter is unused */
907 (void)offset; /* Don't warn that this parameter is unused */
908
909 while (*codes) {
910 c = *codes++;
911 op1 = (c & 3) + ((opex & 1) << 2);
912 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
913 opx = &ins->oprs[op1];
914 opex = 0; /* For the next iteration */
915
916 switch (c) {
917 case4(01):
918 codes += c, length += c;
919 break;
920
921 case3(05):
922 opex = c;
923 break;
924
925 case4(010):
926 ins->rex |=
927 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
928 codes++, length++;
929 break;
930
931 case4(014):
932 /* this is an index reg of MIB operand */
933 mib_index = opx->basereg;
934 break;
935
936 case4(020):
937 case4(024):
938 length++;
939 break;
940
941 case4(030):
942 length += 2;
943 break;
944
945 case4(034):
946 if (opx->type & (BITS16 | BITS32 | BITS64))
947 length += (opx->type & BITS16) ? 2 : 4;
948 else
949 length += (bits == 16) ? 2 : 4;
950 break;
951
952 case4(040):
953 length += 4;
954 break;
955
956 case4(044):
957 length += ins->addr_size >> 3;
958 break;
959
960 case4(050):
961 length++;
962 break;
963
964 case4(054):
965 length += 8; /* MOV reg64/imm */
966 break;
967
968 case4(060):
969 length += 2;
970 break;
971
972 case4(064):
973 if (opx->type & (BITS16 | BITS32 | BITS64))
974 length += (opx->type & BITS16) ? 2 : 4;
975 else
976 length += (bits == 16) ? 2 : 4;
977 break;
978
979 case4(070):
980 length += 4;
981 break;
982
983 case4(074):
984 length += 2;
985 break;
986
987 case 0172:
988 case 0173:
989 codes++;
990 length++;
991 break;
992
993 case4(0174):
994 length++;
995 break;
996
997 case4(0240):
998 ins->rex |= REX_EV;
999 ins->vexreg = regval(opx);
1000 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
1001 ins->vex_cm = *codes++;
1002 ins->vex_wlp = *codes++;
1003 ins->evex_tuple = (*codes++ - 0300);
1004 break;
1005
1006 case 0250:
1007 ins->rex |= REX_EV;
1008 ins->vexreg = 0;
1009 ins->vex_cm = *codes++;
1010 ins->vex_wlp = *codes++;
1011 ins->evex_tuple = (*codes++ - 0300);
1012 break;
1013
1014 case4(0254):
1015 length += 4;
1016 break;
1017
1018 case4(0260):
1019 ins->rex |= REX_V;
1020 ins->vexreg = regval(opx);
1021 ins->vex_cm = *codes++;
1022 ins->vex_wlp = *codes++;
1023 break;
1024
1025 case 0270:
1026 ins->rex |= REX_V;
1027 ins->vexreg = 0;
1028 ins->vex_cm = *codes++;
1029 ins->vex_wlp = *codes++;
1030 break;
1031
1032 case3(0271):
1033 hleok = c & 3;
1034 break;
1035
1036 case4(0274):
1037 length++;
1038 break;
1039
1040 case4(0300):
1041 break;
1042
1043 case 0310:
1044 if (bits == 64)
1045 return -1;
1046 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1047 break;
1048
1049 case 0311:
1050 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1051 break;
1052
1053 case 0312:
1054 break;
1055
1056 case 0313:
1057 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1058 has_prefix(ins, PPS_ASIZE, P_A32))
1059 return -1;
1060 break;
1061
1062 case4(0314):
1063 break;
1064
1065 case 0320:
1066 {
1067 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1068 if (pfx == P_O16)
1069 break;
1070 if (pfx != P_none)
1071 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1072 else
1073 ins->prefixes[PPS_OSIZE] = P_O16;
1074 break;
1075 }
1076
1077 case 0321:
1078 {
1079 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1080 if (pfx == P_O32)
1081 break;
1082 if (pfx != P_none)
1083 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1084 else
1085 ins->prefixes[PPS_OSIZE] = P_O32;
1086 break;
1087 }
1088
1089 case 0322:
1090 break;
1091
1092 case 0323:
1093 rex_mask &= ~REX_W;
1094 break;
1095
1096 case 0324:
1097 ins->rex |= REX_W;
1098 break;
1099
1100 case 0325:
1101 ins->rex |= REX_NH;
1102 break;
1103
1104 case 0326:
1105 break;
1106
1107 case 0330:
1108 codes++, length++;
1109 break;
1110
1111 case 0331:
1112 break;
1113
1114 case 0332:
1115 case 0333:
1116 length++;
1117 break;
1118
1119 case 0334:
1120 ins->rex |= REX_L;
1121 break;
1122
1123 case 0335:
1124 break;
1125
1126 case 0336:
1127 if (!ins->prefixes[PPS_REP])
1128 ins->prefixes[PPS_REP] = P_REP;
1129 break;
1130
1131 case 0337:
1132 if (!ins->prefixes[PPS_REP])
1133 ins->prefixes[PPS_REP] = P_REPNE;
1134 break;
1135
1136 case 0340:
1137 if (ins->oprs[0].segment != NO_SEG)
1138 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1139 " quantity of BSS space");
1140 else
1141 length += ins->oprs[0].offset;
1142 break;
1143
1144 case 0341:
1145 if (!ins->prefixes[PPS_WAIT])
1146 ins->prefixes[PPS_WAIT] = P_WAIT;
1147 break;
1148
1149 case 0360:
1150 break;
1151
1152 case 0361:
1153 length++;
1154 break;
1155
1156 case 0364:
1157 case 0365:
1158 break;
1159
1160 case 0366:
1161 case 0367:
1162 length++;
1163 break;
1164
1165 case 0370:
1166 case 0371:
1167 break;
1168
1169 case 0373:
1170 length++;
1171 break;
1172
1173 case 0374:
1174 eat = EA_XMMVSIB;
1175 break;
1176
1177 case 0375:
1178 eat = EA_YMMVSIB;
1179 break;
1180
1181 case 0376:
1182 eat = EA_ZMMVSIB;
1183 break;
1184
1185 case4(0100):
1186 case4(0110):
1187 case4(0120):
1188 case4(0130):
1189 case4(0200):
1190 case4(0204):
1191 case4(0210):
1192 case4(0214):
1193 case4(0220):
1194 case4(0224):
1195 case4(0230):
1196 case4(0234):
1197 {
1198 ea ea_data;
1199 int rfield;
1200 opflags_t rflags;
1201 struct operand *opy = &ins->oprs[op2];
1202 struct operand *op_er_sae;
1203
1204 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1205
1206 if (c <= 0177) {
1207 /* pick rfield from operand b (opx) */
1208 rflags = regflag(opx);
1209 rfield = nasm_regvals[opx->basereg];
1210 } else {
1211 rflags = 0;
1212 rfield = c & 7;
1213 }
1214
1215 /* EVEX.b1 : evex_brerop contains the operand position */
1216 op_er_sae = (ins->evex_brerop >= 0 ?
1217 &ins->oprs[ins->evex_brerop] : NULL);
1218
1219 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1220 /* set EVEX.b */
1221 ins->evex_p[2] |= EVEX_P2B;
1222 if (op_er_sae->decoflags & ER) {
1223 /* set EVEX.RC (rounding control) */
1224 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1225 & EVEX_P2RC;
1226 }
1227 } else {
1228 /* set EVEX.L'L (vector length) */
1229 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1230 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1231 if (opy->decoflags & BRDCAST_MASK) {
1232 /* set EVEX.b */
1233 ins->evex_p[2] |= EVEX_P2B;
1234 }
1235 }
1236
1237 if (itemp_has(temp, IF_MIB)) {
1238 opy->eaflags |= EAF_MIB;
1239 /*
1240 * if a separate form of MIB (ICC style) is used,
1241 * the index reg info is merged into mem operand
1242 */
1243 if (mib_index != R_none) {
1244 opy->indexreg = mib_index;
1245 opy->scale = 1;
1246 opy->hintbase = mib_index;
1247 opy->hinttype = EAH_NOTBASE;
1248 }
1249 }
1250
1251 if (process_ea(opy, &ea_data, bits,
1252 rfield, rflags, ins) != eat) {
1253 errfunc(ERR_NONFATAL, "invalid effective address");
1254 return -1;
1255 } else {
1256 ins->rex |= ea_data.rex;
1257 length += ea_data.size;
1258 }
1259 }
1260 break;
1261
1262 default:
1263 errfunc(ERR_PANIC, "internal instruction table corrupt"
1264 ": instruction code \\%o (0x%02X) given", c, c);
1265 break;
1266 }
1267 }
1268
1269 ins->rex &= rex_mask;
1270
1271 if (ins->rex & REX_NH) {
1272 if (ins->rex & REX_H) {
1273 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1274 return -1;
1275 }
1276 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1277 }
1278
1279 switch (ins->prefixes[PPS_VEX]) {
1280 case P_EVEX:
1281 if (!(ins->rex & REX_EV))
1282 return -1;
1283 break;
1284 case P_VEX3:
1285 case P_VEX2:
1286 if (!(ins->rex & REX_V))
1287 return -1;
1288 break;
1289 default:
1290 break;
1291 }
1292
1293 if (ins->rex & (REX_V | REX_EV)) {
1294 int bad32 = REX_R|REX_W|REX_X|REX_B;
1295
1296 if (ins->rex & REX_H) {
1297 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1298 return -1;
1299 }
1300 switch (ins->vex_wlp & 060) {
1301 case 000:
1302 case 040:
1303 ins->rex &= ~REX_W;
1304 break;
1305 case 020:
1306 ins->rex |= REX_W;
1307 bad32 &= ~REX_W;
1308 break;
1309 case 060:
1310 /* Follow REX_W */
1311 break;
1312 }
1313
1314 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1315 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1316 return -1;
1317 } else if (!(ins->rex & REX_EV) &&
1318 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1319 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1320 return -1;
1321 }
1322 if (ins->rex & REX_EV)
1323 length += 4;
1324 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1325 ins->prefixes[PPS_VEX] == P_VEX3)
1326 length += 3;
1327 else
1328 length += 2;
1329 } else if (ins->rex & REX_MASK) {
1330 if (ins->rex & REX_H) {
1331 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1332 return -1;
1333 } else if (bits == 64) {
1334 length++;
1335 } else if ((ins->rex & REX_L) &&
1336 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1337 iflag_ffs(&cpu) >= IF_X86_64) {
1338 /* LOCK-as-REX.R */
1339 assert_no_prefix(ins, PPS_LOCK);
1340 lockcheck = false; /* Already errored, no need for warning */
1341 length++;
1342 } else {
1343 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1344 return -1;
1345 }
1346 }
1347
1348 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1349 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1350 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1351 "instruction is not lockable");
1352 }
1353
1354 bad_hle_warn(ins, hleok);
1355
1356 /*
1357 * when BND prefix is set by DEFAULT directive,
1358 * BND prefix is added to every appropriate instruction line
1359 * unless it is overridden by NOBND prefix.
1360 */
1361 if (globalbnd &&
1362 (itemp_has(temp, IF_BND) && !has_prefix(ins, PPS_REP, P_NOBND)))
1363 ins->prefixes[PPS_REP] = P_BND;
1364
1365 return length;
1366 }
1367
1368 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1369 {
1370 if (bits == 64) {
1371 if ((ins->rex & REX_MASK) &&
1372 !(ins->rex & (REX_V | REX_EV)) &&
1373 !ins->rex_done) {
1374 int rex = (ins->rex & REX_MASK) | REX_P;
1375 out(offset, segment, &rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1376 ins->rex_done = true;
1377 return 1;
1378 }
1379 }
1380
1381 return 0;
1382 }
1383
1384 static void gencode(int32_t segment, int64_t offset, int bits,
1385 insn * ins, const struct itemplate *temp,
1386 int64_t insn_end)
1387 {
1388 uint8_t c;
1389 uint8_t bytes[4];
1390 int64_t size;
1391 int64_t data;
1392 int op1, op2;
1393 struct operand *opx;
1394 const uint8_t *codes = temp->code;
1395 uint8_t opex = 0;
1396 enum ea_type eat = EA_SCALAR;
1397
1398 ins->rex_done = false;
1399
1400 while (*codes) {
1401 c = *codes++;
1402 op1 = (c & 3) + ((opex & 1) << 2);
1403 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1404 opx = &ins->oprs[op1];
1405 opex = 0; /* For the next iteration */
1406
1407 switch (c) {
1408 case 01:
1409 case 02:
1410 case 03:
1411 case 04:
1412 offset += emit_rex(ins, segment, offset, bits);
1413 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1414 codes += c;
1415 offset += c;
1416 break;
1417
1418 case 05:
1419 case 06:
1420 case 07:
1421 opex = c;
1422 break;
1423
1424 case4(010):
1425 offset += emit_rex(ins, segment, offset, bits);
1426 bytes[0] = *codes++ + (regval(opx) & 7);
1427 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1428 offset += 1;
1429 break;
1430
1431 case4(014):
1432 break;
1433
1434 case4(020):
1435 if (opx->offset < -256 || opx->offset > 255) {
1436 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1437 "byte value exceeds bounds");
1438 }
1439 out_imm8(offset, segment, opx, -1);
1440 offset += 1;
1441 break;
1442
1443 case4(024):
1444 if (opx->offset < 0 || opx->offset > 255)
1445 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1446 "unsigned byte value exceeds bounds");
1447 out_imm8(offset, segment, opx, 1);
1448 offset += 1;
1449 break;
1450
1451 case4(030):
1452 warn_overflow_opd(opx, 2);
1453 data = opx->offset;
1454 out(offset, segment, &data, OUT_ADDRESS, 2,
1455 opx->segment, opx->wrt);
1456 offset += 2;
1457 break;
1458
1459 case4(034):
1460 if (opx->type & (BITS16 | BITS32))
1461 size = (opx->type & BITS16) ? 2 : 4;
1462 else
1463 size = (bits == 16) ? 2 : 4;
1464 warn_overflow_opd(opx, size);
1465 data = opx->offset;
1466 out(offset, segment, &data, OUT_ADDRESS, size,
1467 opx->segment, opx->wrt);
1468 offset += size;
1469 break;
1470
1471 case4(040):
1472 warn_overflow_opd(opx, 4);
1473 data = opx->offset;
1474 out(offset, segment, &data, OUT_ADDRESS, 4,
1475 opx->segment, opx->wrt);
1476 offset += 4;
1477 break;
1478
1479 case4(044):
1480 data = opx->offset;
1481 size = ins->addr_size >> 3;
1482 warn_overflow_opd(opx, size);
1483 out(offset, segment, &data, OUT_ADDRESS, size,
1484 opx->segment, opx->wrt);
1485 offset += size;
1486 break;
1487
1488 case4(050):
1489 if (opx->segment != segment) {
1490 data = opx->offset;
1491 out(offset, segment, &data,
1492 OUT_REL1ADR, insn_end - offset,
1493 opx->segment, opx->wrt);
1494 } else {
1495 data = opx->offset - insn_end;
1496 if (data > 127 || data < -128)
1497 errfunc(ERR_NONFATAL, "short jump is out of range");
1498 out(offset, segment, &data,
1499 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1500 }
1501 offset += 1;
1502 break;
1503
1504 case4(054):
1505 data = (int64_t)opx->offset;
1506 out(offset, segment, &data, OUT_ADDRESS, 8,
1507 opx->segment, opx->wrt);
1508 offset += 8;
1509 break;
1510
1511 case4(060):
1512 if (opx->segment != segment) {
1513 data = opx->offset;
1514 out(offset, segment, &data,
1515 OUT_REL2ADR, insn_end - offset,
1516 opx->segment, opx->wrt);
1517 } else {
1518 data = opx->offset - insn_end;
1519 out(offset, segment, &data,
1520 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1521 }
1522 offset += 2;
1523 break;
1524
1525 case4(064):
1526 if (opx->type & (BITS16 | BITS32 | BITS64))
1527 size = (opx->type & BITS16) ? 2 : 4;
1528 else
1529 size = (bits == 16) ? 2 : 4;
1530 if (opx->segment != segment) {
1531 data = opx->offset;
1532 out(offset, segment, &data,
1533 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1534 insn_end - offset, opx->segment, opx->wrt);
1535 } else {
1536 data = opx->offset - insn_end;
1537 out(offset, segment, &data,
1538 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1539 }
1540 offset += size;
1541 break;
1542
1543 case4(070):
1544 if (opx->segment != segment) {
1545 data = opx->offset;
1546 out(offset, segment, &data,
1547 OUT_REL4ADR, insn_end - offset,
1548 opx->segment, opx->wrt);
1549 } else {
1550 data = opx->offset - insn_end;
1551 out(offset, segment, &data,
1552 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1553 }
1554 offset += 4;
1555 break;
1556
1557 case4(074):
1558 if (opx->segment == NO_SEG)
1559 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1560 " relocatable");
1561 data = 0;
1562 out(offset, segment, &data, OUT_ADDRESS, 2,
1563 outfmt->segbase(1 + opx->segment),
1564 opx->wrt);
1565 offset += 2;
1566 break;
1567
1568 case 0172:
1569 c = *codes++;
1570 opx = &ins->oprs[c >> 3];
1571 bytes[0] = nasm_regvals[opx->basereg] << 4;
1572 opx = &ins->oprs[c & 7];
1573 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1574 errfunc(ERR_NONFATAL,
1575 "non-absolute expression not permitted as argument %d",
1576 c & 7);
1577 } else {
1578 if (opx->offset & ~15) {
1579 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1580 "four-bit argument exceeds bounds");
1581 }
1582 bytes[0] |= opx->offset & 15;
1583 }
1584 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1585 offset++;
1586 break;
1587
1588 case 0173:
1589 c = *codes++;
1590 opx = &ins->oprs[c >> 4];
1591 bytes[0] = nasm_regvals[opx->basereg] << 4;
1592 bytes[0] |= c & 15;
1593 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1594 offset++;
1595 break;
1596
1597 case4(0174):
1598 bytes[0] = nasm_regvals[opx->basereg] << 4;
1599 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1600 offset++;
1601 break;
1602
1603 case4(0254):
1604 data = opx->offset;
1605 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1606 (int32_t)data != (int64_t)data) {
1607 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1608 "signed dword immediate exceeds bounds");
1609 }
1610 out(offset, segment, &data, OUT_ADDRESS, -4,
1611 opx->segment, opx->wrt);
1612 offset += 4;
1613 break;
1614
1615 case4(0240):
1616 case 0250:
1617 codes += 3;
1618 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1619 EVEX_P2Z | EVEX_P2AAA, 2);
1620 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1621 bytes[0] = 0x62;
1622 /* EVEX.X can be set by either REX or EVEX for different reasons */
1623 bytes[1] = ((((ins->rex & 7) << 5) |
1624 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1625 (ins->vex_cm & 3);
1626 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1627 ((~ins->vexreg & 15) << 3) |
1628 (1 << 2) | (ins->vex_wlp & 3);
1629 bytes[3] = ins->evex_p[2];
1630 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1631 offset += 4;
1632 break;
1633
1634 case4(0260):
1635 case 0270:
1636 codes += 2;
1637 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1638 ins->prefixes[PPS_VEX] == P_VEX3) {
1639 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1640 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1641 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1642 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1643 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1644 offset += 3;
1645 } else {
1646 bytes[0] = 0xc5;
1647 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1648 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1649 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1650 offset += 2;
1651 }
1652 break;
1653
1654 case 0271:
1655 case 0272:
1656 case 0273:
1657 break;
1658
1659 case4(0274):
1660 {
1661 uint64_t uv, um;
1662 int s;
1663
1664 if (ins->rex & REX_W)
1665 s = 64;
1666 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1667 s = 16;
1668 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1669 s = 32;
1670 else
1671 s = bits;
1672
1673 um = (uint64_t)2 << (s-1);
1674 uv = opx->offset;
1675
1676 if (uv > 127 && uv < (uint64_t)-128 &&
1677 (uv < um-128 || uv > um-1)) {
1678 /* If this wasn't explicitly byte-sized, warn as though we
1679 * had fallen through to the imm16/32/64 case.
1680 */
1681 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1682 "%s value exceeds bounds",
1683 (opx->type & BITS8) ? "signed byte" :
1684 s == 16 ? "word" :
1685 s == 32 ? "dword" :
1686 "signed dword");
1687 }
1688 if (opx->segment != NO_SEG) {
1689 data = uv;
1690 out(offset, segment, &data, OUT_ADDRESS, 1,
1691 opx->segment, opx->wrt);
1692 } else {
1693 bytes[0] = uv;
1694 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1695 NO_SEG);
1696 }
1697 offset += 1;
1698 break;
1699 }
1700
1701 case4(0300):
1702 break;
1703
1704 case 0310:
1705 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1706 *bytes = 0x67;
1707 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1708 offset += 1;
1709 } else
1710 offset += 0;
1711 break;
1712
1713 case 0311:
1714 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1715 *bytes = 0x67;
1716 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1717 offset += 1;
1718 } else
1719 offset += 0;
1720 break;
1721
1722 case 0312:
1723 break;
1724
1725 case 0313:
1726 ins->rex = 0;
1727 break;
1728
1729 case4(0314):
1730 break;
1731
1732 case 0320:
1733 case 0321:
1734 break;
1735
1736 case 0322:
1737 case 0323:
1738 break;
1739
1740 case 0324:
1741 ins->rex |= REX_W;
1742 break;
1743
1744 case 0325:
1745 break;
1746
1747 case 0326:
1748 break;
1749
1750 case 0330:
1751 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1752 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1753 offset += 1;
1754 break;
1755
1756 case 0331:
1757 break;
1758
1759 case 0332:
1760 case 0333:
1761 *bytes = c - 0332 + 0xF2;
1762 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1763 offset += 1;
1764 break;
1765
1766 case 0334:
1767 if (ins->rex & REX_R) {
1768 *bytes = 0xF0;
1769 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1770 offset += 1;
1771 }
1772 ins->rex &= ~(REX_L|REX_R);
1773 break;
1774
1775 case 0335:
1776 break;
1777
1778 case 0336:
1779 case 0337:
1780 break;
1781
1782 case 0340:
1783 if (ins->oprs[0].segment != NO_SEG)
1784 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1785 else {
1786 int64_t size = ins->oprs[0].offset;
1787 if (size > 0)
1788 out(offset, segment, NULL,
1789 OUT_RESERVE, size, NO_SEG, NO_SEG);
1790 offset += size;
1791 }
1792 break;
1793
1794 case 0341:
1795 break;
1796
1797 case 0360:
1798 break;
1799
1800 case 0361:
1801 bytes[0] = 0x66;
1802 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1803 offset += 1;
1804 break;
1805
1806 case 0364:
1807 case 0365:
1808 break;
1809
1810 case 0366:
1811 case 0367:
1812 *bytes = c - 0366 + 0x66;
1813 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1814 offset += 1;
1815 break;
1816
1817 case3(0370):
1818 break;
1819
1820 case 0373:
1821 *bytes = bits == 16 ? 3 : 5;
1822 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1823 offset += 1;
1824 break;
1825
1826 case 0374:
1827 eat = EA_XMMVSIB;
1828 break;
1829
1830 case 0375:
1831 eat = EA_YMMVSIB;
1832 break;
1833
1834 case 0376:
1835 eat = EA_ZMMVSIB;
1836 break;
1837
1838 case4(0100):
1839 case4(0110):
1840 case4(0120):
1841 case4(0130):
1842 case4(0200):
1843 case4(0204):
1844 case4(0210):
1845 case4(0214):
1846 case4(0220):
1847 case4(0224):
1848 case4(0230):
1849 case4(0234):
1850 {
1851 ea ea_data;
1852 int rfield;
1853 opflags_t rflags;
1854 uint8_t *p;
1855 int32_t s;
1856 struct operand *opy = &ins->oprs[op2];
1857
1858 if (c <= 0177) {
1859 /* pick rfield from operand b (opx) */
1860 rflags = regflag(opx);
1861 rfield = nasm_regvals[opx->basereg];
1862 } else {
1863 /* rfield is constant */
1864 rflags = 0;
1865 rfield = c & 7;
1866 }
1867
1868 if (process_ea(opy, &ea_data, bits,
1869 rfield, rflags, ins) != eat)
1870 errfunc(ERR_NONFATAL, "invalid effective address");
1871
1872 p = bytes;
1873 *p++ = ea_data.modrm;
1874 if (ea_data.sib_present)
1875 *p++ = ea_data.sib;
1876
1877 s = p - bytes;
1878 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1879
1880 /*
1881 * Make sure the address gets the right offset in case
1882 * the line breaks in the .lst file (BR 1197827)
1883 */
1884 offset += s;
1885 s = 0;
1886
1887 if (ea_data.bytes) {
1888 /* use compressed displacement, if available */
1889 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1890 s += ea_data.bytes;
1891 if (ea_data.rip) {
1892 if (opy->segment == segment) {
1893 data -= insn_end;
1894 if (overflow_signed(data, ea_data.bytes))
1895 warn_overflow(ERR_PASS2, ea_data.bytes);
1896 out(offset, segment, &data, OUT_ADDRESS,
1897 ea_data.bytes, NO_SEG, NO_SEG);
1898 } else {
1899 /* overflow check in output/linker? */
1900 out(offset, segment, &data, OUT_REL4ADR,
1901 insn_end - offset, opy->segment, opy->wrt);
1902 }
1903 } else {
1904 int asize = ins->addr_size >> 3;
1905 int atype = ea_data.bytes;
1906
1907 if (overflow_general(data, asize) ||
1908 signed_bits(data, ins->addr_size) !=
1909 signed_bits(data, ea_data.bytes << 3))
1910 warn_overflow(ERR_PASS2, ea_data.bytes);
1911
1912 if (asize > ea_data.bytes) {
1913 /*
1914 * If the address isn't the full width of
1915 * the address size, treat is as signed...
1916 */
1917 atype = -atype;
1918 }
1919
1920 out(offset, segment, &data, OUT_ADDRESS,
1921 atype, opy->segment, opy->wrt);
1922 }
1923 }
1924 offset += s;
1925 }
1926 break;
1927
1928 default:
1929 errfunc(ERR_PANIC, "internal instruction table corrupt"
1930 ": instruction code \\%o (0x%02X) given", c, c);
1931 break;
1932 }
1933 }
1934 }
1935
1936 static opflags_t regflag(const operand * o)
1937 {
1938 if (!is_register(o->basereg))
1939 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1940 return nasm_reg_flags[o->basereg];
1941 }
1942
1943 static int32_t regval(const operand * o)
1944 {
1945 if (!is_register(o->basereg))
1946 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1947 return nasm_regvals[o->basereg];
1948 }
1949
1950 static int op_rexflags(const operand * o, int mask)
1951 {
1952 opflags_t flags;
1953 int val;
1954
1955 if (!is_register(o->basereg))
1956 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1957
1958 flags = nasm_reg_flags[o->basereg];
1959 val = nasm_regvals[o->basereg];
1960
1961 return rexflags(val, flags, mask);
1962 }
1963
1964 static int rexflags(int val, opflags_t flags, int mask)
1965 {
1966 int rex = 0;
1967
1968 if (val >= 0 && (val & 8))
1969 rex |= REX_B|REX_X|REX_R;
1970 if (flags & BITS64)
1971 rex |= REX_W;
1972 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1973 rex |= REX_H;
1974 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1975 rex |= REX_P;
1976
1977 return rex & mask;
1978 }
1979
1980 static int evexflags(int val, decoflags_t deco,
1981 int mask, uint8_t byte)
1982 {
1983 int evex = 0;
1984
1985 switch (byte) {
1986 case 0:
1987 if (val >= 0 && (val & 16))
1988 evex |= (EVEX_P0RP | EVEX_P0X);
1989 break;
1990 case 2:
1991 if (val >= 0 && (val & 16))
1992 evex |= EVEX_P2VP;
1993 if (deco & Z)
1994 evex |= EVEX_P2Z;
1995 if (deco & OPMASK_MASK)
1996 evex |= deco & EVEX_P2AAA;
1997 break;
1998 }
1999 return evex & mask;
2000 }
2001
2002 static int op_evexflags(const operand * o, int mask, uint8_t byte)
2003 {
2004 int val;
2005
2006 val = nasm_regvals[o->basereg];
2007
2008 return evexflags(val, o->decoflags, mask, byte);
2009 }
2010
2011 static enum match_result find_match(const struct itemplate **tempp,
2012 insn *instruction,
2013 int32_t segment, int64_t offset, int bits)
2014 {
2015 const struct itemplate *temp;
2016 enum match_result m, merr;
2017 opflags_t xsizeflags[MAX_OPERANDS];
2018 bool opsizemissing = false;
2019 int8_t broadcast = instruction->evex_brerop;
2020 int i;
2021
2022 /* broadcasting uses a different data element size */
2023 for (i = 0; i < instruction->operands; i++)
2024 if (i == broadcast)
2025 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
2026 else
2027 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
2028
2029 merr = MERR_INVALOP;
2030
2031 for (temp = nasm_instructions[instruction->opcode];
2032 temp->opcode != I_none; temp++) {
2033 m = matches(temp, instruction, bits);
2034 if (m == MOK_JUMP) {
2035 if (jmp_match(segment, offset, bits, instruction, temp))
2036 m = MOK_GOOD;
2037 else
2038 m = MERR_INVALOP;
2039 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2040 /*
2041 * Missing operand size and a candidate for fuzzy matching...
2042 */
2043 for (i = 0; i < temp->operands; i++)
2044 if (i == broadcast)
2045 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2046 else
2047 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2048 opsizemissing = true;
2049 }
2050 if (m > merr)
2051 merr = m;
2052 if (merr == MOK_GOOD)
2053 goto done;
2054 }
2055
2056 /* No match, but see if we can get a fuzzy operand size match... */
2057 if (!opsizemissing)
2058 goto done;
2059
2060 for (i = 0; i < instruction->operands; i++) {
2061 /*
2062 * We ignore extrinsic operand sizes on registers, so we should
2063 * never try to fuzzy-match on them. This also resolves the case
2064 * when we have e.g. "xmmrm128" in two different positions.
2065 */
2066 if (is_class(REGISTER, instruction->oprs[i].type))
2067 continue;
2068
2069 /* This tests if xsizeflags[i] has more than one bit set */
2070 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2071 goto done; /* No luck */
2072
2073 if (i == broadcast) {
2074 instruction->oprs[i].decoflags |= xsizeflags[i];
2075 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2076 BITS32 : BITS64);
2077 } else {
2078 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2079 }
2080 }
2081
2082 /* Try matching again... */
2083 for (temp = nasm_instructions[instruction->opcode];
2084 temp->opcode != I_none; temp++) {
2085 m = matches(temp, instruction, bits);
2086 if (m == MOK_JUMP) {
2087 if (jmp_match(segment, offset, bits, instruction, temp))
2088 m = MOK_GOOD;
2089 else
2090 m = MERR_INVALOP;
2091 }
2092 if (m > merr)
2093 merr = m;
2094 if (merr == MOK_GOOD)
2095 goto done;
2096 }
2097
2098 done:
2099 *tempp = temp;
2100 return merr;
2101 }
2102
2103 static enum match_result matches(const struct itemplate *itemp,
2104 insn *instruction, int bits)
2105 {
2106 opflags_t size[MAX_OPERANDS], asize;
2107 bool opsizemissing = false;
2108 int i, oprs;
2109
2110 /*
2111 * Check the opcode
2112 */
2113 if (itemp->opcode != instruction->opcode)
2114 return MERR_INVALOP;
2115
2116 /*
2117 * Count the operands
2118 */
2119 if (itemp->operands != instruction->operands)
2120 return MERR_INVALOP;
2121
2122 /*
2123 * Is it legal?
2124 */
2125 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2126 return MERR_INVALOP;
2127
2128 /*
2129 * {evex} available?
2130 */
2131 switch (instruction->prefixes[PPS_VEX]) {
2132 case P_EVEX:
2133 if (!itemp_has(itemp, IF_EVEX))
2134 return MERR_ENCMISMATCH;
2135 break;
2136 case P_VEX3:
2137 case P_VEX2:
2138 if (!itemp_has(itemp, IF_VEX))
2139 return MERR_ENCMISMATCH;
2140 break;
2141 default:
2142 break;
2143 }
2144
2145 /*
2146 * Check that no spurious colons or TOs are present
2147 */
2148 for (i = 0; i < itemp->operands; i++)
2149 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2150 return MERR_INVALOP;
2151
2152 /*
2153 * Process size flags
2154 */
2155 switch (itemp_smask(itemp)) {
2156 case IF_GENBIT(IF_SB):
2157 asize = BITS8;
2158 break;
2159 case IF_GENBIT(IF_SW):
2160 asize = BITS16;
2161 break;
2162 case IF_GENBIT(IF_SD):
2163 asize = BITS32;
2164 break;
2165 case IF_GENBIT(IF_SQ):
2166 asize = BITS64;
2167 break;
2168 case IF_GENBIT(IF_SO):
2169 asize = BITS128;
2170 break;
2171 case IF_GENBIT(IF_SY):
2172 asize = BITS256;
2173 break;
2174 case IF_GENBIT(IF_SZ):
2175 asize = BITS512;
2176 break;
2177 case IF_GENBIT(IF_SIZE):
2178 switch (bits) {
2179 case 16:
2180 asize = BITS16;
2181 break;
2182 case 32:
2183 asize = BITS32;
2184 break;
2185 case 64:
2186 asize = BITS64;
2187 break;
2188 default:
2189 asize = 0;
2190 break;
2191 }
2192 break;
2193 default:
2194 asize = 0;
2195 break;
2196 }
2197
2198 if (itemp_armask(itemp)) {
2199 /* S- flags only apply to a specific operand */
2200 i = itemp_arg(itemp);
2201 memset(size, 0, sizeof size);
2202 size[i] = asize;
2203 } else {
2204 /* S- flags apply to all operands */
2205 for (i = 0; i < MAX_OPERANDS; i++)
2206 size[i] = asize;
2207 }
2208
2209 /*
2210 * Check that the operand flags all match up,
2211 * it's a bit tricky so lets be verbose:
2212 *
2213 * 1) Find out the size of operand. If instruction
2214 * doesn't have one specified -- we're trying to
2215 * guess it either from template (IF_S* flag) or
2216 * from code bits.
2217 *
2218 * 2) If template operand do not match the instruction OR
2219 * template has an operand size specified AND this size differ
2220 * from which instruction has (perhaps we got it from code bits)
2221 * we are:
2222 * a) Check that only size of instruction and operand is differ
2223 * other characteristics do match
2224 * b) Perhaps it's a register specified in instruction so
2225 * for such a case we just mark that operand as "size
2226 * missing" and this will turn on fuzzy operand size
2227 * logic facility (handled by a caller)
2228 */
2229 for (i = 0; i < itemp->operands; i++) {
2230 opflags_t type = instruction->oprs[i].type;
2231 decoflags_t deco = instruction->oprs[i].decoflags;
2232 bool is_broadcast = deco & BRDCAST_MASK;
2233 uint8_t brcast_num = 0;
2234 opflags_t template_opsize, insn_opsize;
2235
2236 if (!(type & SIZE_MASK))
2237 type |= size[i];
2238
2239 insn_opsize = type & SIZE_MASK;
2240 if (!is_broadcast) {
2241 template_opsize = itemp->opd[i] & SIZE_MASK;
2242 } else {
2243 decoflags_t deco_brsize = itemp->deco[i] & BRSIZE_MASK;
2244 /*
2245 * when broadcasting, the element size depends on
2246 * the instruction type. decorator flag should match.
2247 */
2248
2249 if (deco_brsize) {
2250 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2251 /* calculate the proper number : {1to<brcast_num>} */
2252 brcast_num = (itemp->opd[i] & SIZE_MASK) / BITS128 *
2253 BITS64 / template_opsize * 2;
2254 } else {
2255 template_opsize = 0;
2256 }
2257 }
2258
2259 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2260 (deco & ~itemp->deco[i] & ~BRNUM_MASK)) {
2261 return MERR_INVALOP;
2262 } else if (template_opsize) {
2263 if (template_opsize != insn_opsize) {
2264 if (insn_opsize) {
2265 return MERR_INVALOP;
2266 } else if (!is_class(REGISTER, type)) {
2267 /*
2268 * Note: we don't honor extrinsic operand sizes for registers,
2269 * so "missing operand size" for a register should be
2270 * considered a wildcard match rather than an error.
2271 */
2272 opsizemissing = true;
2273 }
2274 } else if (is_broadcast &&
2275 (brcast_num !=
2276 (8U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2277 /*
2278 * broadcasting opsize matches but the number of repeated memory
2279 * element does not match.
2280 * if 64b double precision float is broadcasted to zmm (512b),
2281 * broadcasting decorator must be {1to8}.
2282 */
2283 return MERR_BRNUMMISMATCH;
2284 }
2285 }
2286 }
2287
2288 if (opsizemissing)
2289 return MERR_OPSIZEMISSING;
2290
2291 /*
2292 * Check operand sizes
2293 */
2294 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2295 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2296 for (i = 0; i < oprs; i++) {
2297 asize = itemp->opd[i] & SIZE_MASK;
2298 if (asize) {
2299 for (i = 0; i < oprs; i++)
2300 size[i] = asize;
2301 break;
2302 }
2303 }
2304 } else {
2305 oprs = itemp->operands;
2306 }
2307
2308 for (i = 0; i < itemp->operands; i++) {
2309 if (!(itemp->opd[i] & SIZE_MASK) &&
2310 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2311 return MERR_OPSIZEMISMATCH;
2312 }
2313
2314 /*
2315 * Check template is okay at the set cpu level
2316 */
2317 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2318 return MERR_BADCPU;
2319
2320 /*
2321 * Verify the appropriate long mode flag.
2322 */
2323 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2324 return MERR_BADMODE;
2325
2326 /*
2327 * If we have a HLE prefix, look for the NOHLE flag
2328 */
2329 if (itemp_has(itemp, IF_NOHLE) &&
2330 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2331 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2332 return MERR_BADHLE;
2333
2334 /*
2335 * Check if special handling needed for Jumps
2336 */
2337 if ((itemp->code[0] & ~1) == 0370)
2338 return MOK_JUMP;
2339
2340 /*
2341 * Check if BND prefix is allowed.
2342 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2343 */
2344 if (!itemp_has(itemp, IF_BND) &&
2345 (has_prefix(instruction, PPS_REP, P_BND) ||
2346 has_prefix(instruction, PPS_REP, P_NOBND)))
2347 return MERR_BADBND;
2348 else if (itemp_has(itemp, IF_BND) &&
2349 (has_prefix(instruction, PPS_REP, P_REPNE) ||
2350 has_prefix(instruction, PPS_REP, P_REPNZ)))
2351 return MERR_BADREPNE;
2352
2353 return MOK_GOOD;
2354 }
2355
2356 /*
2357 * Check if ModR/M.mod should/can be 01.
2358 * - EAF_BYTEOFFS is set
2359 * - offset can fit in a byte when EVEX is not used
2360 * - offset can be compressed when EVEX is used
2361 */
2362 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2363 (o >= -128 && o <= 127 && \
2364 seg == NO_SEG && !forw_ref && \
2365 !(input->eaflags & EAF_WORDOFFS) && \
2366 !(ins->rex & REX_EV)) || \
2367 (ins->rex & REX_EV && \
2368 is_disp8n(input, ins, &output->disp8)))
2369
2370 static enum ea_type process_ea(operand *input, ea *output, int bits,
2371 int rfield, opflags_t rflags, insn *ins)
2372 {
2373 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2374 int addrbits = ins->addr_size;
2375 int eaflags = input->eaflags;
2376
2377 output->type = EA_SCALAR;
2378 output->rip = false;
2379 output->disp8 = 0;
2380
2381 /* REX flags for the rfield operand */
2382 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2383 /* EVEX.R' flag for the REG operand */
2384 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2385
2386 if (is_class(REGISTER, input->type)) {
2387 /*
2388 * It's a direct register.
2389 */
2390 if (!is_register(input->basereg))
2391 goto err;
2392
2393 if (!is_reg_class(REG_EA, input->basereg))
2394 goto err;
2395
2396 /* broadcasting is not available with a direct register operand. */
2397 if (input->decoflags & BRDCAST_MASK) {
2398 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2399 goto err;
2400 }
2401
2402 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2403 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2404 output->sib_present = false; /* no SIB necessary */
2405 output->bytes = 0; /* no offset necessary either */
2406 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2407 } else {
2408 /*
2409 * It's a memory reference.
2410 */
2411
2412 /* Embedded rounding or SAE is not available with a mem ref operand. */
2413 if (input->decoflags & (ER | SAE)) {
2414 nasm_error(ERR_NONFATAL,
2415 "Embedded rounding is available only with reg-reg op.");
2416 return -1;
2417 }
2418
2419 if (input->basereg == -1 &&
2420 (input->indexreg == -1 || input->scale == 0)) {
2421 /*
2422 * It's a pure offset.
2423 */
2424 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2425 input->segment == NO_SEG) {
2426 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2427 input->type &= ~IP_REL;
2428 input->type |= MEMORY;
2429 }
2430
2431 if (bits == 64 &&
2432 !(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
2433 nasm_error(ERR_NONFATAL, "RIP-relative addressing is prohibited for mib.");
2434 return -1;
2435 }
2436
2437 if (eaflags & EAF_BYTEOFFS ||
2438 (eaflags & EAF_WORDOFFS &&
2439 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2440 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2441 }
2442
2443 if (bits == 64 && (~input->type & IP_REL)) {
2444 output->sib_present = true;
2445 output->sib = GEN_SIB(0, 4, 5);
2446 output->bytes = 4;
2447 output->modrm = GEN_MODRM(0, rfield, 4);
2448 output->rip = false;
2449 } else {
2450 output->sib_present = false;
2451 output->bytes = (addrbits != 16 ? 4 : 2);
2452 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2453 output->rip = bits == 64;
2454 }
2455 } else {
2456 /*
2457 * It's an indirection.
2458 */
2459 int i = input->indexreg, b = input->basereg, s = input->scale;
2460 int32_t seg = input->segment;
2461 int hb = input->hintbase, ht = input->hinttype;
2462 int t, it, bt; /* register numbers */
2463 opflags_t x, ix, bx; /* register flags */
2464
2465 if (s == 0)
2466 i = -1; /* make this easy, at least */
2467
2468 if (is_register(i)) {
2469 it = nasm_regvals[i];
2470 ix = nasm_reg_flags[i];
2471 } else {
2472 it = -1;
2473 ix = 0;
2474 }
2475
2476 if (is_register(b)) {
2477 bt = nasm_regvals[b];
2478 bx = nasm_reg_flags[b];
2479 } else {
2480 bt = -1;
2481 bx = 0;
2482 }
2483
2484 /* if either one are a vector register... */
2485 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2486 opflags_t sok = BITS32 | BITS64;
2487 int32_t o = input->offset;
2488 int mod, scale, index, base;
2489
2490 /*
2491 * For a vector SIB, one has to be a vector and the other,
2492 * if present, a GPR. The vector must be the index operand.
2493 */
2494 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2495 if (s == 0)
2496 s = 1;
2497 else if (s != 1)
2498 goto err;
2499
2500 t = bt, bt = it, it = t;
2501 x = bx, bx = ix, ix = x;
2502 }
2503
2504 if (bt != -1) {
2505 if (REG_GPR & ~bx)
2506 goto err;
2507 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2508 sok &= bx;
2509 else
2510 goto err;
2511 }
2512
2513 /*
2514 * While we're here, ensure the user didn't specify
2515 * WORD or QWORD
2516 */
2517 if (input->disp_size == 16 || input->disp_size == 64)
2518 goto err;
2519
2520 if (addrbits == 16 ||
2521 (addrbits == 32 && !(sok & BITS32)) ||
2522 (addrbits == 64 && !(sok & BITS64)))
2523 goto err;
2524
2525 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2526 : ((ix & YMMREG & ~REG_EA)
2527 ? EA_YMMVSIB : EA_XMMVSIB));
2528
2529 output->rex |= rexflags(it, ix, REX_X);
2530 output->rex |= rexflags(bt, bx, REX_B);
2531 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2532
2533 index = it & 7; /* it is known to be != -1 */
2534
2535 switch (s) {
2536 case 1:
2537 scale = 0;
2538 break;
2539 case 2:
2540 scale = 1;
2541 break;
2542 case 4:
2543 scale = 2;
2544 break;
2545 case 8:
2546 scale = 3;
2547 break;
2548 default: /* then what the smeg is it? */
2549 goto err; /* panic */
2550 }
2551
2552 if (bt == -1) {
2553 base = 5;
2554 mod = 0;
2555 } else {
2556 base = (bt & 7);
2557 if (base != REG_NUM_EBP && o == 0 &&
2558 seg == NO_SEG && !forw_ref &&
2559 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2560 mod = 0;
2561 else if (IS_MOD_01())
2562 mod = 1;
2563 else
2564 mod = 2;
2565 }
2566
2567 output->sib_present = true;
2568 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2569 output->modrm = GEN_MODRM(mod, rfield, 4);
2570 output->sib = GEN_SIB(scale, index, base);
2571 } else if ((ix|bx) & (BITS32|BITS64)) {
2572 /*
2573 * it must be a 32/64-bit memory reference. Firstly we have
2574 * to check that all registers involved are type E/Rxx.
2575 */
2576 opflags_t sok = BITS32 | BITS64;
2577 int32_t o = input->offset;
2578
2579 if (it != -1) {
2580 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2581 sok &= ix;
2582 else
2583 goto err;
2584 }
2585
2586 if (bt != -1) {
2587 if (REG_GPR & ~bx)
2588 goto err; /* Invalid register */
2589 if (~sok & bx & SIZE_MASK)
2590 goto err; /* Invalid size */
2591 sok &= bx;
2592 }
2593
2594 /*
2595 * While we're here, ensure the user didn't specify
2596 * WORD or QWORD
2597 */
2598 if (input->disp_size == 16 || input->disp_size == 64)
2599 goto err;
2600
2601 if (addrbits == 16 ||
2602 (addrbits == 32 && !(sok & BITS32)) ||
2603 (addrbits == 64 && !(sok & BITS64)))
2604 goto err;
2605
2606 /* now reorganize base/index */
2607 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2608 ((hb == b && ht == EAH_NOTBASE) ||
2609 (hb == i && ht == EAH_MAKEBASE))) {
2610 /* swap if hints say so */
2611 t = bt, bt = it, it = t;
2612 x = bx, bx = ix, ix = x;
2613 }
2614
2615 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2616 /* make single reg base, unless hint */
2617 bt = it, bx = ix, it = -1, ix = 0;
2618 }
2619 if (eaflags & EAF_MIB) {
2620 /* only for mib operands */
2621 if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
2622 /*
2623 * make a single reg index [reg*1].
2624 * gas uses this form for an explicit index register.
2625 */
2626 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2627 }
2628 if ((ht == EAH_SUMMED) && bt == -1) {
2629 /* separate once summed index into [base, index] */
2630 bt = it, bx = ix, s--;
2631 }
2632 } else {
2633 if (((s == 2 && it != REG_NUM_ESP &&
2634 (!(eaflags & EAF_TIMESTWO) || (ht == EAH_SUMMED))) ||
2635 s == 3 || s == 5 || s == 9) && bt == -1) {
2636 /* convert 3*EAX to EAX+2*EAX */
2637 bt = it, bx = ix, s--;
2638 }
2639 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2640 (eaflags & EAF_TIMESTWO) &&
2641 (hb == b && ht == EAH_NOTBASE)) {
2642 /*
2643 * convert [NOSPLIT EAX*1]
2644 * to sib format with 0x0 displacement - [EAX*1+0].
2645 */
2646 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2647 }
2648 }
2649 if (s == 1 && it == REG_NUM_ESP) {
2650 /* swap ESP into base if scale is 1 */
2651 t = it, it = bt, bt = t;
2652 x = ix, ix = bx, bx = x;
2653 }
2654 if (it == REG_NUM_ESP ||
2655 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2656 goto err; /* wrong, for various reasons */
2657
2658 output->rex |= rexflags(it, ix, REX_X);
2659 output->rex |= rexflags(bt, bx, REX_B);
2660
2661 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2662 /* no SIB needed */
2663 int mod, rm;
2664
2665 if (bt == -1) {
2666 rm = 5;
2667 mod = 0;
2668 } else {
2669 rm = (bt & 7);
2670 if (rm != REG_NUM_EBP && o == 0 &&
2671 seg == NO_SEG && !forw_ref &&
2672 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2673 mod = 0;
2674 else if (IS_MOD_01())
2675 mod = 1;
2676 else
2677 mod = 2;
2678 }
2679
2680 output->sib_present = false;
2681 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2682 output->modrm = GEN_MODRM(mod, rfield, rm);
2683 } else {
2684 /* we need a SIB */
2685 int mod, scale, index, base;
2686
2687 if (it == -1)
2688 index = 4, s = 1;
2689 else
2690 index = (it & 7);
2691
2692 switch (s) {
2693 case 1:
2694 scale = 0;
2695 break;
2696 case 2:
2697 scale = 1;
2698 break;
2699 case 4:
2700 scale = 2;
2701 break;
2702 case 8:
2703 scale = 3;
2704 break;
2705 default: /* then what the smeg is it? */
2706 goto err; /* panic */
2707 }
2708
2709 if (bt == -1) {
2710 base = 5;
2711 mod = 0;
2712 } else {
2713 base = (bt & 7);
2714 if (base != REG_NUM_EBP && o == 0 &&
2715 seg == NO_SEG && !forw_ref &&
2716 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2717 mod = 0;
2718 else if (IS_MOD_01())
2719 mod = 1;
2720 else
2721 mod = 2;
2722 }
2723
2724 output->sib_present = true;
2725 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2726 output->modrm = GEN_MODRM(mod, rfield, 4);
2727 output->sib = GEN_SIB(scale, index, base);
2728 }
2729 } else { /* it's 16-bit */
2730 int mod, rm;
2731 int16_t o = input->offset;
2732
2733 /* check for 64-bit long mode */
2734 if (addrbits == 64)
2735 goto err;
2736
2737 /* check all registers are BX, BP, SI or DI */
2738 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2739 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2740 goto err;
2741
2742 /* ensure the user didn't specify DWORD/QWORD */
2743 if (input->disp_size == 32 || input->disp_size == 64)
2744 goto err;
2745
2746 if (s != 1 && i != -1)
2747 goto err; /* no can do, in 16-bit EA */
2748 if (b == -1 && i != -1) {
2749 int tmp = b;
2750 b = i;
2751 i = tmp;
2752 } /* swap */
2753 if ((b == R_SI || b == R_DI) && i != -1) {
2754 int tmp = b;
2755 b = i;
2756 i = tmp;
2757 }
2758 /* have BX/BP as base, SI/DI index */
2759 if (b == i)
2760 goto err; /* shouldn't ever happen, in theory */
2761 if (i != -1 && b != -1 &&
2762 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2763 goto err; /* invalid combinations */
2764 if (b == -1) /* pure offset: handled above */
2765 goto err; /* so if it gets to here, panic! */
2766
2767 rm = -1;
2768 if (i != -1)
2769 switch (i * 256 + b) {
2770 case R_SI * 256 + R_BX:
2771 rm = 0;
2772 break;
2773 case R_DI * 256 + R_BX:
2774 rm = 1;
2775 break;
2776 case R_SI * 256 + R_BP:
2777 rm = 2;
2778 break;
2779 case R_DI * 256 + R_BP:
2780 rm = 3;
2781 break;
2782 } else
2783 switch (b) {
2784 case R_SI:
2785 rm = 4;
2786 break;
2787 case R_DI:
2788 rm = 5;
2789 break;
2790 case R_BP:
2791 rm = 6;
2792 break;
2793 case R_BX:
2794 rm = 7;
2795 break;
2796 }
2797 if (rm == -1) /* can't happen, in theory */
2798 goto err; /* so panic if it does */
2799
2800 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2801 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2802 mod = 0;
2803 else if (IS_MOD_01())
2804 mod = 1;
2805 else
2806 mod = 2;
2807
2808 output->sib_present = false; /* no SIB - it's 16-bit */
2809 output->bytes = mod; /* bytes of offset needed */
2810 output->modrm = GEN_MODRM(mod, rfield, rm);
2811 }
2812 }
2813 }
2814
2815 output->size = 1 + output->sib_present + output->bytes;
2816 return output->type;
2817
2818 err:
2819 return output->type = EA_INVALID;
2820 }
2821
2822 static void add_asp(insn *ins, int addrbits)
2823 {
2824 int j, valid;
2825 int defdisp;
2826
2827 valid = (addrbits == 64) ? 64|32 : 32|16;
2828
2829 switch (ins->prefixes[PPS_ASIZE]) {
2830 case P_A16:
2831 valid &= 16;
2832 break;
2833 case P_A32:
2834 valid &= 32;
2835 break;
2836 case P_A64:
2837 valid &= 64;
2838 break;
2839 case P_ASP:
2840 valid &= (addrbits == 32) ? 16 : 32;
2841 break;
2842 default:
2843 break;
2844 }
2845
2846 for (j = 0; j < ins->operands; j++) {
2847 if (is_class(MEMORY, ins->oprs[j].type)) {
2848 opflags_t i, b;
2849
2850 /* Verify as Register */
2851 if (!is_register(ins->oprs[j].indexreg))
2852 i = 0;
2853 else
2854 i = nasm_reg_flags[ins->oprs[j].indexreg];
2855
2856 /* Verify as Register */
2857 if (!is_register(ins->oprs[j].basereg))
2858 b = 0;
2859 else
2860 b = nasm_reg_flags[ins->oprs[j].basereg];
2861
2862 if (ins->oprs[j].scale == 0)
2863 i = 0;
2864
2865 if (!i && !b) {
2866 int ds = ins->oprs[j].disp_size;
2867 if ((addrbits != 64 && ds > 8) ||
2868 (addrbits == 64 && ds == 16))
2869 valid &= ds;
2870 } else {
2871 if (!(REG16 & ~b))
2872 valid &= 16;
2873 if (!(REG32 & ~b))
2874 valid &= 32;
2875 if (!(REG64 & ~b))
2876 valid &= 64;
2877
2878 if (!(REG16 & ~i))
2879 valid &= 16;
2880 if (!(REG32 & ~i))
2881 valid &= 32;
2882 if (!(REG64 & ~i))
2883 valid &= 64;
2884 }
2885 }
2886 }
2887
2888 if (valid & addrbits) {
2889 ins->addr_size = addrbits;
2890 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2891 /* Add an address size prefix */
2892 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2893 ins->addr_size = (addrbits == 32) ? 16 : 32;
2894 } else {
2895 /* Impossible... */
2896 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2897 ins->addr_size = addrbits; /* Error recovery */
2898 }
2899
2900 defdisp = ins->addr_size == 16 ? 16 : 32;
2901
2902 for (j = 0; j < ins->operands; j++) {
2903 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2904 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2905 /*
2906 * mem_offs sizes must match the address size; if not,
2907 * strip the MEM_OFFS bit and match only EA instructions
2908 */
2909 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2910 }
2911 }
2912 }