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BR 3392421: consider mode decorators in instruction matching
[nasm/externdefs2.git] / asm / assemble.c
blob851ea8228eb51bfb95c826f02a725352cf620a95
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2017 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * Bytecode specification
38 * ----------------------
39 *
40 *
41 * Codes Mnemonic Explanation
42 *
43 * \0 terminates the code. (Unless it's a literal of course.)
44 * \1..\4 that many literal bytes follow in the code stream
45 * \5 add 4 to the primary operand number (b, low octdigit)
46 * \6 add 4 to the secondary operand number (a, middle octdigit)
47 * \7 add 4 to both the primary and the secondary operand number
48 * \10..\13 a literal byte follows in the code stream, to be added
49 * to the register value of operand 0..3
50 * \14..\17 the position of index register operand in MIB (BND insns)
51 * \20..\23 ib a byte immediate operand, from operand 0..3
52 * \24..\27 ib,u a zero-extended byte immediate operand, from operand 0..3
53 * \30..\33 iw a word immediate operand, from operand 0..3
54 * \34..\37 iwd select between \3[0-3] and \4[0-3] depending on 16/32 bit
55 * assembly mode or the operand-size override on the operand
56 * \40..\43 id a long immediate operand, from operand 0..3
57 * \44..\47 iwdq select between \3[0-3], \4[0-3] and \5[4-7]
58 * depending on the address size of the instruction.
59 * \50..\53 rel8 a byte relative operand, from operand 0..3
60 * \54..\57 iq a qword immediate operand, from operand 0..3
61 * \60..\63 rel16 a word relative operand, from operand 0..3
62 * \64..\67 rel select between \6[0-3] and \7[0-3] depending on 16/32 bit
63 * assembly mode or the operand-size override on the operand
64 * \70..\73 rel32 a long relative operand, from operand 0..3
65 * \74..\77 seg a word constant, from the _segment_ part of operand 0..3
66 * \1ab a ModRM, calculated on EA in operand a, with the spare
67 * field the register value of operand b.
68 * \172\ab the register number from operand a in bits 7..4, with
69 * the 4-bit immediate from operand b in bits 3..0.
70 * \173\xab the register number from operand a in bits 7..4, with
71 * the value b in bits 3..0.
72 * \174..\177 the register number from operand 0..3 in bits 7..4, and
73 * an arbitrary value in bits 3..0 (assembled as zero.)
74 * \2ab a ModRM, calculated on EA in operand a, with the spare
75 * field equal to digit b.
76 *
77 * \240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
78 * V field taken from operand 0..3.
79 * \250 this instruction uses EVEX rather than REX or VEX/XOP, with the
80 * V field set to 1111b.
81 *
82 * EVEX prefixes are followed by the sequence:
83 * \cm\wlp\tup where cm is:
84 * cc 00m mmm
85 * c = 2 for EVEX and mmmm is the M field (EVEX.P0[3:0])
86 * and wlp is:
87 * 00 wwl lpp
88 * [l0] ll = 0 (.128, .lz)
89 * [l1] ll = 1 (.256)
90 * [l2] ll = 2 (.512)
91 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
92 *
93 * [w0] ww = 0 for W = 0
94 * [w1] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
97 *
98 * [p0] pp = 0 for no prefix
99 * [60] pp = 1 for legacy prefix 60
100 * [f3] pp = 2
101 * [f2] pp = 3
102 *
103 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
104 * (compressed displacement encoding)
105 *
106 * \254..\257 id,s a signed 32-bit operand to be extended to 64 bits.
107 * \260..\263 this instruction uses VEX/XOP rather than REX, with the
108 * V field taken from operand 0..3.
109 * \270 this instruction uses VEX/XOP rather than REX, with the
110 * V field set to 1111b.
111 *
112 * VEX/XOP prefixes are followed by the sequence:
113 * \tmm\wlp where mm is the M field; and wlp is:
114 * 00 wwl lpp
115 * [l0] ll = 0 for L = 0 (.128, .lz)
116 * [l1] ll = 1 for L = 1 (.256)
117 * [lig] ll = 2 for L don't care (always assembled as 0)
118 *
119 * [w0] ww = 0 for W = 0
120 * [w1 ] ww = 1 for W = 1
121 * [wig] ww = 2 for W don't care (always assembled as 0)
122 * [ww] ww = 3 for W used as REX.W
123 *
124 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
125 *
126 * \271 hlexr instruction takes XRELEASE (F3) with or without lock
127 * \272 hlenl instruction takes XACQUIRE/XRELEASE with or without lock
128 * \273 hle instruction takes XACQUIRE/XRELEASE with lock only
129 * \274..\277 ib,s a byte immediate operand, from operand 0..3, sign-extended
130 * to the operand size (if o16/o32/o64 present) or the bit size
131 * \310 a16 indicates fixed 16-bit address size, i.e. optional 0x67.
132 * \311 a32 indicates fixed 32-bit address size, i.e. optional 0x67.
133 * \312 adf (disassembler only) invalid with non-default address size.
134 * \313 a64 indicates fixed 64-bit address size, 0x67 invalid.
135 * \314 norexb (disassembler only) invalid with REX.B
136 * \315 norexx (disassembler only) invalid with REX.X
137 * \316 norexr (disassembler only) invalid with REX.R
138 * \317 norexw (disassembler only) invalid with REX.W
139 * \320 o16 indicates fixed 16-bit operand size, i.e. optional 0x66.
140 * \321 o32 indicates fixed 32-bit operand size, i.e. optional 0x66.
141 * \322 odf indicates that this instruction is only valid when the
142 * operand size is the default (instruction to disassembler,
143 * generates no code in the assembler)
144 * \323 o64nw indicates fixed 64-bit operand size, REX on extensions only.
145 * \324 o64 indicates 64-bit operand size requiring REX prefix.
146 * \325 nohi instruction which always uses spl/bpl/sil/dil
147 * \326 nof3 instruction not valid with 0xF3 REP prefix. Hint for
148 disassembler only; for SSE instructions.
149 * \330 a literal byte follows in the code stream, to be added
150 * to the condition code value of the instruction.
151 * \331 norep instruction not valid with REP prefix. Hint for
152 * disassembler only; for SSE instructions.
153 * \332 f2i REP prefix (0xF2 byte) used as opcode extension.
154 * \333 f3i REP prefix (0xF3 byte) used as opcode extension.
155 * \334 rex.l LOCK prefix used as REX.R (used in non-64-bit mode)
156 * \335 repe disassemble a rep (0xF3 byte) prefix as repe not rep.
157 * \336 mustrep force a REP(E) prefix (0xF3) even if not specified.
158 * \337 mustrepne force a REPNE prefix (0xF2) even if not specified.
159 * \336-\337 are still listed as prefixes in the disassembler.
160 * \340 resb reserve <operand 0> bytes of uninitialized storage.
161 * Operand 0 had better be a segmentless constant.
162 * \341 wait this instruction needs a WAIT "prefix"
163 * \360 np no SSE prefix (== \364\331)
164 * \361 66 SSE prefix (== \366\331)
165 * \364 !osp operand-size prefix (0x66) not permitted
166 * \365 !asp address-size prefix (0x67) not permitted
167 * \366 operand-size prefix (0x66) used as opcode extension
168 * \367 address-size prefix (0x67) used as opcode extension
169 * \370,\371 jcc8 match only if operand 0 meets byte jump criteria.
170 * jmp8 370 is used for Jcc, 371 is used for JMP.
171 * \373 jlen assemble 0x03 if bits==16, 0x05 if bits==32;
172 * used for conditional jump over longer jump
173 * \374 vsibx|vm32x|vm64x this instruction takes an XMM VSIB memory EA
174 * \375 vsiby|vm32y|vm64y this instruction takes an YMM VSIB memory EA
175 * \376 vsibz|vm32z|vm64z this instruction takes an ZMM VSIB memory EA
176 */
177
178 #include "compiler.h"
179
180 #include <stdio.h>
181 #include <string.h>
182 #include <stdlib.h>
183
184 #include "nasm.h"
185 #include "nasmlib.h"
186 #include "error.h"
187 #include "assemble.h"
188 #include "insns.h"
189 #include "tables.h"
190 #include "disp8.h"
191 #include "listing.h"
192
193 enum match_result {
194 /*
195 * Matching errors. These should be sorted so that more specific
196 * errors come later in the sequence.
197 */
198 MERR_INVALOP,
199 MERR_OPSIZEMISSING,
200 MERR_OPSIZEMISMATCH,
201 MERR_BRNOTHERE,
202 MERR_BRNUMMISMATCH,
203 MERR_MASKNOTHERE,
204 MERR_DECONOTHERE,
205 MERR_BADCPU,
206 MERR_BADMODE,
207 MERR_BADHLE,
208 MERR_ENCMISMATCH,
209 MERR_BADBND,
210 MERR_BADREPNE,
211 /*
212 * Matching success; the conditional ones first
213 */
214 MOK_JUMP, /* Matching OK but needs jmp_match() */
215 MOK_GOOD /* Matching unconditionally OK */
216 };
217
218 typedef struct {
219 enum ea_type type; /* what kind of EA is this? */
220 int sib_present; /* is a SIB byte necessary? */
221 int bytes; /* # of bytes of offset needed */
222 int size; /* lazy - this is sib+bytes+1 */
223 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
224 int8_t disp8; /* compressed displacement for EVEX */
225 } ea;
226
227 #define GEN_SIB(scale, index, base) \
228 (((scale) << 6) | ((index) << 3) | ((base)))
229
230 #define GEN_MODRM(mod, reg, rm) \
231 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
232
233 static int64_t calcsize(int32_t, int64_t, int, insn *,
234 const struct itemplate *);
235 static int emit_prefix(struct out_data *data, const int bits, insn *ins);
236 static void gencode(struct out_data *data, insn *ins);
237 static enum match_result find_match(const struct itemplate **tempp,
238 insn *instruction,
239 int32_t segment, int64_t offset, int bits);
240 static enum match_result matches(const struct itemplate *, insn *, int bits);
241 static opflags_t regflag(const operand *);
242 static int32_t regval(const operand *);
243 static int rexflags(int, opflags_t, int);
244 static int op_rexflags(const operand *, int);
245 static int op_evexflags(const operand *, int, uint8_t);
246 static void add_asp(insn *, int);
247
248 static enum ea_type process_ea(operand *, ea *, int, int,
249 opflags_t, insn *, const char **);
250
251 static inline bool absolute_op(const struct operand *o)
252 {
253 return o->segment == NO_SEG && o->wrt == NO_SEG &&
254 !(o->opflags & OPFLAG_RELATIVE);
255 }
256
257 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
258 {
259 return ins->prefixes[pos] == prefix;
260 }
261
262 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
263 {
264 if (ins->prefixes[pos])
265 nasm_error(ERR_NONFATAL, "invalid %s prefix",
266 prefix_name(ins->prefixes[pos]));
267 }
268
269 static const char *size_name(int size)
270 {
271 switch (size) {
272 case 1:
273 return "byte";
274 case 2:
275 return "word";
276 case 4:
277 return "dword";
278 case 8:
279 return "qword";
280 case 10:
281 return "tword";
282 case 16:
283 return "oword";
284 case 32:
285 return "yword";
286 case 64:
287 return "zword";
288 default:
289 return "???";
290 }
291 }
292
293 static void warn_overflow(int size)
294 {
295 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
296 "%s data exceeds bounds", size_name(size));
297 }
298
299 static void warn_overflow_const(int64_t data, int size)
300 {
301 if (overflow_general(data, size))
302 warn_overflow(size);
303 }
304
305 static void warn_overflow_opd(const struct operand *o, int size)
306 {
307 if (absolute_op(o)) {
308 if (overflow_general(o->offset, size))
309 warn_overflow(size);
310 }
311 }
312
313 static void warn_overflow_out(int64_t data, int size, enum out_sign sign)
314 {
315 bool err;
316
317 switch (sign) {
318 case OUT_WRAP:
319 err = overflow_general(data, size);
320 break;
321 case OUT_SIGNED:
322 err = overflow_signed(data, size);
323 break;
324 case OUT_UNSIGNED:
325 err = overflow_unsigned(data, size);
326 break;
327 default:
328 panic();
329 break;
330 }
331
332 if (err)
333 warn_overflow(size);
334 }
335
336 /*
337 * This routine wrappers the real output format's output routine,
338 * in order to pass a copy of the data off to the listing file
339 * generator at the same time, flatten unnecessary relocations,
340 * and verify backend compatibility.
341 */
342 static void out(struct out_data *data)
343 {
344 static int32_t lineno = 0; /* static!!! */
345 static const char *lnfname = NULL;
346 int asize;
347 const int amax = ofmt->maxbits >> 3; /* Maximum address size in bytes */
348 union {
349 uint8_t b[8];
350 uint64_t q;
351 } xdata;
352 uint64_t size = data->size;
353 int64_t addrval;
354 int32_t fixseg; /* Segment for which to produce fixed data */
355
356 if (!data->size)
357 return; /* Nothing to do */
358
359 /*
360 * Convert addresses to RAWDATA if possible
361 * XXX: not all backends want this for global symbols!!!!
362 */
363 switch (data->type) {
364 case OUT_ADDRESS:
365 addrval = data->toffset;
366 fixseg = NO_SEG; /* Absolute address is fixed data */
367 goto address;
368
369 case OUT_RELADDR:
370 addrval = data->toffset - data->relbase;
371 fixseg = data->segment; /* Our own segment is fixed data */
372 goto address;
373
374 address:
375 asize = data->size;
376 nasm_assert(asize <= 8);
377 if (data->tsegment == fixseg && data->twrt == NO_SEG) {
378 uint8_t *q = xdata.b;
379
380 warn_overflow_out(addrval, asize, data->sign);
381
382 WRITEADDR(q, addrval, asize);
383 data->data = xdata.b;
384 data->type = OUT_RAWDATA;
385 asize = 0; /* No longer an address */
386 }
387 break;
388
389 default:
390 asize = 0; /* Not an address */
391 break;
392 }
393
394 lfmt->output(data);
395
396 /*
397 * this call to src_get determines when we call the
398 * debug-format-specific "linenum" function
399 * it updates lineno and lnfname to the current values
400 * returning 0 if "same as last time", -2 if lnfname
401 * changed, and the amount by which lineno changed,
402 * if it did. thus, these variables must be static
403 */
404
405 if (src_get(&lineno, &lnfname))
406 dfmt->linenum(lnfname, lineno, data->segment);
407
408 if (asize && asize > amax) {
409 if (data->type != OUT_ADDRESS || data->sign == OUT_SIGNED) {
410 nasm_error(ERR_NONFATAL,
411 "%d-bit signed relocation unsupported by output format %s\n",
412 asize << 3, ofmt->shortname);
413 } else {
414 nasm_error(ERR_WARNING | ERR_WARN_ZEXTRELOC,
415 "%d-bit unsigned relocation zero-extended from %d bits\n",
416 asize << 3, ofmt->maxbits);
417 data->size = amax;
418 ofmt->output(data);
419 data->insoffs += amax;
420 data->offset += amax;
421 data->size = size = asize - amax;
422 }
423 data->data = zero_buffer;
424 data->type = OUT_RAWDATA;
425 }
426
427 ofmt->output(data);
428 data->offset += size;
429 data->insoffs += size;
430 }
431
432 static inline void out_rawdata(struct out_data *data, const void *rawdata,
433 size_t size)
434 {
435 data->type = OUT_RAWDATA;
436 data->data = rawdata;
437 data->size = size;
438 out(data);
439 }
440
441 static void out_rawbyte(struct out_data *data, uint8_t byte)
442 {
443 data->type = OUT_RAWDATA;
444 data->data = &byte;
445 data->size = 1;
446 out(data);
447 }
448
449 static inline void out_reserve(struct out_data *data, uint64_t size)
450 {
451 data->type = OUT_RESERVE;
452 data->size = size;
453 out(data);
454 }
455
456 static inline void out_imm(struct out_data *data, const struct operand *opx,
457 int size, enum out_sign sign)
458 {
459 data->type =
460 (opx->opflags & OPFLAG_RELATIVE) ? OUT_RELADDR : OUT_ADDRESS;
461 data->sign = sign;
462 data->size = size;
463 data->toffset = opx->offset;
464 data->tsegment = opx->segment;
465 data->twrt = opx->wrt;
466 /*
467 * XXX: improve this if at some point in the future we can
468 * distinguish the subtrahend in expressions like [foo - bar]
469 * where bar is a symbol in the current segment. However, at the
470 * current point, if OPFLAG_RELATIVE is set that subtraction has
471 * already occurred.
472 */
473 data->relbase = 0;
474 out(data);
475 }
476
477 static void out_reladdr(struct out_data *data, const struct operand *opx,
478 int size)
479 {
480 if (opx->opflags & OPFLAG_RELATIVE)
481 nasm_error(ERR_NONFATAL, "invalid use of self-relative expression");
482
483 data->type = OUT_RELADDR;
484 data->sign = OUT_SIGNED;
485 data->size = size;
486 data->toffset = opx->offset;
487 data->tsegment = opx->segment;
488 data->twrt = opx->wrt;
489 data->relbase = data->offset + (data->inslen - data->insoffs);
490 out(data);
491 }
492
493 static inline void out_segment(struct out_data *data,
494 const struct operand *opx)
495 {
496 data->type = OUT_SEGMENT;
497 data->sign = OUT_UNSIGNED;
498 data->size = 2;
499 data->toffset = opx->offset; /* Is this really needed/wanted? */
500 data->tsegment = ofmt->segbase(opx->segment + 1);
501 data->twrt = opx->wrt;
502 out(data);
503 }
504
505 static bool jmp_match(int32_t segment, int64_t offset, int bits,
506 insn * ins, const struct itemplate *temp)
507 {
508 int64_t isize;
509 const uint8_t *code = temp->code;
510 uint8_t c = code[0];
511 bool is_byte;
512
513 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
514 return false;
515 if (!optimizing)
516 return false;
517 if (optimizing < 0 && c == 0371)
518 return false;
519
520 isize = calcsize(segment, offset, bits, ins, temp);
521
522 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
523 /* Be optimistic in pass 1 */
524 return true;
525
526 if (ins->oprs[0].segment != segment)
527 return false;
528
529 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
530 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
531
532 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
533 /* jmp short (opcode eb) cannot be used with bnd prefix. */
534 ins->prefixes[PPS_REP] = P_none;
535 nasm_error(ERR_WARNING | ERR_WARN_BND | ERR_PASS2 ,
536 "jmp short does not init bnd regs - bnd prefix dropped.");
537 }
538
539 return is_byte;
540 }
541
542 /* This is totally just a wild guess what is reasonable... */
543 #define INCBIN_MAX_BUF (ZERO_BUF_SIZE * 16)
544
545 int64_t assemble(int32_t segment, int64_t start, int bits, insn *instruction)
546 {
547 struct out_data data;
548 const struct itemplate *temp;
549 enum match_result m;
550 int64_t wsize; /* size for DB etc. */
551
552 nasm_zero(data);
553 data.offset = start;
554 data.segment = segment;
555 data.itemp = NULL;
556 data.sign = OUT_WRAP;
557 data.bits = bits;
558
559 wsize = idata_bytes(instruction->opcode);
560 if (wsize == -1)
561 return 0;
562
563 if (wsize) {
564 extop *e;
565
566 list_for_each(e, instruction->eops) {
567 if (e->type == EOT_DB_NUMBER) {
568 if (wsize > 8) {
569 nasm_error(ERR_NONFATAL,
570 "integer supplied to a DT, DO, DY or DZ"
571 " instruction");
572 } else {
573 data.insoffs = 0;
574 data.type = e->relative ? OUT_RELADDR : OUT_ADDRESS;
575 data.inslen = data.size = wsize;
576 data.toffset = e->offset;
577 data.tsegment = e->segment;
578 data.twrt = e->wrt;
579 data.relbase = 0;
580 out(&data);
581 }
582 } else if (e->type == EOT_DB_STRING ||
583 e->type == EOT_DB_STRING_FREE) {
584 int align = e->stringlen % wsize;
585 if (align)
586 align = wsize - align;
587
588 data.insoffs = 0;
589 data.inslen = e->stringlen + align;
590
591 out_rawdata(&data, e->stringval, e->stringlen);
592 out_rawdata(&data, zero_buffer, align);
593 }
594 }
595 } else if (instruction->opcode == I_INCBIN) {
596 const char *fname = instruction->eops->stringval;
597 FILE *fp;
598 size_t t = instruction->times; /* INCBIN handles TIMES by itself */
599 off_t base = 0;
600 off_t len;
601 const void *map = NULL;
602 char *buf = NULL;
603 size_t blk = 0; /* Buffered I/O block size */
604 size_t m = 0; /* Bytes last read */
605
606 fp = nasm_open_read(fname, NF_BINARY|NF_FORMAP);
607 if (!fp) {
608 nasm_error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
609 fname);
610 goto done;
611 }
612
613 len = nasm_file_size(fp);
614
615 if (len == (off_t)-1) {
616 nasm_error(ERR_NONFATAL, "`incbin': unable to get length of file `%s'",
617 fname);
618 goto close_done;
619 }
620
621 if (instruction->eops->next) {
622 base = instruction->eops->next->offset;
623 if (base >= len) {
624 len = 0;
625 } else {
626 len -= base;
627 if (instruction->eops->next->next &&
628 len > (off_t)instruction->eops->next->next->offset)
629 len = (off_t)instruction->eops->next->next->offset;
630 }
631 }
632
633 lfmt->set_offset(data.offset);
634 lfmt->uplevel(LIST_INCBIN);
635
636 if (!len)
637 goto end_incbin;
638
639 /* Try to map file data */
640 map = nasm_map_file(fp, base, len);
641 if (!map) {
642 blk = len < (off_t)INCBIN_MAX_BUF ? (size_t)len : INCBIN_MAX_BUF;
643 buf = nasm_malloc(blk);
644 }
645
646 while (t--) {
647 /*
648 * Consider these irrelevant for INCBIN, since it is fully
649 * possible that these might be (way) bigger than an int
650 * can hold; there is, however, no reason to widen these
651 * types just for INCBIN. data.inslen == 0 signals to the
652 * backend that these fields are meaningless, if at all
653 * needed.
654 */
655 data.insoffs = 0;
656 data.inslen = 0;
657
658 if (map) {
659 out_rawdata(&data, map, len);
660 } else if ((off_t)m == len) {
661 out_rawdata(&data, buf, len);
662 } else {
663 off_t l = len;
664
665 if (fseeko(fp, base, SEEK_SET) < 0 || ferror(fp)) {
666 nasm_error(ERR_NONFATAL,
667 "`incbin': unable to seek on file `%s'",
668 fname);
669 goto end_incbin;
670 }
671 while (l > 0) {
672 m = fread(buf, 1, l < (off_t)blk ? (size_t)l : blk, fp);
673 if (!m || feof(fp)) {
674 /*
675 * This shouldn't happen unless the file
676 * actually changes while we are reading
677 * it.
678 */
679 nasm_error(ERR_NONFATAL,
680 "`incbin': unexpected EOF while"
681 " reading file `%s'", fname);
682 goto end_incbin;
683 }
684 out_rawdata(&data, buf, m);
685 l -= m;
686 }
687 }
688 }
689 end_incbin:
690 lfmt->downlevel(LIST_INCBIN);
691 if (instruction->times > 1) {
692 lfmt->set_offset(start);
693 lfmt->uplevel(LIST_TIMES);
694 lfmt->downlevel(LIST_TIMES);
695 }
696 if (ferror(fp)) {
697 nasm_error(ERR_NONFATAL,
698 "`incbin': error while"
699 " reading file `%s'", fname);
700 }
701 close_done:
702 if (buf)
703 nasm_free(buf);
704 if (map)
705 nasm_unmap_file(map, len);
706 fclose(fp);
707 done:
708 instruction->times = 1; /* Tell the upper layer not to iterate */
709 ;
710 } else {
711 /* "Real" instruction */
712
713 /* Check to see if we need an address-size prefix */
714 add_asp(instruction, bits);
715
716 m = find_match(&temp, instruction, data.segment, data.offset, bits);
717
718 if (m == MOK_GOOD) {
719 /* Matches! */
720 int64_t insn_size = calcsize(data.segment, data.offset,
721 bits, instruction, temp);
722 nasm_assert(insn_size >= 0);
723
724 data.itemp = temp;
725 data.bits = bits;
726 data.insoffs = 0;
727 data.inslen = insn_size;
728
729 gencode(&data, instruction);
730 nasm_assert(data.insoffs == insn_size);
731 } else {
732 /* No match */
733 switch (m) {
734 case MERR_OPSIZEMISSING:
735 nasm_error(ERR_NONFATAL, "operation size not specified");
736 break;
737 case MERR_OPSIZEMISMATCH:
738 nasm_error(ERR_NONFATAL, "mismatch in operand sizes");
739 break;
740 case MERR_BRNOTHERE:
741 nasm_error(ERR_NONFATAL,
742 "broadcast not permitted on this operand");
743 break;
744 case MERR_BRNUMMISMATCH:
745 nasm_error(ERR_NONFATAL,
746 "mismatch in the number of broadcasting elements");
747 break;
748 case MERR_MASKNOTHERE:
749 nasm_error(ERR_NONFATAL,
750 "mask not permitted on this operand");
751 break;
752 case MERR_DECONOTHERE:
753 nasm_error(ERR_NONFATAL, "unsupported mode decorator for instruction");
754 break;
755 case MERR_BADCPU:
756 nasm_error(ERR_NONFATAL, "no instruction for this cpu level");
757 break;
758 case MERR_BADMODE:
759 nasm_error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
760 bits);
761 break;
762 case MERR_ENCMISMATCH:
763 nasm_error(ERR_NONFATAL, "specific encoding scheme not available");
764 break;
765 case MERR_BADBND:
766 nasm_error(ERR_NONFATAL, "bnd prefix is not allowed");
767 break;
768 case MERR_BADREPNE:
769 nasm_error(ERR_NONFATAL, "%s prefix is not allowed",
770 (has_prefix(instruction, PPS_REP, P_REPNE) ?
771 "repne" : "repnz"));
772 break;
773 default:
774 nasm_error(ERR_NONFATAL,
775 "invalid combination of opcode and operands");
776 break;
777 }
778
779 instruction->times = 1; /* Avoid repeated error messages */
780 }
781 }
782 return data.offset - start;
783 }
784
785 int64_t insn_size(int32_t segment, int64_t offset, int bits, insn *instruction)
786 {
787 const struct itemplate *temp;
788 enum match_result m;
789
790 if (instruction->opcode == I_none)
791 return 0;
792
793 if (opcode_is_db(instruction->opcode)) {
794 extop *e;
795 int32_t isize, osize, wsize;
796
797 isize = 0;
798 wsize = idata_bytes(instruction->opcode);
799 nasm_assert(wsize > 0);
800
801 list_for_each(e, instruction->eops) {
802 int32_t align;
803
804 osize = 0;
805 if (e->type == EOT_DB_NUMBER) {
806 osize = 1;
807 warn_overflow_const(e->offset, wsize);
808 } else if (e->type == EOT_DB_STRING ||
809 e->type == EOT_DB_STRING_FREE)
810 osize = e->stringlen;
811
812 align = (-osize) % wsize;
813 if (align < 0)
814 align += wsize;
815 isize += osize + align;
816 }
817 return isize;
818 }
819
820 if (instruction->opcode == I_INCBIN) {
821 const char *fname = instruction->eops->stringval;
822 off_t len;
823
824 len = nasm_file_size_by_path(fname);
825 if (len == (off_t)-1) {
826 nasm_error(ERR_NONFATAL, "`incbin': unable to get length of file `%s'",
827 fname);
828 return 0;
829 }
830
831 if (instruction->eops->next) {
832 if (len <= (off_t)instruction->eops->next->offset) {
833 len = 0;
834 } else {
835 len -= instruction->eops->next->offset;
836 if (instruction->eops->next->next &&
837 len > (off_t)instruction->eops->next->next->offset) {
838 len = (off_t)instruction->eops->next->next->offset;
839 }
840 }
841 }
842
843 len *= instruction->times;
844 instruction->times = 1; /* Tell the upper layer to not iterate */
845
846 return len;
847 }
848
849 /* Check to see if we need an address-size prefix */
850 add_asp(instruction, bits);
851
852 m = find_match(&temp, instruction, segment, offset, bits);
853 if (m == MOK_GOOD) {
854 /* we've matched an instruction. */
855 return calcsize(segment, offset, bits, instruction, temp);
856 } else {
857 return -1; /* didn't match any instruction */
858 }
859 }
860
861 static void bad_hle_warn(const insn * ins, uint8_t hleok)
862 {
863 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
864 enum whatwarn { w_none, w_lock, w_inval } ww;
865 static const enum whatwarn warn[2][4] =
866 {
867 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
868 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
869 };
870 unsigned int n;
871
872 n = (unsigned int)rep_pfx - P_XACQUIRE;
873 if (n > 1)
874 return; /* Not XACQUIRE/XRELEASE */
875
876 ww = warn[n][hleok];
877 if (!is_class(MEMORY, ins->oprs[0].type))
878 ww = w_inval; /* HLE requires operand 0 to be memory */
879
880 switch (ww) {
881 case w_none:
882 break;
883
884 case w_lock:
885 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
886 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
887 "%s with this instruction requires lock",
888 prefix_name(rep_pfx));
889 }
890 break;
891
892 case w_inval:
893 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
894 "%s invalid with this instruction",
895 prefix_name(rep_pfx));
896 break;
897 }
898 }
899
900 /* Common construct */
901 #define case3(x) case (x): case (x)+1: case (x)+2
902 #define case4(x) case3(x): case (x)+3
903
904 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
905 insn * ins, const struct itemplate *temp)
906 {
907 const uint8_t *codes = temp->code;
908 int64_t length = 0;
909 uint8_t c;
910 int rex_mask = ~0;
911 int op1, op2;
912 struct operand *opx;
913 uint8_t opex = 0;
914 enum ea_type eat;
915 uint8_t hleok = 0;
916 bool lockcheck = true;
917 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
918 const char *errmsg;
919
920 ins->rex = 0; /* Ensure REX is reset */
921 eat = EA_SCALAR; /* Expect a scalar EA */
922 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
923
924 if (ins->prefixes[PPS_OSIZE] == P_O64)
925 ins->rex |= REX_W;
926
927 (void)segment; /* Don't warn that this parameter is unused */
928 (void)offset; /* Don't warn that this parameter is unused */
929
930 while (*codes) {
931 c = *codes++;
932 op1 = (c & 3) + ((opex & 1) << 2);
933 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
934 opx = &ins->oprs[op1];
935 opex = 0; /* For the next iteration */
936
937 switch (c) {
938 case4(01):
939 codes += c, length += c;
940 break;
941
942 case3(05):
943 opex = c;
944 break;
945
946 case4(010):
947 ins->rex |=
948 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
949 codes++, length++;
950 break;
951
952 case4(014):
953 /* this is an index reg of MIB operand */
954 mib_index = opx->basereg;
955 break;
956
957 case4(020):
958 case4(024):
959 length++;
960 break;
961
962 case4(030):
963 length += 2;
964 break;
965
966 case4(034):
967 if (opx->type & (BITS16 | BITS32 | BITS64))
968 length += (opx->type & BITS16) ? 2 : 4;
969 else
970 length += (bits == 16) ? 2 : 4;
971 break;
972
973 case4(040):
974 length += 4;
975 break;
976
977 case4(044):
978 length += ins->addr_size >> 3;
979 break;
980
981 case4(050):
982 length++;
983 break;
984
985 case4(054):
986 length += 8; /* MOV reg64/imm */
987 break;
988
989 case4(060):
990 length += 2;
991 break;
992
993 case4(064):
994 if (opx->type & (BITS16 | BITS32 | BITS64))
995 length += (opx->type & BITS16) ? 2 : 4;
996 else
997 length += (bits == 16) ? 2 : 4;
998 break;
999
1000 case4(070):
1001 length += 4;
1002 break;
1003
1004 case4(074):
1005 length += 2;
1006 break;
1007
1008 case 0172:
1009 case 0173:
1010 codes++;
1011 length++;
1012 break;
1013
1014 case4(0174):
1015 length++;
1016 break;
1017
1018 case4(0240):
1019 ins->rex |= REX_EV;
1020 ins->vexreg = regval(opx);
1021 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
1022 ins->vex_cm = *codes++;
1023 ins->vex_wlp = *codes++;
1024 ins->evex_tuple = (*codes++ - 0300);
1025 break;
1026
1027 case 0250:
1028 ins->rex |= REX_EV;
1029 ins->vexreg = 0;
1030 ins->vex_cm = *codes++;
1031 ins->vex_wlp = *codes++;
1032 ins->evex_tuple = (*codes++ - 0300);
1033 break;
1034
1035 case4(0254):
1036 length += 4;
1037 break;
1038
1039 case4(0260):
1040 ins->rex |= REX_V;
1041 ins->vexreg = regval(opx);
1042 ins->vex_cm = *codes++;
1043 ins->vex_wlp = *codes++;
1044 break;
1045
1046 case 0270:
1047 ins->rex |= REX_V;
1048 ins->vexreg = 0;
1049 ins->vex_cm = *codes++;
1050 ins->vex_wlp = *codes++;
1051 break;
1052
1053 case3(0271):
1054 hleok = c & 3;
1055 break;
1056
1057 case4(0274):
1058 length++;
1059 break;
1060
1061 case4(0300):
1062 break;
1063
1064 case 0310:
1065 if (bits == 64)
1066 return -1;
1067 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1068 break;
1069
1070 case 0311:
1071 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1072 break;
1073
1074 case 0312:
1075 break;
1076
1077 case 0313:
1078 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1079 has_prefix(ins, PPS_ASIZE, P_A32))
1080 return -1;
1081 break;
1082
1083 case4(0314):
1084 break;
1085
1086 case 0320:
1087 {
1088 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1089 if (pfx == P_O16)
1090 break;
1091 if (pfx != P_none)
1092 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1093 else
1094 ins->prefixes[PPS_OSIZE] = P_O16;
1095 break;
1096 }
1097
1098 case 0321:
1099 {
1100 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1101 if (pfx == P_O32)
1102 break;
1103 if (pfx != P_none)
1104 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1105 else
1106 ins->prefixes[PPS_OSIZE] = P_O32;
1107 break;
1108 }
1109
1110 case 0322:
1111 break;
1112
1113 case 0323:
1114 rex_mask &= ~REX_W;
1115 break;
1116
1117 case 0324:
1118 ins->rex |= REX_W;
1119 break;
1120
1121 case 0325:
1122 ins->rex |= REX_NH;
1123 break;
1124
1125 case 0326:
1126 break;
1127
1128 case 0330:
1129 codes++, length++;
1130 break;
1131
1132 case 0331:
1133 break;
1134
1135 case 0332:
1136 case 0333:
1137 length++;
1138 break;
1139
1140 case 0334:
1141 ins->rex |= REX_L;
1142 break;
1143
1144 case 0335:
1145 break;
1146
1147 case 0336:
1148 if (!ins->prefixes[PPS_REP])
1149 ins->prefixes[PPS_REP] = P_REP;
1150 break;
1151
1152 case 0337:
1153 if (!ins->prefixes[PPS_REP])
1154 ins->prefixes[PPS_REP] = P_REPNE;
1155 break;
1156
1157 case 0340:
1158 if (!absolute_op(&ins->oprs[0]))
1159 nasm_error(ERR_NONFATAL, "attempt to reserve non-constant"
1160 " quantity of BSS space");
1161 else if (ins->oprs[0].opflags & OPFLAG_FORWARD)
1162 nasm_error(ERR_WARNING | ERR_PASS1,
1163 "forward reference in RESx can have unpredictable results");
1164 else
1165 length += ins->oprs[0].offset;
1166 break;
1167
1168 case 0341:
1169 if (!ins->prefixes[PPS_WAIT])
1170 ins->prefixes[PPS_WAIT] = P_WAIT;
1171 break;
1172
1173 case 0360:
1174 break;
1175
1176 case 0361:
1177 length++;
1178 break;
1179
1180 case 0364:
1181 case 0365:
1182 break;
1183
1184 case 0366:
1185 case 0367:
1186 length++;
1187 break;
1188
1189 case 0370:
1190 case 0371:
1191 break;
1192
1193 case 0373:
1194 length++;
1195 break;
1196
1197 case 0374:
1198 eat = EA_XMMVSIB;
1199 break;
1200
1201 case 0375:
1202 eat = EA_YMMVSIB;
1203 break;
1204
1205 case 0376:
1206 eat = EA_ZMMVSIB;
1207 break;
1208
1209 case4(0100):
1210 case4(0110):
1211 case4(0120):
1212 case4(0130):
1213 case4(0200):
1214 case4(0204):
1215 case4(0210):
1216 case4(0214):
1217 case4(0220):
1218 case4(0224):
1219 case4(0230):
1220 case4(0234):
1221 {
1222 ea ea_data;
1223 int rfield;
1224 opflags_t rflags;
1225 struct operand *opy = &ins->oprs[op2];
1226 struct operand *op_er_sae;
1227
1228 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1229
1230 if (c <= 0177) {
1231 /* pick rfield from operand b (opx) */
1232 rflags = regflag(opx);
1233 rfield = nasm_regvals[opx->basereg];
1234 } else {
1235 rflags = 0;
1236 rfield = c & 7;
1237 }
1238
1239 /* EVEX.b1 : evex_brerop contains the operand position */
1240 op_er_sae = (ins->evex_brerop >= 0 ?
1241 &ins->oprs[ins->evex_brerop] : NULL);
1242
1243 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1244 /* set EVEX.b */
1245 ins->evex_p[2] |= EVEX_P2B;
1246 if (op_er_sae->decoflags & ER) {
1247 /* set EVEX.RC (rounding control) */
1248 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1249 & EVEX_P2RC;
1250 }
1251 } else {
1252 /* set EVEX.L'L (vector length) */
1253 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1254 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1255 if (opy->decoflags & BRDCAST_MASK) {
1256 /* set EVEX.b */
1257 ins->evex_p[2] |= EVEX_P2B;
1258 }
1259 }
1260
1261 if (itemp_has(temp, IF_MIB)) {
1262 opy->eaflags |= EAF_MIB;
1263 /*
1264 * if a separate form of MIB (ICC style) is used,
1265 * the index reg info is merged into mem operand
1266 */
1267 if (mib_index != R_none) {
1268 opy->indexreg = mib_index;
1269 opy->scale = 1;
1270 opy->hintbase = mib_index;
1271 opy->hinttype = EAH_NOTBASE;
1272 }
1273 }
1274
1275 if (process_ea(opy, &ea_data, bits,
1276 rfield, rflags, ins, &errmsg) != eat) {
1277 nasm_error(ERR_NONFATAL, "%s", errmsg);
1278 return -1;
1279 } else {
1280 ins->rex |= ea_data.rex;
1281 length += ea_data.size;
1282 }
1283 }
1284 break;
1285
1286 default:
1287 nasm_panic(0, "internal instruction table corrupt"
1288 ": instruction code \\%o (0x%02X) given", c, c);
1289 break;
1290 }
1291 }
1292
1293 ins->rex &= rex_mask;
1294
1295 if (ins->rex & REX_NH) {
1296 if (ins->rex & REX_H) {
1297 nasm_error(ERR_NONFATAL, "instruction cannot use high registers");
1298 return -1;
1299 }
1300 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1301 }
1302
1303 switch (ins->prefixes[PPS_VEX]) {
1304 case P_EVEX:
1305 if (!(ins->rex & REX_EV))
1306 return -1;
1307 break;
1308 case P_VEX3:
1309 case P_VEX2:
1310 if (!(ins->rex & REX_V))
1311 return -1;
1312 break;
1313 default:
1314 break;
1315 }
1316
1317 if (ins->rex & (REX_V | REX_EV)) {
1318 int bad32 = REX_R|REX_W|REX_X|REX_B;
1319
1320 if (ins->rex & REX_H) {
1321 nasm_error(ERR_NONFATAL, "cannot use high register in AVX instruction");
1322 return -1;
1323 }
1324 switch (ins->vex_wlp & 060) {
1325 case 000:
1326 case 040:
1327 ins->rex &= ~REX_W;
1328 break;
1329 case 020:
1330 ins->rex |= REX_W;
1331 bad32 &= ~REX_W;
1332 break;
1333 case 060:
1334 /* Follow REX_W */
1335 break;
1336 }
1337
1338 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1339 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1340 return -1;
1341 } else if (!(ins->rex & REX_EV) &&
1342 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1343 nasm_error(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1344 return -1;
1345 }
1346 if (ins->rex & REX_EV)
1347 length += 4;
1348 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1349 ins->prefixes[PPS_VEX] == P_VEX3)
1350 length += 3;
1351 else
1352 length += 2;
1353 } else if (ins->rex & REX_MASK) {
1354 if (ins->rex & REX_H) {
1355 nasm_error(ERR_NONFATAL, "cannot use high register in rex instruction");
1356 return -1;
1357 } else if (bits == 64) {
1358 length++;
1359 } else if ((ins->rex & REX_L) &&
1360 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1361 iflag_ffs(&cpu) >= IF_X86_64) {
1362 /* LOCK-as-REX.R */
1363 assert_no_prefix(ins, PPS_LOCK);
1364 lockcheck = false; /* Already errored, no need for warning */
1365 length++;
1366 } else {
1367 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1368 return -1;
1369 }
1370 }
1371
1372 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1373 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1374 nasm_error(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1375 "instruction is not lockable");
1376 }
1377
1378 bad_hle_warn(ins, hleok);
1379
1380 /*
1381 * when BND prefix is set by DEFAULT directive,
1382 * BND prefix is added to every appropriate instruction line
1383 * unless it is overridden by NOBND prefix.
1384 */
1385 if (globalbnd &&
1386 (itemp_has(temp, IF_BND) && !has_prefix(ins, PPS_REP, P_NOBND)))
1387 ins->prefixes[PPS_REP] = P_BND;
1388
1389 /*
1390 * Add length of legacy prefixes
1391 */
1392 length += emit_prefix(NULL, bits, ins);
1393
1394 return length;
1395 }
1396
1397 static inline void emit_rex(struct out_data *data, insn *ins)
1398 {
1399 if (data->bits == 64) {
1400 if ((ins->rex & REX_MASK) &&
1401 !(ins->rex & (REX_V | REX_EV)) &&
1402 !ins->rex_done) {
1403 uint8_t rex = (ins->rex & REX_MASK) | REX_P;
1404 out_rawbyte(data, rex);
1405 ins->rex_done = true;
1406 }
1407 }
1408 }
1409
1410 static int emit_prefix(struct out_data *data, const int bits, insn *ins)
1411 {
1412 int bytes = 0;
1413 int j;
1414
1415 for (j = 0; j < MAXPREFIX; j++) {
1416 uint8_t c = 0;
1417 switch (ins->prefixes[j]) {
1418 case P_WAIT:
1419 c = 0x9B;
1420 break;
1421 case P_LOCK:
1422 c = 0xF0;
1423 break;
1424 case P_REPNE:
1425 case P_REPNZ:
1426 case P_XACQUIRE:
1427 case P_BND:
1428 c = 0xF2;
1429 break;
1430 case P_REPE:
1431 case P_REPZ:
1432 case P_REP:
1433 case P_XRELEASE:
1434 c = 0xF3;
1435 break;
1436 case R_CS:
1437 if (bits == 64) {
1438 nasm_error(ERR_WARNING | ERR_PASS2,
1439 "cs segment base generated, but will be ignored in 64-bit mode");
1440 }
1441 c = 0x2E;
1442 break;
1443 case R_DS:
1444 if (bits == 64) {
1445 nasm_error(ERR_WARNING | ERR_PASS2,
1446 "ds segment base generated, but will be ignored in 64-bit mode");
1447 }
1448 c = 0x3E;
1449 break;
1450 case R_ES:
1451 if (bits == 64) {
1452 nasm_error(ERR_WARNING | ERR_PASS2,
1453 "es segment base generated, but will be ignored in 64-bit mode");
1454 }
1455 c = 0x26;
1456 break;
1457 case R_FS:
1458 c = 0x64;
1459 break;
1460 case R_GS:
1461 c = 0x65;
1462 break;
1463 case R_SS:
1464 if (bits == 64) {
1465 nasm_error(ERR_WARNING | ERR_PASS2,
1466 "ss segment base generated, but will be ignored in 64-bit mode");
1467 }
1468 c = 0x36;
1469 break;
1470 case R_SEGR6:
1471 case R_SEGR7:
1472 nasm_error(ERR_NONFATAL,
1473 "segr6 and segr7 cannot be used as prefixes");
1474 break;
1475 case P_A16:
1476 if (bits == 64) {
1477 nasm_error(ERR_NONFATAL,
1478 "16-bit addressing is not supported "
1479 "in 64-bit mode");
1480 } else if (bits != 16)
1481 c = 0x67;
1482 break;
1483 case P_A32:
1484 if (bits != 32)
1485 c = 0x67;
1486 break;
1487 case P_A64:
1488 if (bits != 64) {
1489 nasm_error(ERR_NONFATAL,
1490 "64-bit addressing is only supported "
1491 "in 64-bit mode");
1492 }
1493 break;
1494 case P_ASP:
1495 c = 0x67;
1496 break;
1497 case P_O16:
1498 if (bits != 16)
1499 c = 0x66;
1500 break;
1501 case P_O32:
1502 if (bits == 16)
1503 c = 0x66;
1504 break;
1505 case P_O64:
1506 /* REX.W */
1507 break;
1508 case P_OSP:
1509 c = 0x66;
1510 break;
1511 case P_EVEX:
1512 case P_VEX3:
1513 case P_VEX2:
1514 case P_NOBND:
1515 case P_none:
1516 break;
1517 default:
1518 nasm_panic(0, "invalid instruction prefix");
1519 }
1520 if (c) {
1521 if (data)
1522 out_rawbyte(data, c);
1523 bytes++;
1524 }
1525 }
1526 return bytes;
1527 }
1528
1529 static void gencode(struct out_data *data, insn *ins)
1530 {
1531 uint8_t c;
1532 uint8_t bytes[4];
1533 int64_t size;
1534 int op1, op2;
1535 struct operand *opx;
1536 const uint8_t *codes = data->itemp->code;
1537 uint8_t opex = 0;
1538 enum ea_type eat = EA_SCALAR;
1539 int r;
1540 const int bits = data->bits;
1541 const char *errmsg;
1542
1543 ins->rex_done = false;
1544
1545 emit_prefix(data, bits, ins);
1546
1547 while (*codes) {
1548 c = *codes++;
1549 op1 = (c & 3) + ((opex & 1) << 2);
1550 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1551 opx = &ins->oprs[op1];
1552 opex = 0; /* For the next iteration */
1553
1554
1555 switch (c) {
1556 case 01:
1557 case 02:
1558 case 03:
1559 case 04:
1560 emit_rex(data, ins);
1561 out_rawdata(data, codes, c);
1562 codes += c;
1563 break;
1564
1565 case 05:
1566 case 06:
1567 case 07:
1568 opex = c;
1569 break;
1570
1571 case4(010):
1572 emit_rex(data, ins);
1573 out_rawbyte(data, *codes++ + (regval(opx) & 7));
1574 break;
1575
1576 case4(014):
1577 break;
1578
1579 case4(020):
1580 if (opx->offset < -256 || opx->offset > 255)
1581 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1582 "byte value exceeds bounds");
1583 out_imm(data, opx, 1, OUT_WRAP);
1584 break;
1585
1586 case4(024):
1587 if (opx->offset < 0 || opx->offset > 255)
1588 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1589 "unsigned byte value exceeds bounds");
1590 out_imm(data, opx, 1, OUT_UNSIGNED);
1591 break;
1592
1593 case4(030):
1594 warn_overflow_opd(opx, 2);
1595 out_imm(data, opx, 2, OUT_WRAP);
1596 break;
1597
1598 case4(034):
1599 if (opx->type & (BITS16 | BITS32))
1600 size = (opx->type & BITS16) ? 2 : 4;
1601 else
1602 size = (bits == 16) ? 2 : 4;
1603 warn_overflow_opd(opx, size);
1604 out_imm(data, opx, size, OUT_WRAP);
1605 break;
1606
1607 case4(040):
1608 warn_overflow_opd(opx, 4);
1609 out_imm(data, opx, 4, OUT_WRAP);
1610 break;
1611
1612 case4(044):
1613 size = ins->addr_size >> 3;
1614 warn_overflow_opd(opx, size);
1615 out_imm(data, opx, size, OUT_WRAP);
1616 break;
1617
1618 case4(050):
1619 if (opx->segment == data->segment) {
1620 int64_t delta = opx->offset - data->offset
1621 - (data->inslen - data->insoffs);
1622 if (delta > 127 || delta < -128)
1623 nasm_error(ERR_NONFATAL, "short jump is out of range");
1624 }
1625 out_reladdr(data, opx, 1);
1626 break;
1627
1628 case4(054):
1629 out_imm(data, opx, 8, OUT_WRAP);
1630 break;
1631
1632 case4(060):
1633 out_reladdr(data, opx, 2);
1634 break;
1635
1636 case4(064):
1637 if (opx->type & (BITS16 | BITS32 | BITS64))
1638 size = (opx->type & BITS16) ? 2 : 4;
1639 else
1640 size = (bits == 16) ? 2 : 4;
1641
1642 out_reladdr(data, opx, size);
1643 break;
1644
1645 case4(070):
1646 out_reladdr(data, opx, 4);
1647 break;
1648
1649 case4(074):
1650 if (opx->segment == NO_SEG)
1651 nasm_error(ERR_NONFATAL, "value referenced by FAR is not"
1652 " relocatable");
1653 out_segment(data, opx);
1654 break;
1655
1656 case 0172:
1657 {
1658 int mask = ins->prefixes[PPS_VEX] == P_EVEX ? 7 : 15;
1659 const struct operand *opy;
1660
1661 c = *codes++;
1662 opx = &ins->oprs[c >> 3];
1663 opy = &ins->oprs[c & 7];
1664 if (!absolute_op(opy)) {
1665 nasm_error(ERR_NONFATAL,
1666 "non-absolute expression not permitted as argument %d",
1667 c & 7);
1668 } else if (opy->offset & ~mask) {
1669 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1670 "is4 argument exceeds bounds");
1671 }
1672 c = opy->offset & mask;
1673 goto emit_is4;
1674 }
1675
1676 case 0173:
1677 c = *codes++;
1678 opx = &ins->oprs[c >> 4];
1679 c &= 15;
1680 goto emit_is4;
1681
1682 case4(0174):
1683 c = 0;
1684 emit_is4:
1685 r = nasm_regvals[opx->basereg];
1686 out_rawbyte(data, (r << 4) | ((r & 0x10) >> 1) | c);
1687 break;
1688
1689 case4(0254):
1690 if (absolute_op(opx) &&
1691 (int32_t)opx->offset != (int64_t)opx->offset) {
1692 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1693 "signed dword immediate exceeds bounds");
1694 }
1695 out_imm(data, opx, 4, OUT_SIGNED);
1696 break;
1697
1698 case4(0240):
1699 case 0250:
1700 codes += 3;
1701 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1702 EVEX_P2Z | EVEX_P2AAA, 2);
1703 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1704 bytes[0] = 0x62;
1705 /* EVEX.X can be set by either REX or EVEX for different reasons */
1706 bytes[1] = ((((ins->rex & 7) << 5) |
1707 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1708 (ins->vex_cm & EVEX_P0MM);
1709 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1710 ((~ins->vexreg & 15) << 3) |
1711 (1 << 2) | (ins->vex_wlp & 3);
1712 bytes[3] = ins->evex_p[2];
1713 out_rawdata(data, bytes, 4);
1714 break;
1715
1716 case4(0260):
1717 case 0270:
1718 codes += 2;
1719 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1720 ins->prefixes[PPS_VEX] == P_VEX3) {
1721 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1722 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1723 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1724 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1725 out_rawdata(data, bytes, 3);
1726 } else {
1727 bytes[0] = 0xc5;
1728 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1729 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1730 out_rawdata(data, bytes, 2);
1731 }
1732 break;
1733
1734 case 0271:
1735 case 0272:
1736 case 0273:
1737 break;
1738
1739 case4(0274):
1740 {
1741 uint64_t uv, um;
1742 int s;
1743
1744 if (absolute_op(opx)) {
1745 if (ins->rex & REX_W)
1746 s = 64;
1747 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1748 s = 16;
1749 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1750 s = 32;
1751 else
1752 s = bits;
1753
1754 um = (uint64_t)2 << (s-1);
1755 uv = opx->offset;
1756
1757 if (uv > 127 && uv < (uint64_t)-128 &&
1758 (uv < um-128 || uv > um-1)) {
1759 /* If this wasn't explicitly byte-sized, warn as though we
1760 * had fallen through to the imm16/32/64 case.
1761 */
1762 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1763 "%s value exceeds bounds",
1764 (opx->type & BITS8) ? "signed byte" :
1765 s == 16 ? "word" :
1766 s == 32 ? "dword" :
1767 "signed dword");
1768 }
1769
1770 /* Output as a raw byte to avoid byte overflow check */
1771 out_rawbyte(data, (uint8_t)uv);
1772 } else {
1773 out_imm(data, opx, 1, OUT_WRAP); /* XXX: OUT_SIGNED? */
1774 }
1775 break;
1776 }
1777
1778 case4(0300):
1779 break;
1780
1781 case 0310:
1782 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16))
1783 out_rawbyte(data, 0x67);
1784 break;
1785
1786 case 0311:
1787 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32))
1788 out_rawbyte(data, 0x67);
1789 break;
1790
1791 case 0312:
1792 break;
1793
1794 case 0313:
1795 ins->rex = 0;
1796 break;
1797
1798 case4(0314):
1799 break;
1800
1801 case 0320:
1802 case 0321:
1803 break;
1804
1805 case 0322:
1806 case 0323:
1807 break;
1808
1809 case 0324:
1810 ins->rex |= REX_W;
1811 break;
1812
1813 case 0325:
1814 break;
1815
1816 case 0326:
1817 break;
1818
1819 case 0330:
1820 out_rawbyte(data, *codes++ ^ get_cond_opcode(ins->condition));
1821 break;
1822
1823 case 0331:
1824 break;
1825
1826 case 0332:
1827 case 0333:
1828 out_rawbyte(data, c - 0332 + 0xF2);
1829 break;
1830
1831 case 0334:
1832 if (ins->rex & REX_R)
1833 out_rawbyte(data, 0xF0);
1834 ins->rex &= ~(REX_L|REX_R);
1835 break;
1836
1837 case 0335:
1838 break;
1839
1840 case 0336:
1841 case 0337:
1842 break;
1843
1844 case 0340:
1845 if (ins->oprs[0].segment != NO_SEG)
1846 nasm_panic(0, "non-constant BSS size in pass two");
1847
1848 out_reserve(data, ins->oprs[0].offset);
1849 break;
1850
1851 case 0341:
1852 break;
1853
1854 case 0360:
1855 break;
1856
1857 case 0361:
1858 out_rawbyte(data, 0x66);
1859 break;
1860
1861 case 0364:
1862 case 0365:
1863 break;
1864
1865 case 0366:
1866 case 0367:
1867 out_rawbyte(data, c - 0366 + 0x66);
1868 break;
1869
1870 case3(0370):
1871 break;
1872
1873 case 0373:
1874 out_rawbyte(data, bits == 16 ? 3 : 5);
1875 break;
1876
1877 case 0374:
1878 eat = EA_XMMVSIB;
1879 break;
1880
1881 case 0375:
1882 eat = EA_YMMVSIB;
1883 break;
1884
1885 case 0376:
1886 eat = EA_ZMMVSIB;
1887 break;
1888
1889 case4(0100):
1890 case4(0110):
1891 case4(0120):
1892 case4(0130):
1893 case4(0200):
1894 case4(0204):
1895 case4(0210):
1896 case4(0214):
1897 case4(0220):
1898 case4(0224):
1899 case4(0230):
1900 case4(0234):
1901 {
1902 ea ea_data;
1903 int rfield;
1904 opflags_t rflags;
1905 uint8_t *p;
1906 struct operand *opy = &ins->oprs[op2];
1907
1908 if (c <= 0177) {
1909 /* pick rfield from operand b (opx) */
1910 rflags = regflag(opx);
1911 rfield = nasm_regvals[opx->basereg];
1912 } else {
1913 /* rfield is constant */
1914 rflags = 0;
1915 rfield = c & 7;
1916 }
1917
1918 if (process_ea(opy, &ea_data, bits,
1919 rfield, rflags, ins, &errmsg) != eat)
1920 nasm_error(ERR_NONFATAL, "%s", errmsg);
1921
1922 p = bytes;
1923 *p++ = ea_data.modrm;
1924 if (ea_data.sib_present)
1925 *p++ = ea_data.sib;
1926 out_rawdata(data, bytes, p - bytes);
1927
1928 /*
1929 * Make sure the address gets the right offset in case
1930 * the line breaks in the .lst file (BR 1197827)
1931 */
1932
1933 if (ea_data.bytes) {
1934 /* use compressed displacement, if available */
1935 if (ea_data.disp8) {
1936 out_rawbyte(data, ea_data.disp8);
1937 } else if (ea_data.rip) {
1938 out_reladdr(data, opy, ea_data.bytes);
1939 } else {
1940 int asize = ins->addr_size >> 3;
1941
1942 if (overflow_general(opy->offset, asize) ||
1943 signed_bits(opy->offset, ins->addr_size) !=
1944 signed_bits(opy->offset, ea_data.bytes << 3))
1945 warn_overflow(ea_data.bytes);
1946
1947 out_imm(data, opy, ea_data.bytes,
1948 (asize > ea_data.bytes)
1949 ? OUT_SIGNED : OUT_WRAP);
1950 }
1951 }
1952 }
1953 break;
1954
1955 default:
1956 nasm_panic(0, "internal instruction table corrupt"
1957 ": instruction code \\%o (0x%02X) given", c, c);
1958 break;
1959 }
1960 }
1961 }
1962
1963 static opflags_t regflag(const operand * o)
1964 {
1965 if (!is_register(o->basereg))
1966 nasm_panic(0, "invalid operand passed to regflag()");
1967 return nasm_reg_flags[o->basereg];
1968 }
1969
1970 static int32_t regval(const operand * o)
1971 {
1972 if (!is_register(o->basereg))
1973 nasm_panic(0, "invalid operand passed to regval()");
1974 return nasm_regvals[o->basereg];
1975 }
1976
1977 static int op_rexflags(const operand * o, int mask)
1978 {
1979 opflags_t flags;
1980 int val;
1981
1982 if (!is_register(o->basereg))
1983 nasm_panic(0, "invalid operand passed to op_rexflags()");
1984
1985 flags = nasm_reg_flags[o->basereg];
1986 val = nasm_regvals[o->basereg];
1987
1988 return rexflags(val, flags, mask);
1989 }
1990
1991 static int rexflags(int val, opflags_t flags, int mask)
1992 {
1993 int rex = 0;
1994
1995 if (val >= 0 && (val & 8))
1996 rex |= REX_B|REX_X|REX_R;
1997 if (flags & BITS64)
1998 rex |= REX_W;
1999 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
2000 rex |= REX_H;
2001 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
2002 rex |= REX_P;
2003
2004 return rex & mask;
2005 }
2006
2007 static int evexflags(int val, decoflags_t deco,
2008 int mask, uint8_t byte)
2009 {
2010 int evex = 0;
2011
2012 switch (byte) {
2013 case 0:
2014 if (val >= 0 && (val & 16))
2015 evex |= (EVEX_P0RP | EVEX_P0X);
2016 break;
2017 case 2:
2018 if (val >= 0 && (val & 16))
2019 evex |= EVEX_P2VP;
2020 if (deco & Z)
2021 evex |= EVEX_P2Z;
2022 if (deco & OPMASK_MASK)
2023 evex |= deco & EVEX_P2AAA;
2024 break;
2025 }
2026 return evex & mask;
2027 }
2028
2029 static int op_evexflags(const operand * o, int mask, uint8_t byte)
2030 {
2031 int val;
2032
2033 val = nasm_regvals[o->basereg];
2034
2035 return evexflags(val, o->decoflags, mask, byte);
2036 }
2037
2038 static enum match_result find_match(const struct itemplate **tempp,
2039 insn *instruction,
2040 int32_t segment, int64_t offset, int bits)
2041 {
2042 const struct itemplate *temp;
2043 enum match_result m, merr;
2044 opflags_t xsizeflags[MAX_OPERANDS];
2045 bool opsizemissing = false;
2046 int8_t broadcast = instruction->evex_brerop;
2047 int i;
2048
2049 /* broadcasting uses a different data element size */
2050 for (i = 0; i < instruction->operands; i++)
2051 if (i == broadcast)
2052 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
2053 else
2054 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
2055
2056 merr = MERR_INVALOP;
2057
2058 for (temp = nasm_instructions[instruction->opcode];
2059 temp->opcode != I_none; temp++) {
2060 m = matches(temp, instruction, bits);
2061 if (m == MOK_JUMP) {
2062 if (jmp_match(segment, offset, bits, instruction, temp))
2063 m = MOK_GOOD;
2064 else
2065 m = MERR_INVALOP;
2066 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2067 /*
2068 * Missing operand size and a candidate for fuzzy matching...
2069 */
2070 for (i = 0; i < temp->operands; i++)
2071 if (i == broadcast)
2072 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2073 else
2074 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2075 opsizemissing = true;
2076 }
2077 if (m > merr)
2078 merr = m;
2079 if (merr == MOK_GOOD)
2080 goto done;
2081 }
2082
2083 /* No match, but see if we can get a fuzzy operand size match... */
2084 if (!opsizemissing)
2085 goto done;
2086
2087 for (i = 0; i < instruction->operands; i++) {
2088 /*
2089 * We ignore extrinsic operand sizes on registers, so we should
2090 * never try to fuzzy-match on them. This also resolves the case
2091 * when we have e.g. "xmmrm128" in two different positions.
2092 */
2093 if (is_class(REGISTER, instruction->oprs[i].type))
2094 continue;
2095
2096 /* This tests if xsizeflags[i] has more than one bit set */
2097 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2098 goto done; /* No luck */
2099
2100 if (i == broadcast) {
2101 instruction->oprs[i].decoflags |= xsizeflags[i];
2102 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2103 BITS32 : BITS64);
2104 } else {
2105 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2106 }
2107 }
2108
2109 /* Try matching again... */
2110 for (temp = nasm_instructions[instruction->opcode];
2111 temp->opcode != I_none; temp++) {
2112 m = matches(temp, instruction, bits);
2113 if (m == MOK_JUMP) {
2114 if (jmp_match(segment, offset, bits, instruction, temp))
2115 m = MOK_GOOD;
2116 else
2117 m = MERR_INVALOP;
2118 }
2119 if (m > merr)
2120 merr = m;
2121 if (merr == MOK_GOOD)
2122 goto done;
2123 }
2124
2125 done:
2126 *tempp = temp;
2127 return merr;
2128 }
2129
2130 static uint8_t get_broadcast_num(opflags_t opflags, opflags_t brsize)
2131 {
2132 unsigned int opsize = (opflags & SIZE_MASK) >> SIZE_SHIFT;
2133 uint8_t brcast_num;
2134
2135 if (brsize > BITS64)
2136 nasm_error(ERR_FATAL,
2137 "size of broadcasting element is greater than 64 bits");
2138
2139 /*
2140 * The shift term is to take care of the extra BITS80 inserted
2141 * between BITS64 and BITS128.
2142 */
2143 brcast_num = ((opsize / (BITS64 >> SIZE_SHIFT)) * (BITS64 / brsize))
2144 >> (opsize > (BITS64 >> SIZE_SHIFT));
2145
2146 return brcast_num;
2147 }
2148
2149 static enum match_result matches(const struct itemplate *itemp,
2150 insn *instruction, int bits)
2151 {
2152 opflags_t size[MAX_OPERANDS], asize;
2153 bool opsizemissing = false;
2154 int i, oprs;
2155
2156 /*
2157 * Check the opcode
2158 */
2159 if (itemp->opcode != instruction->opcode)
2160 return MERR_INVALOP;
2161
2162 /*
2163 * Count the operands
2164 */
2165 if (itemp->operands != instruction->operands)
2166 return MERR_INVALOP;
2167
2168 /*
2169 * Is it legal?
2170 */
2171 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2172 return MERR_INVALOP;
2173
2174 /*
2175 * {evex} available?
2176 */
2177 switch (instruction->prefixes[PPS_VEX]) {
2178 case P_EVEX:
2179 if (!itemp_has(itemp, IF_EVEX))
2180 return MERR_ENCMISMATCH;
2181 break;
2182 case P_VEX3:
2183 case P_VEX2:
2184 if (!itemp_has(itemp, IF_VEX))
2185 return MERR_ENCMISMATCH;
2186 break;
2187 default:
2188 break;
2189 }
2190
2191 /*
2192 * Check that no spurious colons or TOs are present
2193 */
2194 for (i = 0; i < itemp->operands; i++)
2195 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2196 return MERR_INVALOP;
2197
2198 /*
2199 * Process size flags
2200 */
2201 switch (itemp_smask(itemp)) {
2202 case IF_GENBIT(IF_SB):
2203 asize = BITS8;
2204 break;
2205 case IF_GENBIT(IF_SW):
2206 asize = BITS16;
2207 break;
2208 case IF_GENBIT(IF_SD):
2209 asize = BITS32;
2210 break;
2211 case IF_GENBIT(IF_SQ):
2212 asize = BITS64;
2213 break;
2214 case IF_GENBIT(IF_SO):
2215 asize = BITS128;
2216 break;
2217 case IF_GENBIT(IF_SY):
2218 asize = BITS256;
2219 break;
2220 case IF_GENBIT(IF_SZ):
2221 asize = BITS512;
2222 break;
2223 case IF_GENBIT(IF_SIZE):
2224 switch (bits) {
2225 case 16:
2226 asize = BITS16;
2227 break;
2228 case 32:
2229 asize = BITS32;
2230 break;
2231 case 64:
2232 asize = BITS64;
2233 break;
2234 default:
2235 asize = 0;
2236 break;
2237 }
2238 break;
2239 default:
2240 asize = 0;
2241 break;
2242 }
2243
2244 if (itemp_armask(itemp)) {
2245 /* S- flags only apply to a specific operand */
2246 i = itemp_arg(itemp);
2247 memset(size, 0, sizeof size);
2248 size[i] = asize;
2249 } else {
2250 /* S- flags apply to all operands */
2251 for (i = 0; i < MAX_OPERANDS; i++)
2252 size[i] = asize;
2253 }
2254
2255 /*
2256 * Check that the operand flags all match up,
2257 * it's a bit tricky so lets be verbose:
2258 *
2259 * 1) Find out the size of operand. If instruction
2260 * doesn't have one specified -- we're trying to
2261 * guess it either from template (IF_S* flag) or
2262 * from code bits.
2263 *
2264 * 2) If template operand do not match the instruction OR
2265 * template has an operand size specified AND this size differ
2266 * from which instruction has (perhaps we got it from code bits)
2267 * we are:
2268 * a) Check that only size of instruction and operand is differ
2269 * other characteristics do match
2270 * b) Perhaps it's a register specified in instruction so
2271 * for such a case we just mark that operand as "size
2272 * missing" and this will turn on fuzzy operand size
2273 * logic facility (handled by a caller)
2274 */
2275 for (i = 0; i < itemp->operands; i++) {
2276 opflags_t type = instruction->oprs[i].type;
2277 decoflags_t deco = instruction->oprs[i].decoflags;
2278 decoflags_t ideco = itemp->deco[i];
2279 bool is_broadcast = deco & BRDCAST_MASK;
2280 uint8_t brcast_num = 0;
2281 opflags_t template_opsize, insn_opsize;
2282
2283 if (!(type & SIZE_MASK))
2284 type |= size[i];
2285
2286 insn_opsize = type & SIZE_MASK;
2287 if (!is_broadcast) {
2288 template_opsize = itemp->opd[i] & SIZE_MASK;
2289 } else {
2290 decoflags_t deco_brsize = ideco & BRSIZE_MASK;
2291
2292 if (~ideco & BRDCAST_MASK)
2293 return MERR_BRNOTHERE;
2294
2295 /*
2296 * when broadcasting, the element size depends on
2297 * the instruction type. decorator flag should match.
2298 */
2299 if (deco_brsize) {
2300 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2301 /* calculate the proper number : {1to<brcast_num>} */
2302 brcast_num = get_broadcast_num(itemp->opd[i], template_opsize);
2303 } else {
2304 template_opsize = 0;
2305 }
2306 }
2307
2308 if (~ideco & deco & OPMASK_MASK)
2309 return MERR_MASKNOTHERE;
2310
2311 if (~ideco & deco & (Z_MASK|STATICRND_MASK|SAE_MASK))
2312 return MERR_DECONOTHERE;
2313
2314 if (itemp->opd[i] & ~type & ~SIZE_MASK) {
2315 return MERR_INVALOP;
2316 } else if (template_opsize) {
2317 if (template_opsize != insn_opsize) {
2318 if (insn_opsize) {
2319 return MERR_INVALOP;
2320 } else if (!is_class(REGISTER, type)) {
2321 /*
2322 * Note: we don't honor extrinsic operand sizes for registers,
2323 * so "missing operand size" for a register should be
2324 * considered a wildcard match rather than an error.
2325 */
2326 opsizemissing = true;
2327 }
2328 } else if (is_broadcast &&
2329 (brcast_num !=
2330 (2U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2331 /*
2332 * broadcasting opsize matches but the number of repeated memory
2333 * element does not match.
2334 * if 64b double precision float is broadcasted to ymm (256b),
2335 * broadcasting decorator must be {1to4}.
2336 */
2337 return MERR_BRNUMMISMATCH;
2338 }
2339 }
2340 }
2341
2342 if (opsizemissing)
2343 return MERR_OPSIZEMISSING;
2344
2345 /*
2346 * Check operand sizes
2347 */
2348 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2349 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2350 for (i = 0; i < oprs; i++) {
2351 asize = itemp->opd[i] & SIZE_MASK;
2352 if (asize) {
2353 for (i = 0; i < oprs; i++)
2354 size[i] = asize;
2355 break;
2356 }
2357 }
2358 } else {
2359 oprs = itemp->operands;
2360 }
2361
2362 for (i = 0; i < itemp->operands; i++) {
2363 if (!(itemp->opd[i] & SIZE_MASK) &&
2364 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2365 return MERR_OPSIZEMISMATCH;
2366 }
2367
2368 /*
2369 * Check template is okay at the set cpu level
2370 */
2371 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2372 return MERR_BADCPU;
2373
2374 /*
2375 * Verify the appropriate long mode flag.
2376 */
2377 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2378 return MERR_BADMODE;
2379
2380 /*
2381 * If we have a HLE prefix, look for the NOHLE flag
2382 */
2383 if (itemp_has(itemp, IF_NOHLE) &&
2384 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2385 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2386 return MERR_BADHLE;
2387
2388 /*
2389 * Check if special handling needed for Jumps
2390 */
2391 if ((itemp->code[0] & ~1) == 0370)
2392 return MOK_JUMP;
2393
2394 /*
2395 * Check if BND prefix is allowed.
2396 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2397 */
2398 if (!itemp_has(itemp, IF_BND) &&
2399 (has_prefix(instruction, PPS_REP, P_BND) ||
2400 has_prefix(instruction, PPS_REP, P_NOBND)))
2401 return MERR_BADBND;
2402 else if (itemp_has(itemp, IF_BND) &&
2403 (has_prefix(instruction, PPS_REP, P_REPNE) ||
2404 has_prefix(instruction, PPS_REP, P_REPNZ)))
2405 return MERR_BADREPNE;
2406
2407 return MOK_GOOD;
2408 }
2409
2410 /*
2411 * Check if ModR/M.mod should/can be 01.
2412 * - EAF_BYTEOFFS is set
2413 * - offset can fit in a byte when EVEX is not used
2414 * - offset can be compressed when EVEX is used
2415 */
2416 #define IS_MOD_01() (!(input->eaflags & EAF_WORDOFFS) && \
2417 (ins->rex & REX_EV ? seg == NO_SEG && !forw_ref && \
2418 is_disp8n(input, ins, &output->disp8) : \
2419 input->eaflags & EAF_BYTEOFFS || (o >= -128 && \
2420 o <= 127 && seg == NO_SEG && !forw_ref)))
2421
2422 static enum ea_type process_ea(operand *input, ea *output, int bits,
2423 int rfield, opflags_t rflags, insn *ins,
2424 const char **errmsg)
2425 {
2426 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2427 int addrbits = ins->addr_size;
2428 int eaflags = input->eaflags;
2429
2430 *errmsg = "invalid effective address"; /* Default error message */
2431
2432 output->type = EA_SCALAR;
2433 output->rip = false;
2434 output->disp8 = 0;
2435
2436 /* REX flags for the rfield operand */
2437 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2438 /* EVEX.R' flag for the REG operand */
2439 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2440
2441 if (is_class(REGISTER, input->type)) {
2442 /*
2443 * It's a direct register.
2444 */
2445 if (!is_register(input->basereg))
2446 goto err;
2447
2448 if (!is_reg_class(REG_EA, input->basereg))
2449 goto err;
2450
2451 /* broadcasting is not available with a direct register operand. */
2452 if (input->decoflags & BRDCAST_MASK) {
2453 *errmsg = "broadcast not allowed with register operand";
2454 goto err;
2455 }
2456
2457 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2458 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2459 output->sib_present = false; /* no SIB necessary */
2460 output->bytes = 0; /* no offset necessary either */
2461 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2462 } else {
2463 /*
2464 * It's a memory reference.
2465 */
2466
2467 /* Embedded rounding or SAE is not available with a mem ref operand. */
2468 if (input->decoflags & (ER | SAE)) {
2469 *errmsg = "embedded rounding is available only with "
2470 "register-register operations";
2471 goto err;
2472 }
2473
2474 if (input->basereg == -1 &&
2475 (input->indexreg == -1 || input->scale == 0)) {
2476 /*
2477 * It's a pure offset.
2478 */
2479 if (bits == 64 && ((input->type & IP_REL) == IP_REL)) {
2480 if (input->segment == NO_SEG ||
2481 (input->opflags & OPFLAG_RELATIVE)) {
2482 nasm_error(ERR_WARNING | ERR_PASS2,
2483 "absolute address can not be RIP-relative");
2484 input->type &= ~IP_REL;
2485 input->type |= MEMORY;
2486 }
2487 }
2488
2489 if (bits == 64 &&
2490 !(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
2491 *errmsg = "RIP-relative addressing is prohibited for MIB";
2492 goto err;
2493 }
2494
2495 if (eaflags & EAF_BYTEOFFS ||
2496 (eaflags & EAF_WORDOFFS &&
2497 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2498 nasm_error(ERR_WARNING | ERR_PASS1,
2499 "displacement size ignored on absolute address");
2500 }
2501
2502 if (bits == 64 && (~input->type & IP_REL)) {
2503 output->sib_present = true;
2504 output->sib = GEN_SIB(0, 4, 5);
2505 output->bytes = 4;
2506 output->modrm = GEN_MODRM(0, rfield, 4);
2507 output->rip = false;
2508 } else {
2509 output->sib_present = false;
2510 output->bytes = (addrbits != 16 ? 4 : 2);
2511 output->modrm = GEN_MODRM(0, rfield,
2512 (addrbits != 16 ? 5 : 6));
2513 output->rip = bits == 64;
2514 }
2515 } else {
2516 /*
2517 * It's an indirection.
2518 */
2519 int i = input->indexreg, b = input->basereg, s = input->scale;
2520 int32_t seg = input->segment;
2521 int hb = input->hintbase, ht = input->hinttype;
2522 int t, it, bt; /* register numbers */
2523 opflags_t x, ix, bx; /* register flags */
2524
2525 if (s == 0)
2526 i = -1; /* make this easy, at least */
2527
2528 if (is_register(i)) {
2529 it = nasm_regvals[i];
2530 ix = nasm_reg_flags[i];
2531 } else {
2532 it = -1;
2533 ix = 0;
2534 }
2535
2536 if (is_register(b)) {
2537 bt = nasm_regvals[b];
2538 bx = nasm_reg_flags[b];
2539 } else {
2540 bt = -1;
2541 bx = 0;
2542 }
2543
2544 /* if either one are a vector register... */
2545 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2546 opflags_t sok = BITS32 | BITS64;
2547 int32_t o = input->offset;
2548 int mod, scale, index, base;
2549
2550 /*
2551 * For a vector SIB, one has to be a vector and the other,
2552 * if present, a GPR. The vector must be the index operand.
2553 */
2554 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2555 if (s == 0)
2556 s = 1;
2557 else if (s != 1)
2558 goto err;
2559
2560 t = bt, bt = it, it = t;
2561 x = bx, bx = ix, ix = x;
2562 }
2563
2564 if (bt != -1) {
2565 if (REG_GPR & ~bx)
2566 goto err;
2567 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2568 sok &= bx;
2569 else
2570 goto err;
2571 }
2572
2573 /*
2574 * While we're here, ensure the user didn't specify
2575 * WORD or QWORD
2576 */
2577 if (input->disp_size == 16 || input->disp_size == 64)
2578 goto err;
2579
2580 if (addrbits == 16 ||
2581 (addrbits == 32 && !(sok & BITS32)) ||
2582 (addrbits == 64 && !(sok & BITS64)))
2583 goto err;
2584
2585 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2586 : ((ix & YMMREG & ~REG_EA)
2587 ? EA_YMMVSIB : EA_XMMVSIB));
2588
2589 output->rex |= rexflags(it, ix, REX_X);
2590 output->rex |= rexflags(bt, bx, REX_B);
2591 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2592
2593 index = it & 7; /* it is known to be != -1 */
2594
2595 switch (s) {
2596 case 1:
2597 scale = 0;
2598 break;
2599 case 2:
2600 scale = 1;
2601 break;
2602 case 4:
2603 scale = 2;
2604 break;
2605 case 8:
2606 scale = 3;
2607 break;
2608 default: /* then what the smeg is it? */
2609 goto err; /* panic */
2610 }
2611
2612 if (bt == -1) {
2613 base = 5;
2614 mod = 0;
2615 } else {
2616 base = (bt & 7);
2617 if (base != REG_NUM_EBP && o == 0 &&
2618 seg == NO_SEG && !forw_ref &&
2619 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2620 mod = 0;
2621 else if (IS_MOD_01())
2622 mod = 1;
2623 else
2624 mod = 2;
2625 }
2626
2627 output->sib_present = true;
2628 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2629 output->modrm = GEN_MODRM(mod, rfield, 4);
2630 output->sib = GEN_SIB(scale, index, base);
2631 } else if ((ix|bx) & (BITS32|BITS64)) {
2632 /*
2633 * it must be a 32/64-bit memory reference. Firstly we have
2634 * to check that all registers involved are type E/Rxx.
2635 */
2636 opflags_t sok = BITS32 | BITS64;
2637 int32_t o = input->offset;
2638
2639 if (it != -1) {
2640 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2641 sok &= ix;
2642 else
2643 goto err;
2644 }
2645
2646 if (bt != -1) {
2647 if (REG_GPR & ~bx)
2648 goto err; /* Invalid register */
2649 if (~sok & bx & SIZE_MASK)
2650 goto err; /* Invalid size */
2651 sok &= bx;
2652 }
2653
2654 /*
2655 * While we're here, ensure the user didn't specify
2656 * WORD or QWORD
2657 */
2658 if (input->disp_size == 16 || input->disp_size == 64)
2659 goto err;
2660
2661 if (addrbits == 16 ||
2662 (addrbits == 32 && !(sok & BITS32)) ||
2663 (addrbits == 64 && !(sok & BITS64)))
2664 goto err;
2665
2666 /* now reorganize base/index */
2667 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2668 ((hb == b && ht == EAH_NOTBASE) ||
2669 (hb == i && ht == EAH_MAKEBASE))) {
2670 /* swap if hints say so */
2671 t = bt, bt = it, it = t;
2672 x = bx, bx = ix, ix = x;
2673 }
2674
2675 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2676 /* make single reg base, unless hint */
2677 bt = it, bx = ix, it = -1, ix = 0;
2678 }
2679 if (eaflags & EAF_MIB) {
2680 /* only for mib operands */
2681 if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
2682 /*
2683 * make a single reg index [reg*1].
2684 * gas uses this form for an explicit index register.
2685 */
2686 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2687 }
2688 if ((ht == EAH_SUMMED) && bt == -1) {
2689 /* separate once summed index into [base, index] */
2690 bt = it, bx = ix, s--;
2691 }
2692 } else {
2693 if (((s == 2 && it != REG_NUM_ESP &&
2694 (!(eaflags & EAF_TIMESTWO) || (ht == EAH_SUMMED))) ||
2695 s == 3 || s == 5 || s == 9) && bt == -1) {
2696 /* convert 3*EAX to EAX+2*EAX */
2697 bt = it, bx = ix, s--;
2698 }
2699 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2700 (eaflags & EAF_TIMESTWO) &&
2701 (hb == b && ht == EAH_NOTBASE)) {
2702 /*
2703 * convert [NOSPLIT EAX*1]
2704 * to sib format with 0x0 displacement - [EAX*1+0].
2705 */
2706 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2707 }
2708 }
2709 if (s == 1 && it == REG_NUM_ESP) {
2710 /* swap ESP into base if scale is 1 */
2711 t = it, it = bt, bt = t;
2712 x = ix, ix = bx, bx = x;
2713 }
2714 if (it == REG_NUM_ESP ||
2715 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2716 goto err; /* wrong, for various reasons */
2717
2718 output->rex |= rexflags(it, ix, REX_X);
2719 output->rex |= rexflags(bt, bx, REX_B);
2720
2721 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2722 /* no SIB needed */
2723 int mod, rm;
2724
2725 if (bt == -1) {
2726 rm = 5;
2727 mod = 0;
2728 } else {
2729 rm = (bt & 7);
2730 if (rm != REG_NUM_EBP && o == 0 &&
2731 seg == NO_SEG && !forw_ref &&
2732 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2733 mod = 0;
2734 else if (IS_MOD_01())
2735 mod = 1;
2736 else
2737 mod = 2;
2738 }
2739
2740 output->sib_present = false;
2741 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2742 output->modrm = GEN_MODRM(mod, rfield, rm);
2743 } else {
2744 /* we need a SIB */
2745 int mod, scale, index, base;
2746
2747 if (it == -1)
2748 index = 4, s = 1;
2749 else
2750 index = (it & 7);
2751
2752 switch (s) {
2753 case 1:
2754 scale = 0;
2755 break;
2756 case 2:
2757 scale = 1;
2758 break;
2759 case 4:
2760 scale = 2;
2761 break;
2762 case 8:
2763 scale = 3;
2764 break;
2765 default: /* then what the smeg is it? */
2766 goto err; /* panic */
2767 }
2768
2769 if (bt == -1) {
2770 base = 5;
2771 mod = 0;
2772 } else {
2773 base = (bt & 7);
2774 if (base != REG_NUM_EBP && o == 0 &&
2775 seg == NO_SEG && !forw_ref &&
2776 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2777 mod = 0;
2778 else if (IS_MOD_01())
2779 mod = 1;
2780 else
2781 mod = 2;
2782 }
2783
2784 output->sib_present = true;
2785 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2786 output->modrm = GEN_MODRM(mod, rfield, 4);
2787 output->sib = GEN_SIB(scale, index, base);
2788 }
2789 } else { /* it's 16-bit */
2790 int mod, rm;
2791 int16_t o = input->offset;
2792
2793 /* check for 64-bit long mode */
2794 if (addrbits == 64)
2795 goto err;
2796
2797 /* check all registers are BX, BP, SI or DI */
2798 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2799 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2800 goto err;
2801
2802 /* ensure the user didn't specify DWORD/QWORD */
2803 if (input->disp_size == 32 || input->disp_size == 64)
2804 goto err;
2805
2806 if (s != 1 && i != -1)
2807 goto err; /* no can do, in 16-bit EA */
2808 if (b == -1 && i != -1) {
2809 int tmp = b;
2810 b = i;
2811 i = tmp;
2812 } /* swap */
2813 if ((b == R_SI || b == R_DI) && i != -1) {
2814 int tmp = b;
2815 b = i;
2816 i = tmp;
2817 }
2818 /* have BX/BP as base, SI/DI index */
2819 if (b == i)
2820 goto err; /* shouldn't ever happen, in theory */
2821 if (i != -1 && b != -1 &&
2822 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2823 goto err; /* invalid combinations */
2824 if (b == -1) /* pure offset: handled above */
2825 goto err; /* so if it gets to here, panic! */
2826
2827 rm = -1;
2828 if (i != -1)
2829 switch (i * 256 + b) {
2830 case R_SI * 256 + R_BX:
2831 rm = 0;
2832 break;
2833 case R_DI * 256 + R_BX:
2834 rm = 1;
2835 break;
2836 case R_SI * 256 + R_BP:
2837 rm = 2;
2838 break;
2839 case R_DI * 256 + R_BP:
2840 rm = 3;
2841 break;
2842 } else
2843 switch (b) {
2844 case R_SI:
2845 rm = 4;
2846 break;
2847 case R_DI:
2848 rm = 5;
2849 break;
2850 case R_BP:
2851 rm = 6;
2852 break;
2853 case R_BX:
2854 rm = 7;
2855 break;
2856 }
2857 if (rm == -1) /* can't happen, in theory */
2858 goto err; /* so panic if it does */
2859
2860 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2861 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2862 mod = 0;
2863 else if (IS_MOD_01())
2864 mod = 1;
2865 else
2866 mod = 2;
2867
2868 output->sib_present = false; /* no SIB - it's 16-bit */
2869 output->bytes = mod; /* bytes of offset needed */
2870 output->modrm = GEN_MODRM(mod, rfield, rm);
2871 }
2872 }
2873 }
2874
2875 output->size = 1 + output->sib_present + output->bytes;
2876 return output->type;
2877
2878 err:
2879 return output->type = EA_INVALID;
2880 }
2881
2882 static void add_asp(insn *ins, int addrbits)
2883 {
2884 int j, valid;
2885 int defdisp;
2886
2887 valid = (addrbits == 64) ? 64|32 : 32|16;
2888
2889 switch (ins->prefixes[PPS_ASIZE]) {
2890 case P_A16:
2891 valid &= 16;
2892 break;
2893 case P_A32:
2894 valid &= 32;
2895 break;
2896 case P_A64:
2897 valid &= 64;
2898 break;
2899 case P_ASP:
2900 valid &= (addrbits == 32) ? 16 : 32;
2901 break;
2902 default:
2903 break;
2904 }
2905
2906 for (j = 0; j < ins->operands; j++) {
2907 if (is_class(MEMORY, ins->oprs[j].type)) {
2908 opflags_t i, b;
2909
2910 /* Verify as Register */
2911 if (!is_register(ins->oprs[j].indexreg))
2912 i = 0;
2913 else
2914 i = nasm_reg_flags[ins->oprs[j].indexreg];
2915
2916 /* Verify as Register */
2917 if (!is_register(ins->oprs[j].basereg))
2918 b = 0;
2919 else
2920 b = nasm_reg_flags[ins->oprs[j].basereg];
2921
2922 if (ins->oprs[j].scale == 0)
2923 i = 0;
2924
2925 if (!i && !b) {
2926 int ds = ins->oprs[j].disp_size;
2927 if ((addrbits != 64 && ds > 8) ||
2928 (addrbits == 64 && ds == 16))
2929 valid &= ds;
2930 } else {
2931 if (!(REG16 & ~b))
2932 valid &= 16;
2933 if (!(REG32 & ~b))
2934 valid &= 32;
2935 if (!(REG64 & ~b))
2936 valid &= 64;
2937
2938 if (!(REG16 & ~i))
2939 valid &= 16;
2940 if (!(REG32 & ~i))
2941 valid &= 32;
2942 if (!(REG64 & ~i))
2943 valid &= 64;
2944 }
2945 }
2946 }
2947
2948 if (valid & addrbits) {
2949 ins->addr_size = addrbits;
2950 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2951 /* Add an address size prefix */
2952 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2953 ins->addr_size = (addrbits == 32) ? 16 : 32;
2954 } else {
2955 /* Impossible... */
2956 nasm_error(ERR_NONFATAL, "impossible combination of address sizes");
2957 ins->addr_size = addrbits; /* Error recovery */
2958 }
2959
2960 defdisp = ins->addr_size == 16 ? 16 : 32;
2961
2962 for (j = 0; j < ins->operands; j++) {
2963 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2964 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2965 /*
2966 * mem_offs sizes must match the address size; if not,
2967 * strip the MEM_OFFS bit and match only EA instructions
2968 */
2969 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2970 }
2971 }
2972 }
Adding externdefs, 2. version.