| blob | bd7d758c923ef5bfd53315ffc1ce3a844e08f146 |
1 \r
2 Intel 8086 Family Architecture. . . . . . . . . . . . . . . . . . . . . 3\r
3 \r
4 Instruction Clock Cycle Calculation . . . . . . . . . . . . . . . . . . 3\r
5 \r
6 8088/8086 Effective Address (EA) Calculation . . . . . . . . . . . . . 3\r
7 \r
8 Task State Calculation. . . . . . . . . . . . . . . . . . . . . . . . . 4\r
9 \r
10 FLAGS - Intel 8086 Family Flags Register. . . . . . . . . . . . . . . . 4\r
11 \r
12 MSW - Machine Status Word (286+ only) . . . . . . . . . . . . . . . . . 5\r
13 \r
14 8086/80186/80286/80386/80486 Instruction Set. . . . . . . . . . . . . . 6\r
15 AAA - Ascii Adjust for Addition. . . . . . . . . . . . . . . . . . 6\r
16 AAD - Ascii Adjust for Division. . . . . . . . . . . . . . . . . . 6\r
17 AAM - Ascii Adjust for Multiplication. . . . . . . . . . . . . . . 6\r
18 AAS - Ascii Adjust for Subtraction . . . . . . . . . . . . . . . . 6\r
19 ADC - Add With Carry . . . . . . . . . . . . . . . . . . . . . . . 7\r
20 ADD - Arithmetic Addition. . . . . . . . . . . . . . . . . . . . . 7\r
21 AND - Logical And. . . . . . . . . . . . . . . . . . . . . . . . . 7\r
22 ARPL - Adjusted Requested Privilege Level of Selector (286+ PM). . 7\r
23 BOUND - Array Index Bound Check (80188+) . . . . . . . . . . . . . 8\r
24 BSF - Bit Scan Forward (386+). . . . . . . . . . . . . . . . . . . 8\r
25 BSR - Bit Scan Reverse (386+) . . . . . . . . . . . . . . . . . . 8\r
26 BSWAP - Byte Swap (486+) . . . . . . . . . . . . . . . . . . 8\r
27 BT - Bit Test (386+) . . . . . . . . . . . . . . . . . . 9\r
28 BTC - Bit Test with Compliment (386+). . . . . . . . . . . . . . . 9\r
29 BTR - Bit Test with Reset (386+) . . . . . . . . . . . . . . . . . 9\r
30 BTS - Bit Test and Set (386+) . . . . . . . . . . . . . . . . . . 9\r
31 CALL - Procedure Call. . . . . . . . . . . . . . . . . . . . . . . 10\r
32 CBW - Convert Byte to Word . . . . . . . . . . . . . . . . . . . . 10\r
33 CDQ - Convert Double to Quad (386+). . . . . . . . . . . . . . . . 10\r
34 CLC - Clear Carry. . . . . . . . . . . . . . . . . . . . . . . . . 11\r
35 CLD - Clear Direction Flag . . . . . . . . . . . . . . . . . . . . 11\r
36 CLI - Clear Interrupt Flag (disable) . . . . . . . . . . . . . . . 11\r
37 CLTS - Clear Task Switched Flag (286+ privileged). . . . . . . . . 11\r
38 CMC - Complement Carry Flag. . . . . . . . . . . . . . . . . . . . 11\r
39 CMP - Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . 12\r
40 CMPS - Compare String (Byte, Word or Doubleword) . . . . . . . . . 12\r
41 CMPXCHG - Compare and Exchange . . . . . . . . . . . . . . . . . . 12\r
42 CWD - Convert Word to Doubleword . . . . . . . . . . . . . . . . . 12\r
43 CWDE - Convert Word to Extended Doubleword (386+). . . . . . . . . 13\r
44 DAA - Decimal Adjust for Addition. . . . . . . . . . . . . . . . . 13\r
45 DAS - Decimal Adjust for Subtraction . . . . . . . . . . . . . . . 13\r
46 DEC - Decrement. . . . . . . . . . . . . . . . . . . . . . . . . . 13\r
47 DIV - Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . 13\r
48 ENTER - Make Stack Frame (80188+) . . . . . . . . . . . . . . . . 14\r
49 ESC - Escape . . . . . . . . . . . . . . . . . . . . . . . . . . . 14\r
50 HLT - Halt CPU . . . . . . . . . . . . . . . . . . . . . . . . . . 14\r
51 IDIV - Signed Integer Division . . . . . . . . . . . . . . . . . . 14\r
52 IMUL - Signed Multiply . . . . . . . . . . . . . . . . . . . . . . 15\r
53 IN - Input Byte or Word From Port. . . . . . . . . . . . . . . . . 15\r
54 INC - Increment. . . . . . . . . . . . . . . . . . . . . . . . . . 16\r
55 INS - Input String from Port (80188+) . . . . . . . . . . . . . . 16\r
56 INT - Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . 16\r
57 INTO - Interrupt on Overflow . . . . . . . . . . . . . . . . . . . 17\r
58 INVD - Invalidate Cache (486+). . . . . . . . . . . . . . . . . . 17\r
59 INVLPG - Invalidate Translation Look-Aside Buffer Entry (486+) . . 17\r
60 IRET/IRETD - Interrupt Return. . . . . . . . . . . . . . . . . . . 17\r
61 Jxx - Jump Instructions Table. . . . . . . . . . . . . . . . . . . 18\r
62 JCXZ/JECXZ - Jump if Register (E)CX is Zero. . . . . . . . . . . . 18\r
63 JMP - Unconditional Jump . . . . . . . . . . . . . . . . . . . . . 19\r
64 LAHF - Load Register AH From Flags . . . . . . . . . . . . . . . . 19\r
65 LAR - Load Access Rights (286+ protected). . . . . . . . . . . . . 19\r
66 LDS - Load Pointer Using DS. . . . . . . . . . . . . . . . . . . . 20\r
67 LEA - Load Effective Address . . . . . . . . . . . . . . . . . . . 20\r
68 LEAVE - Restore Stack for Procedure Exit (80188+). . . . . . . . . 20\r
69 LES - Load Pointer Using ES. . . . . . . . . . . . . . . . . . . . 20\r
70 LFS - Load Pointer Using FS (386+) . . . . . . . . . . . . . . . . 21\r
71 LGDT - Load Global Descriptor Table (286+ privileged). . . . . . . 21\r
72 LIDT - Load Interrupt Descriptor Table (286+ privileged) . . . . . 21\r
73 LGS - Load Pointer Using GS (386+) . . . . . . . . . . . . . . . . 21\r
74 LLDT - Load Local Descriptor Table (286+ privileged) . . . . . . . 22\r
75 LMSW - Load Machine Status Word (286+ privileged). . . . . . . . . 22\r
76 LOCK - Lock Bus. . . . . . . . . . . . . . . . . . . . . . . . . . 22\r
77 LODS - Load String (Byte, Word or Double). . . . . . . . . . . . . 22\r
78 LOOP - Decrement CX and Loop if CX Not Zero. . . . . . . . . . . . 23\r
79 LOOPE/LOOPZ - Loop While Equal / Loop While Zero . . . . . . . . . 23\r
80 LOOPNZ/LOOPNE - Loop While Not Zero / Loop While Not Equal . . . . 23\r
81 LSL - Load Segment Limit (286+ protected). . . . . . . . . . . . . 23\r
82 LSS - Load Pointer Using SS (386+) . . . . . . . . . . . . . . . . 24\r
83 LTR - Load Task Register (286+ privileged) . . . . . . . . . . . . 24\r
84 MOV - Move Byte or Word. . . . . . . . . . . . . . . . . . . . . . 24\r
85 MOVS - Move String (Byte or Word). . . . . . . . . . . . . . . . . 25\r
86 MOVSX - Move with Sign Extend (386+) . . . . . . . . . . . . . . . 25\r
87 MOVZX - Move with Zero Extend (386+) . . . . . . . . . . . . . . . 25\r
88 MUL - Unsigned Multiply. . . . . . . . . . . . . . . . . . . . . . 25\r
89 NEG - Two's Complement Negation. . . . . . . . . . . . . . . . . . 26\r
90 NOP - No Operation (90h) . . . . . . . . . . . . . . . . . . . . . 26\r
91 NOT - One's Compliment Negation (Logical NOT). . . . . . . . . . . 26\r
92 OR - Inclusive Logical OR. . . . . . . . . . . . . . . . . . . . . 26\r
93 OUT - Output Data to Port. . . . . . . . . . . . . . . . . . . . . 27\r
94 OUTS - Output String to Port (80188+) . . . . . . . . . . . . . . 27\r
95 POP - Pop Word off Stack . . . . . . . . . . . . . . . . . . . . . 27\r
96 POPA/POPAD - Pop All Registers onto Stack (80188+). . . . . . . . 28\r
97 POPF/POPFD - Pop Flags off Stack . . . . . . . . . . . . . . . . . 28\r
98 PUSH - Push Word onto Stack. . . . . . . . . . . . . . . . . . . . 28\r
99 PUSHA/PUSHAD - Push All Registers onto Stack (80188+) . . . . . . 28\r
100 PUSHF/PUSHFD - Push Flags onto Stack . . . . . . . . . . . . . . . 29\r
101 RCL - Rotate Through Carry Left. . . . . . . . . . . . . . . . . . 29\r
102 RCR - Rotate Through Carry Right . . . . . . . . . . . . . . . . . 29\r
103 REP - Repeat String Operation. . . . . . . . . . . . . . . . . . . 30\r
104 REPE/REPZ - Repeat Equal / Repeat Zero . . . . . . . . . . . . . . 30\r
105 REPNE/REPNZ - Repeat Not Equal / Repeat Not Zero . . . . . . . . . 30\r
106 RET/RETF - Return From Procedure . . . . . . . . . . . . . . . . . 31\r
107 ROL - Rotate Left. . . . . . . . . . . . . . . . . . . . . . . . . 31\r
108 ROR - Rotate Right . . . . . . . . . . . . . . . . . . . . . . . . 31\r
109 SAHF - Store AH Register into FLAGS. . . . . . . . . . . . . . . . 32\r
110 SAL/SHL - Shift Arithmetic Left / Shift Logical Left . . . . . . . 32\r
111 SAR - Shift Arithmetic Right . . . . . . . . . . . . . . . . . . . 32\r
112 SBB - Subtract with Borrow/Carry . . . . . . . . . . . . . . . . . 33\r
113 SCAS - Scan String (Byte, Word or Doubleword) . . . . . . . . . . 33\r
114 SETAE/SETNB - Set if Above or Equal / Set if Not Below (386+). . . 33\r
115 SETB/SETNAE - Set if Below / Set if Not Above or Equal (386+). . . 33\r
116 SETBE/SETNA - Set if Below or Equal / Set if Not Above (386+). . . 34\r
117 SETE/SETZ - Set if Equal / Set if Zero (386+). . . . . . . . . . . 34\r
118 SETNE/SETNZ - Set if Not Equal / Set if Not Zero (386+). . . . . . 34\r
119 SETL/SETNGE - Set if Less / Set if Not Greater or Equal (386+) . . 34\r
120 SETGE/SETNL - Set if Greater or Equal / Set if Not Less (386+) . . 35\r
121 SETLE/SETNG - Set if Less or Equal / Set if Not greater or Equal (386+) 35\r
122 SETG/SETNLE - Set if Greater / Set if Not Less or Equal (386+) . . 35\r
123 SETS - Set if Signed (386+). . . . . . . . . . . . . . . . . . . . 35\r
124 SETNS - Set if Not Signed (386+) . . . . . . . . . . . . . . . . . 36\r
125 SETC - Set if Carry (386+) . . . . . . . . . . . . . . . . . . . . 36\r
126 SETNC - Set if Not Carry (386+). . . . . . . . . . . . . . . . . . 36\r
127 SETO - Set if Overflow (386+). . . . . . . . . . . . . . . . . . . 36\r
128 SETNO - Set if Not Overflow (386+) . . . . . . . . . . . . . . . . 36\r
129 SETP/SETPE - Set if Parity / Set if Parity Even (386+). . . . . . 37\r
130 SETNP/SETPO - Set if No Parity / Set if Parity Odd (386+). . . . . 37\r
131 SGDT - Store Global Descriptor Table (286+ privileged) . . . . . . 37\r
132 SIDT - Store Interrupt Descriptor Table (286+ privileged). . . . . 37\r
133 SHL - Shift Logical Left . . . . . . . . . . . . . . . . . . . . . 37\r
134 SHR - Shift Logical Right. . . . . . . . . . . . . . . . . . . . . 38\r
135 SHLD/SHRD - Double Precision Shift (386+). . . . . . . . . . . . . 38\r
136 SLDT - Store Local Descriptor Table (286+ privileged). . . . . . . 38\r
137 SMSW - Store Machine Status Word (286+ privileged) . . . . . . . . 38\r
138 STC - Set Carry. . . . . . . . . . . . . . . . . . . . . . . . . . 39\r
139 STD - Set Direction Flag . . . . . . . . . . . . . . . . . . . . . 39\r
140 STI - Set Interrupt Flag (Enable Interrupts). . . . . . . . . . . 39\r
141 STOS - Store String (Byte, Word or Doubleword). . . . . . . . . . 39\r
142 STR - Store Task Register (286+ privileged). . . . . . . . . . . . 39\r
143 SUB - Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . 40\r
144 TEST - Test For Bit Pattern. . . . . . . . . . . . . . . . . . . . 40\r
145 VERR - Verify Read (286+ protected). . . . . . . . . . . . . . . . 40\r
146 VERW - Verify Write (286+ protected) . . . . . . . . . . . . . . . 40\r
147 WAIT/FWAIT - Event Wait. . . . . . . . . . . . . . . . . . . . . . 41\r
148 WBINVD - Write-Back and Invalidate Cache (486+). . . . . . . . . . 41\r
149 XCHG - Exchange. . . . . . . . . . . . . . . . . . . . . . . . . . 41\r
150 XLAT/XLATB - Translate . . . . . . . . . . . . . . . . . . . . . . 41\r
151 XOR - Exclusive OR . . . . . . . . . . . . . . . . . . . . . . . . 42\r
153 Intel 8086 Family Architecture\r
154 \r
155 General Purpose Registers Segment Registers\r
156 \r
157 AH/AL AX (EAX) Accumulator CS Code Segment\r
158 BH/BL BX (EBX) Base DS Data Segment\r
159 CH/CL CX (ECX) Counter SS Stack Segment\r
160 DH/DL DX (EDX) Data ES Extra Segment\r
161 (FS) 386 and newer\r
162 (Exx) indicates 386+ 32 bit register (GS) 386 and newer\r
163 \r
164 \r
165 Pointer Registers Stack Registers\r
166 \r
167 SI (ESI) Source Index SP (ESP) Stack Pointer\r
168 DI (EDI) Destination Index BP (EBP) Base Pointer\r
169 IP Instruction Pointer\r
170 \r
171 Status Registers\r
172 \r
173 FLAGS Status Flags (see FLAGS)\r
174 \r
175 Special Registers (386+ only)\r
176 \r
177 CR0 Control Register 0 DR0 Debug Register 0\r
178 CR2 Control Register 2 DR1 Debug Register 1\r
179 CR3 Control Register 3 DR2 Debug Register 2\r
180 DR3 Debug Register 3\r
181 TR4 Test Register 4 DR6 Debug Register 6\r
182 TR5 Test Register 5 DR7 Debug Register 7\r
183 TR6 Test Register 6\r
184 TR7 Test Register 7\r
185 \r
186 Register Default Segment Valid Overrides\r
187 \r
188 BP SS DS, ES, CS\r
189 SI or DI DS ES, SS, CS\r
190 DI strings ES None\r
191 SI strings DS ES, SS, CS\r
192 \r
193 \r
194 - see CPU DETECTING Instruction Timing\r
195 \r
196 Instruction Clock Cycle Calculation\r
197 \r
198 \r
199 Some instructions require additional clock cycles due to a "Next\r
200 Instruction Component" identified by a "+m" in the instruction\r
201 clock cycle listings. This is due to the prefetch queue being\r
202 purge on a control transfers. Below is the general rule for\r
203 calculating "m":\r
204 \r
205 \r
206 88/86 not applicable\r
207 286 "m" is the number of bytes in the next instruction\r
208 386 "m" is the number of components in the next instruction\r
209 (the instruction coding (each byte), plus the data and\r
210 the displacement are all considered components)\r
211 \r
212 \r
213 8088/8086 Effective Address (EA) Calculation\r
214 \r
215 Description Clock Cycles\r
216 \r
217 Displacement 6\r
218 Base or Index (BX,BP,SI,DI) 5\r
219 Displacement+(Base or Index) 9\r
220 Base+Index (BP+DI,BX+SI) 7\r
221 Base+Index (BP+SI,BX+DI) 8\r
222 Base+Index+Displacement (BP+DI,BX+SI) 11\r
223 Base+Index+Displacement (BP+SI+disp,BX+DI+disp) 12\r
224 \r
225 \r
226 - add 4 cycles for word operands at odd addresses\r
227 - add 2 cycles for segment override\r
228 - 80188/80186 timings differ from those of the 8088/8086/80286\r
230 \r
231 "TS" is defined as switching from VM/486 or 80286 TSS to one of\r
232 the following:\r
233 \r
234 ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿\r
235 ³ New Task ³\r
236 ÃÄÄÄÄÄÄÄÂÄÄÄÄÄÄÄÂÄÄÄÄÄÄÄÂÄÄÄÄÄÄÄÂÄÄÄÄÄÄÄ´\r
237 ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ´486 TSS³486 TSS³386 TSS³386 TSS³286 TSS³\r
238 ³ Old Task ³ (VM=0)³ (VM=1)³ (VM=0)³ (VM=1)³ ³\r
239 ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄ´\r
240 386 TSS (VM=0) ³ ³ ³ 309 ³ 226 ³ 282 ³\r
241 ÃÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄ´\r
242 386 TSS (VM=1) ³ ³ ³ 314 ³ 231 ³ 287 ³\r
243 ÃÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄ´\r
244 386 CPU/286 TSS ³ ³ ³ 307 ³ 224 ³ 280 ³\r
245 ÃÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄÅÄÄÄÄÄÄÄ´\r
246 486 CPU/286 TSS ³ 199 ³ 177 ³ ³ ³ 180 ³\r
247 ÀÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÙ\r
248 \r
249 \r
250 Miscellaneous\r
251 \r
252 - all timings are for best case and do not take into account wait\r
253 states, instruction alignment, the state of the prefetch queue,\r
254 DMA refresh cycles, cache hits/misses or exception processing.\r
255 - to convert clocks to nanoseconds divide one microsecond by the\r
256 processor speed in MegaHertz:\r
257 \r
258 (1000MHz/(n MHz)) = X nanoseconds\r
259 \r
260 - see 8086 Architecture\r
261 \r
262 \r
263 FLAGS - Intel 8086 Family Flags Register\r
264 \r
265 ³11³10³F³E³D³C³B³A³9³8³7³6³5³4³3³2³1³0³\r
266 ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ÀÄÄÄ CF Carry Flag\r
267 ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ÀÄÄÄ 1\r
268 ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ÀÄÄÄ PF Parity Flag\r
269 ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ÀÄÄÄ 0\r
270 ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ÀÄÄÄ AF Auxiliary Flag\r
271 ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ÀÄÄÄ 0\r
272 ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ÀÄÄÄ ZF Zero Flag\r
273 ³ ³ ³ ³ ³ ³ ³ ³ ³ ³ ÀÄÄÄ SF Sign Flag\r
274 ³ ³ ³ ³ ³ ³ ³ ³ ³ ÀÄÄÄ TF Trap Flag (Single Step)\r
275 ³ ³ ³ ³ ³ ³ ³ ³ ÀÄÄÄ IF Interrupt Flag\r
276 ³ ³ ³ ³ ³ ³ ³ ÀÄÄÄ DF Direction Flag\r
277 ³ ³ ³ ³ ³ ³ ÀÄÄÄ OF Overflow flag\r
278 ³ ³ ³ ³ ÀÄÁÄÄÄ IOPL I/O Privilege Level (286+ only)\r
279 ³ ³ ³ ÀÄÄÄÄÄ NT Nested Task Flag (286+ only)\r
280 ³ ³ ÀÄÄÄÄÄ 0\r
281 ³ ÀÄÄÄÄÄ RF Resume Flag (386+ only)\r
282 ÀÄÄÄÄÄÄ VM Virtual Mode Flag (386+ only)\r
283 \r
284 - see PUSHF POPF STI CLI STD CLD\r
286 \r
287 \r
288 ³31³30-5³4³3³2³1³0³ Machine Status Word\r
289 ³ ³ ³ ³ ³ ³ ÀÄÄÄÄ Protection Enable (PE)\r
290 ³ ³ ³ ³ ³ ÀÄÄÄÄÄ Math Present (MP)\r
291 ³ ³ ³ ³ ÀÄÄÄÄÄÄ Emulation (EM)\r
292 ³ ³ ³ ÀÄÄÄÄÄÄÄ Task Switched (TS)\r
293 ³ ³ ÀÄÄÄÄÄÄÄÄ Extension Type (ET)\r
294 ³ ÀÄÄÄÄÄÄÄÄÄÄ Reserved\r
295 ÀÄÄÄÄÄÄÄÄÄÄÄÄÄ Paging (PG)\r
296 \r
297 \r
298 Bit 0 PE Protection Enable, switches processor between\r
299 protected and real mode\r
300 Bit 1 MP Math Present, controls function of the WAIT\r
301 instruction\r
302 Bit 2 EM Emulation, indicates whether coprocessor functions\r
303 are to be emulated\r
304 Bit 3 TS Task Switched, set and interrogated by coprocessor\r
305 on task switches and when interpretting coprocessor\r
306 instructions\r
307 Bit 4 ET Extension Type, indicates type of coprocessor in\r
308 system\r
309 Bits 5-30 Reserved\r
310 bit 31 PG Paging, indicates whether the processor uses page\r
311 tables to translate linear addresses to physical\r
312 addresses\r
313 \r
314 - see SMSW LMSW\r
316 \r
317 AAA - Ascii Adjust for Addition\r
318 \r
319 Usage: AAA\r
320 Modifies flags: AF CF (OF,PF,SF,ZF undefined)\r
321 \r
322 Changes contents of AL to valid unpacked decimal. The high order\r
323 nibble is zeroed.\r
324 \r
325 Clocks Size\r
326 Operands 808x 286 386 486 Bytes\r
327 \r
328 none 8 3 4 3 1\r
329 \r
330 \r
331 AAD - Ascii Adjust for Division\r
332 \r
333 Usage: AAD\r
334 Modifies flags: SF ZF PF (AF,CF,OF undefined)\r
335 \r
336 Used before dividing unpacked decimal numbers. Multiplies AH by\r
337 10 and the adds result into AL. Sets AH to zero. This instruction\r
338 is also known to have an undocumented behavior.\r
339 \r
340 AL := 10*AH+AL\r
341 AH := 0\r
342 \r
343 Clocks Size\r
344 Operands 808x 286 386 486 Bytes\r
345 \r
346 none 60 14 19 14 2\r
347 \r
348 \r
349 AAM - Ascii Adjust for Multiplication\r
350 \r
351 \r
352 Usage: AAM\r
353 Modifies flags: PF SF ZF (AF,CF,OF undefined)\r
354 \r
355 AH := AL / 10\r
356 AL := AL mod 10\r
357 \r
358 Used after multiplication of two unpacked decimal numbers, this\r
359 instruction adjusts an unpacked decimal number. The high order\r
360 nibble of each byte must be zeroed before using this instruction.\r
361 This instruction is also known to have an undocumented behavior.\r
362 \r
363 Clocks Size\r
364 Operands 808x 286 386 486 Bytes\r
365 \r
366 none 83 16 17 15 2\r
367 \r
368 \r
369 AAS - Ascii Adjust for Subtraction\r
370 \r
371 Usage: AAS\r
372 Modifies flags: AF CF (OF,PF,SF,ZF undefined)\r
373 \r
374 Corrects result of a previous unpacked decimal subtraction in AL.\r
375 High order nibble is zeroed.\r
376 \r
377 Clocks Size\r
378 Operands 808x 286 386 486 Bytes\r
379 \r
380 none 8 3 4 3 1\r
382 \r
383 Usage: ADC dest,src\r
384 Modifies flags: AF CF OF SF PF ZF\r
385 \r
386 Sums two binary operands placing the result in the destination.\r
387 If CF is set, a 1 is added to the destination.\r
388 \r
389 Clocks Size\r
390 Operands 808x 286 386 486 Bytes\r
391 \r
392 reg,reg 3 2 2 1 2\r
393 mem,reg 16+EA 7 7 3 2-4 (W88=24+EA)\r
394 reg,mem 9+EA 7 6 2 2-4 (W88=13+EA)\r
395 reg,immed 4 3 2 1 3-4\r
396 mem,immed 17+EA 7 7 3 3-6 (W88=23+EA)\r
397 accum,immed 4 3 2 1 2-3\r
398 \r
399 \r
400 ADD - Arithmetic Addition\r
401 \r
402 Usage: ADD dest,src\r
403 Modifies flags: AF CF OF PF SF ZF\r
404 \r
405 Adds "src" to "dest" and replacing the original contents of "dest".\r
406 Both operands are binary.\r
407 \r
408 Clocks Size\r
409 Operands 808x 286 386 486 Bytes\r
410 \r
411 reg,reg 3 2 2 1 2\r
412 mem,reg 16+EA 7 7 3 2-4 (W88=24+EA)\r
413 reg,mem 9+EA 7 6 2 2-4 (W88=13+EA)\r
414 reg,immed 4 3 2 1 3-4\r
415 mem,immed 17+EA 7 7 3 3-6 (W88=23+EA)\r
416 accum,immed 4 3 2 1 2-3\r
417 \r
418 \r
419 AND - Logical And\r
420 \r
421 Usage: AND dest,src\r
422 Modifies flags: CF OF PF SF ZF (AF undefined)\r
423 \r
424 Performs a logical AND of the two operands replacing the destination\r
425 with the result.\r
426 \r
427 Clocks Size\r
428 Operands 808x 286 386 486 Bytes\r
429 \r
430 reg,reg 3 2 2 1 2\r
431 mem,reg 16+EA 7 7 3 2-4 (W88=24+EA)\r
432 reg,mem 9+EA 7 6 1 2-4 (W88=13+EA)\r
433 reg,immed 4 3 2 1 3-4\r
434 mem,immed 17+EA 7 7 3 3-6 (W88=23+EA)\r
435 accum,immed 4 3 2 1 2-3\r
436 \r
437 \r
438 ARPL - Adjusted Requested Privilege Level of Selector (286+ PM)\r
439 \r
440 Usage: ARPL dest,src\r
441 (286+ protected mode)\r
442 Modifies flags: ZF\r
443 \r
444 Compares the RPL bits of "dest" against "src". If the RPL bits\r
445 of "dest" are less than "src", the destination RPL bits are set\r
446 equal to the source RPL bits and the Zero Flag is set. Otherwise\r
447 the Zero Flag is cleared.\r
448 \r
449 Clocks Size\r
450 Operands 808x 286 386 486 Bytes\r
451 \r
452 reg,reg - 10 20 9 2\r
453 mem,reg - 11 21 9 4\r
455 \r
456 Usage: BOUND src,limit\r
457 Modifies flags: None\r
458 \r
459 Array index in source register is checked against upper and lower\r
460 bounds in memory source. The first word located at "limit" is\r
461 the lower boundary and the word at "limit+2" is the upper array bound.\r
462 Interrupt 5 occurs if the source value is less than or higher than\r
463 the source.\r
464 \r
465 Clocks Size\r
466 Operands 808x 286 386 486 Bytes\r
467 \r
468 reg16,mem32 - nj=13 nj=10 7 2\r
469 reg32,mem64 - nj=13 nj=10 7 2\r
470 \r
471 - nj = no jump taken\r
472 \r
473 \r
474 BSF - Bit Scan Forward (386+)\r
475 \r
476 Usage: BSF dest,src\r
477 Modifies flags: ZF\r
478 \r
479 Scans source operand for first bit set. Sets ZF if a bit is found\r
480 set and loads the destination with an index to first set bit. Clears\r
481 ZF is no bits are found set. BSF scans forward across bit pattern\r
482 (0-n) while BSR scans in reverse (n-0).\r
483 \r
484 Clocks Size\r
485 Operands 808x 286 386 486 Bytes\r
486 \r
487 reg,reg - - 10+3n 6-42 3\r
488 reg,mem - - 10+3n 7-43 3-7\r
489 reg32,reg32 - - 10+3n 6-42 3-7\r
490 reg32,mem32 - - 10+3n 7-43 3-7\r
491 \r
492 \r
493 BSR - Bit Scan Reverse (386+)\r
494 \r
495 Usage: BSR dest,src\r
496 Modifies flags: ZF\r
497 \r
498 Scans source operand for first bit set. Sets ZF if a bit is found\r
499 set and loads the destination with an index to first set bit. Clears\r
500 ZF is no bits are found set. BSF scans forward across bit pattern\r
501 (0-n) while BSR scans in reverse (n-0).\r
502 \r
503 Clocks Size\r
504 Operands 808x 286 386 486 Bytes\r
505 \r
506 reg,reg - - 10+3n 6-103 3\r
507 reg,mem - - 10+3n 7-104 3-7\r
508 reg32,reg32 - - 10+3n 6-103 3-7\r
509 reg32,mem32 - - 10+3n 7-104 3-7\r
510 \r
511 \r
512 BSWAP - Byte Swap (486+)\r
513 \r
514 Usage: BSWAP reg32\r
515 Modifies flags: none\r
516 \r
517 Changes the byte order of a 32 bit register from big endian to\r
518 little endian or vice versa. Result left in destination register\r
519 is undefined if the operand is a 16 bit register.\r
520 \r
521 Clocks Size\r
522 Operands 808x 286 386 486 Bytes\r
523 \r
524 reg32 - - - 1 2\r
526 \r
527 Usage: BT dest,src\r
528 Modifies flags: CF\r
529 \r
530 The destination bit indexed by the source value is copied into the\r
531 Carry Flag.\r
532 \r
533 Clocks Size\r
534 Operands 808x 286 386 486 Bytes\r
535 \r
536 reg16,immed8 - - 3 3 4-8\r
537 mem16,immed8 - - 6 6 4-8\r
538 reg16,reg16 - - 3 3 3-7\r
539 mem16,reg16 - - 12 12 3-7\r
540 \r
541 \r
542 BTC - Bit Test with Compliment (386+)\r
543 \r
544 Usage: BTC dest,src\r
545 Modifies flags: CF\r
546 \r
547 The destination bit indexed by the source value is copied into the\r
548 Carry Flag after being complimented (inverted).\r
549 \r
550 Clocks Size\r
551 Operands 808x 286 386 486 Bytes\r
552 \r
553 reg16,immed8 - - 6 6 4-8\r
554 mem16,immed8 - - 8 8 4-8\r
555 reg16,reg16 - - 6 6 3-7\r
556 mem16,reg16 - - 13 13 3-7\r
557 \r
558 \r
559 BTR - Bit Test with Reset (386+)\r
560 \r
561 Usage: BTR dest,src\r
562 Modifies flags: CF\r
563 \r
564 The destination bit indexed by the source value is copied into the\r
565 Carry Flag and then cleared in the destination.\r
566 \r
567 Clocks Size\r
568 Operands 808x 286 386 486 Bytes\r
569 \r
570 reg16,immed8 - - 6 6 4-8\r
571 mem16,immed8 - - 8 8 4-8\r
572 reg16,reg16 - - 6 6 3-7\r
573 mem16,reg16 - - 13 13 3-7\r
574 \r
575 \r
576 BTS - Bit Test and Set (386+)\r
577 \r
578 Usage: BTS dest,src\r
579 Modifies flags: CF\r
580 \r
581 The destination bit indexed by the source value is copied into the\r
582 Carry Flag and then set in the destination.\r
583 \r
584 Clocks Size\r
585 Operands 808x 286 386 486 Bytes\r
586 \r
587 reg16,immed8 - - 6 6 4-8\r
588 mem16,immed8 - - 8 8 4-8\r
589 reg16,reg16 - - 6 6 3-7\r
590 mem16,reg16 - - 13 13 3-7\r
592 \r
593 Usage: CALL destination\r
594 Modifies flags: None\r
595 \r
596 Pushes Instruction Pointer (and Code Segment for far calls) onto\r
597 stack and loads Instruction Pointer with the address of proc-name.\r
598 Code continues with execution at CS:IP.\r
599 \r
600 Clocks\r
601 Operands 808x 286 386 486\r
602 \r
603 rel16 (near, IP relative) 19 7 7+m 3\r
604 rel32 (near, IP relative) - - 7+m 3\r
605 \r
606 reg16 (near, register indirect) 16 7 7+m 5\r
607 reg32 (near, register indirect) - - 7+m 5\r
608 \r
609 mem16 (near, memory indirect) - 21+EA 11 10+m 5\r
610 mem32 (near, memory indirect) - - 10+m 5\r
611 \r
612 ptr16:16 (far, full ptr supplied) 28 13 17+m 18\r
613 ptr16:32 (far, full ptr supplied) - - 17+m 18\r
614 ptr16:16 (far, ptr supplied, prot. mode) - 26 34+m 20\r
615 ptr16:32 (far, ptr supplied, prot. mode) - - 34+m 20\r
616 m16:16 (far, indirect) 37+EA 16 22+m 17\r
617 m16:32 (far, indirect) - - 22+m 17\r
618 m16:16 (far, indirect, prot. mode) - 29 38+m 20\r
619 m16:32 (far, indirect, prot. mode) - - 38+m 20\r
620 \r
621 ptr16:16 (task, via TSS or task gate) - 177 TS 37+TS\r
622 m16:16 (task, via TSS or task gate) - 180/185 5+TS 37+TS\r
623 m16:32 (task) - - TS 37+TS\r
624 m16:32 (task) - - 5+TS 37+TS\r
625 \r
626 ptr16:16 (gate, same privilege) - 41 52+m 35\r
627 ptr16:32 (gate, same privilege) - - 52+m 35\r
628 m16:16 (gate, same privilege) - 44 56+m 35\r
629 m16:32 (gate, same privilege) - - 56+m 35\r
630 \r
631 ptr16:16 (gate, more priv, no parm) - 82 86+m 69\r
632 ptr16:32 (gate, more priv, no parm) - - 86+m 69\r
633 m16:16 (gate, more priv, no parm) - 83 90+m 69\r
634 m16:32 (gate, more priv, no parm) - - 90+m 69\r
635 \r
636 ptr16:16 (gate, more priv, x parms) - 86+4x 94+4x+m 77+4x\r
637 ptr16:32 (gate, more priv, x parms) - - 94+4x+m 77+4x\r
638 m16:16 (gate, more priv, x parms) - 90+4x 98+4x+m 77+4x\r
639 m16:32 (gate, more priv, x parms) - - 98+4x+m 77+4x\r
640 \r
641 \r
642 CBW - Convert Byte to Word\r
643 \r
644 Usage: CBW\r
645 Modifies flags: None\r
646 \r
647 Converts byte in AL to word Value in AX by extending sign of AL\r
648 throughout register AH.\r
649 \r
650 Clocks Size\r
651 Operands 808x 286 386 486 Bytes\r
652 \r
653 none 2 2 3 3 1\r
654 \r
655 \r
656 CDQ - Convert Double to Quad (386+)\r
657 \r
658 Usage: CDQ\r
659 Modifies flags: None\r
660 \r
661 Converts signed DWORD in EAX to a signed quad word in EDX:EAX by\r
662 extending the high order bit of EAX throughout EDX\r
663 \r
664 Clocks Size\r
665 Operands 808x 286 386 486 Bytes\r
666 \r
667 none - - 2 3 1\r
669 \r
670 Usage: CLC\r
671 Modifies flags: CF\r
672 \r
673 Clears the Carry Flag.\r
674 \r
675 Clocks Size\r
676 Operands 808x 286 386 486 Bytes\r
677 \r
678 none 2 2 2 2 1\r
679 \r
680 \r
681 CLD - Clear Direction Flag\r
682 \r
683 Usage: CLD\r
684 Modifies flags: DF\r
685 \r
686 Clears the Direction Flag causing string instructions to increment\r
687 the SI and DI index registers.\r
688 \r
689 Clocks Size\r
690 Operands 808x 286 386 486 Bytes\r
691 \r
692 none 2 2 2 2 1\r
693 \r
694 \r
695 CLI - Clear Interrupt Flag (disable)\r
696 \r
697 Usage: CLI\r
698 Modifies flags: IF\r
699 \r
700 Disables the maskable hardware interrupts by clearing the Interrupt\r
701 flag. NMI's and software interrupts are not inhibited.\r
702 \r
703 Clocks Size\r
704 Operands 808x 286 386 486 Bytes\r
705 \r
706 none 2 2 3 5 1\r
707 \r
708 \r
709 CLTS - Clear Task Switched Flag (286+ privileged)\r
710 \r
711 Usage: CLTS\r
712 Modifies flags: None\r
713 \r
714 Clears the Task Switched Flag in the Machine Status Register. This\r
715 is a privileged operation and is generally used only by operating\r
716 system code.\r
717 \r
718 Clocks Size\r
719 Operands 808x 286 386 486 Bytes\r
720 \r
721 none - 2 5 7 2\r
722 \r
723 \r
724 CMC - Complement Carry Flag\r
725 \r
726 Usage: CMC\r
727 Modifies flags: CF\r
728 \r
729 Toggles (inverts) the Carry Flag\r
730 \r
731 Clocks Size\r
732 Operands 808x 286 386 486 Bytes\r
733 \r
734 none 2 2 2 2 1\r
736 \r
737 Usage: CMP dest,src\r
738 Modifies flags: AF CF OF PF SF ZF\r
739 \r
740 Subtracts source from destination and updates the flags but does\r
741 not save result. Flags can subsequently be checked for conditions.\r
742 \r
743 Clocks Size\r
744 Operands 808x 286 386 486 Bytes\r
745 \r
746 reg,reg 3 2 2 1 2\r
747 mem,reg 9+EA 7 5 2 2-4 (W88=13+EA)\r
748 reg,mem 9+EA 6 6 2 2-4 (W88=13+EA)\r
749 reg,immed 4 3 2 1 3-4\r
750 mem,immed 10+EA 6 5 2 3-6 (W88=14+EA)\r
751 accum,immed 4 3 2 1 2-3\r
752 \r
753 \r
754 CMPS - Compare String (Byte, Word or Doubleword)\r
755 \r
756 Usage: CMPS dest,src\r
757 CMPSB\r
758 CMPSW\r
759 CMPSD (386+)\r
760 Modifies flags: AF CF OF PF SF ZF\r
761 \r
762 Subtracts destination value from source without saving results.\r
763 Updates flags based on the subtraction and the index registers\r
764 (E)SI and (E)DI are incremented or decremented depending on the\r
765 state of the Direction Flag. CMPSB inc/decrements the index\r
766 registers by 1, CMPSW inc/decrements by 2, while CMPSD increments\r
767 or decrements by 4. The REP prefixes can be used to process\r
768 entire data items.\r
769 \r
770 Clocks Size\r
771 Operands 808x 286 386 486 Bytes\r
772 \r
773 dest,src 22 8 10 8 1 (W88=30)\r
774 \r
775 \r
776 CMPXCHG - Compare and Exchange\r
777 \r
778 Usage: CMPXCHG dest,src (486+)\r
779 Modifies flags: AF CF OF PF SF ZF\r
780 \r
781 Compares the accumulator (8-32 bits) with "dest". If equal the\r
782 "dest" is loaded with "src", otherwise the accumulator is loaded\r
783 with "dest".\r
784 \r
785 Clocks Size\r
786 Operands 808x 286 386 486 Bytes\r
787 \r
788 reg,reg - - - 6 2\r
789 mem,reg - - - 7 2\r
790 \r
791 - add 3 clocks if the "mem,reg" comparison fails\r
792 \r
793 \r
794 CWD - Convert Word to Doubleword\r
795 \r
796 Usage: CWD\r
797 Modifies flags: None\r
798 \r
799 Extends sign of word in register AX throughout register DX forming\r
800 a doubleword quantity in DX:AX.\r
801 \r
802 Clocks Size\r
803 Operands 808x 286 386 486 Bytes\r
804 \r
805 none 5 2 2 3 1\r
807 \r
808 Usage: CWDE\r
809 Modifies flags: None\r
810 \r
811 Converts a signed word in AX to a signed doubleword in EAX by\r
812 extending the sign bit of AX throughout EAX.\r
813 \r
814 Clocks Size\r
815 Operands 808x 286 386 486 Bytes\r
816 \r
817 none - - 3 3 1\r
818 \r
819 \r
820 DAA - Decimal Adjust for Addition\r
821 \r
822 Usage: DAA\r
823 Modifies flags: AF CF PF SF ZF (OF undefined)\r
824 \r
825 Corrects result (in AL) of a previous BCD addition operation.\r
826 Contents of AL are changed to a pair of packed decimal digits.\r
827 \r
828 Clocks Size\r
829 Operands 808x 286 386 486 Bytes\r
830 \r
831 none 4 3 4 2 1\r
832 \r
833 \r
834 DAS - Decimal Adjust for Subtraction\r
835 \r
836 Usage: DAS\r
837 Modifies flags: AF CF PF SF ZF (OF undefined)\r
838 \r
839 Corrects result (in AL) of a previous BCD subtraction operation.\r
840 Contents of AL are changed to a pair of packed decimal digits.\r
841 \r
842 Clocks Size\r
843 Operands 808x 286 386 486 Bytes\r
844 \r
845 none 4 3 4 2 1\r
846 \r
847 \r
848 DEC - Decrement\r
849 \r
850 Usage: DEC dest\r
851 Modifies flags: AF OF PF SF ZF\r
852 \r
853 Unsigned binary subtraction of one from the destination.\r
854 \r
855 Clocks Size\r
856 Operands 808x 286 386 486 Bytes\r
857 \r
858 reg8 3 2 2 1 2\r
859 mem 15+EA 7 6 3 2-4\r
860 reg16/32 3 2 2 1 1\r
861 \r
862 \r
863 DIV - Divide\r
864 \r
865 Usage: DIV src\r
866 Modifies flags: (AF,CF,OF,PF,SF,ZF undefined)\r
867 \r
868 Unsigned binary division of accumulator by source. If the source\r
869 divisor is a byte value then AX is divided by "src" and the quotient\r
870 is placed in AL and the remainder in AH. If source operand is a word\r
871 value, then DX:AX is divided by "src" and the quotient is stored in AX\r
872 and the remainder in DX.\r
873 \r
874 Clocks Size\r
875 Operands 808x 286 386 486 Bytes\r
876 \r
877 reg8 80-90 14 14 16 2\r
878 reg16 144-162 22 22 24 2\r
879 reg32 - - 38 40 2\r
880 mem8 (86-96)+EA 17 17 16 2-4\r
881 mem16 (150-168)+EA 25 25 24 2-4 (W88=158-176+EA)\r
882 mem32 - - 41 40 2-4\r
884 \r
885 Usage: ENTER locals,level\r
886 Modifies flags: None\r
887 \r
888 Modifies stack for entry to procedure for high level language.\r
889 Operand "locals" specifies the amount of storage to be allocated\r
890 on the stack. "Level" specifies the nesting level of the routine.\r
891 Paired with the LEAVE instruction, this is an efficient method of\r
892 entry and exit to procedures.\r
893 \r
894 Clocks Size\r
895 Operands 808x 286 386 486 Bytes\r
896 \r
897 immed16,0 - 11 10 14 4\r
898 immed16,1 - 15 12 17 4\r
899 immed16,immed8 - 12+4(n-1) 15+4(n-1) 17+3n 4\r
900 \r
901 \r
902 ESC - Escape\r
903 \r
904 Usage: ESC immed,src\r
905 Modifies flags: None\r
906 \r
907 Provides access to the data bus for other resident processors.\r
908 The CPU treats it as a NOP but places memory operand on bus.\r
909 \r
910 Clocks Size\r
911 Operands 808x 286 386 486 Bytes\r
912 \r
913 immed,reg 2 9-20 ? 2\r
914 immed,mem 2 9-20 ? 2-4\r
915 \r
916 \r
917 HLT - Halt CPU\r
918 \r
919 Usage: HLT\r
920 Modifies flags: None\r
921 \r
922 Halts CPU until RESET line is activated, NMI or maskable interrupt\r
923 received. The CPU becomes dormant but retains the current CS:IP\r
924 for later restart.\r
925 \r
926 Clocks Size\r
927 Operands 808x 286 386 486 Bytes\r
928 \r
929 none 2 2 5 4 1\r
930 \r
931 \r
932 IDIV - Signed Integer Division\r
933 \r
934 Usage: IDIV src\r
935 Modifies flags: (AF,CF,OF,PF,SF,ZF undefined)\r
936 \r
937 Signed binary division of accumulator by source. If source is a\r
938 byte value, AX is divided by "src" and the quotient is stored in\r
939 AL and the remainder in AH. If source is a word value, DX:AX is\r
940 divided by "src", and the quotient is stored in AL and the\r
941 remainder in DX.\r
942 Clocks Size\r
943 Operands 808x 286 386 486 Bytes\r
944 \r
945 reg8 101-112 17 19 19 2\r
946 reg16 165-184 25 27 27 2\r
947 reg32 - - 43 43 2\r
948 mem8 (107-118)+EA 20 22 20 2-4\r
949 mem16 (171-190)+EA 38 30 28 2-4 (W88=175-194)\r
950 mem32 - - 46 44 2-4\r
952 \r
953 Usage: IMUL src\r
954 IMUL src,immed (286+)\r
955 IMUL dest,src,immed8 (286+)\r
956 IMUL dest,src (386+)\r
957 Modifies flags: CF OF (AF,PF,SF,ZF undefined)\r
958 \r
959 Signed multiplication of accumulator by "src" with result placed\r
960 in the accumulator. If the source operand is a byte value, it\r
961 is multiplied by AL and the result stored in AX. If the source\r
962 operand is a word value it is multiplied by AX and the result is\r
963 stored in DX:AX. Other variations of this instruction allow\r
964 specification of source and destination registers as well as a\r
965 third immediate factor.\r
966 \r
967 Clocks Size\r
968 Operands 808x 286 386 486 Bytes\r
969 \r
970 reg8 80-98 13 9-14 13-18 2\r
971 reg16 128-154 21 9-22 13-26 2\r
972 reg32 - - 9-38 12-42 2\r
973 mem8 86-104 16 12-17 13-18 2-4\r
974 mem16 134-160 24 12-25 13-26 2-4\r
975 mem32 - - 12-41 13-42 2-4\r
976 reg16,reg16 - - 9-22 13-26 3-5\r
977 reg32,reg32 - - 9-38 13-42 3-5\r
978 reg16,mem16 - - 12-25 13-26 3-5\r
979 reg32,mem32 - - 12-41 13-42 3-5\r
980 reg16,immed - 21 9-22 13-26 3\r
981 reg32,immed - 21 9-38 13-42 3-6\r
982 reg16,reg16,immed - 2 9-22 13-26 3-6\r
983 reg32,reg32,immed - 21 9-38 13-42 3-6\r
984 reg16,mem16,immed - 24 12-25 13-26 3-6\r
985 reg32,mem32,immed - 24 12-41 13-42 3-6\r
986 \r
987 \r
988 IN - Input Byte or Word From Port\r
989 \r
990 Usage: IN accum,port\r
991 Modifies flags: None\r
992 \r
993 A byte, word or dword is read from "port" and placed in AL, AX or\r
994 EAX respectively. If the port number is in the range of 0-255\r
995 it can be specified as an immediate, otherwise the port number\r
996 must be specified in DX. Valid port ranges on the PC are 0-1024,\r
997 though values through 65535 may be specified and recognized by\r
998 third party vendors and PS/2's.\r
999 \r
1000 Clocks Size\r
1001 Operands 808x 286 386 486 Bytes\r
1002 \r
1003 accum,immed8 10/14 5 12 14 2\r
1004 accum,immed8 (PM) 6/26 8/28/27 2\r
1005 accum,DX 8/12 5 13 14 1\r
1006 accum,DX (PM) 7/27 8/28/27 1\r
1007 \r
1008 - 386+ protected mode timings depend on privilege levels.\r
1009 \r
1010 first number is the timing if: CPL ó IOPL\r
1011 second number is the timing if: CPL > IOPL or in VM 86 mode (386)\r
1012 CPL ò IOPL (486)\r
1013 third number is the timing when: virtual mode on 486 processor\r
1014 - 486 virtual mode always requires 27 cycles\r
1016 \r
1017 Usage: INC dest\r
1018 Modifies flags: AF OF PF SF ZF\r
1019 \r
1020 Adds one to destination unsigned binary operand.\r
1021 \r
1022 Clocks Size\r
1023 Operands 808x 286 386 486 Bytes\r
1024 \r
1025 reg8 3 2 2 1 2\r
1026 reg16 3 2 2 1 1\r
1027 reg32 3 2 2 1 1\r
1028 mem 15+EA 7 6 3 2-4 (W88=23+EA)\r
1029 \r
1030 \r
1031 INS - Input String from Port (80188+)\r
1032 \r
1033 Usage: INS dest,port\r
1034 INSB\r
1035 INSW\r
1036 INSD (386+)\r
1037 Modifies flags: None\r
1038 \r
1039 Loads data from port to the destination ES:(E)DI (even if a\r
1040 destination operand is supplied). (E)DI is adjusted by the size\r
1041 of the operand and increased if the Direction Flag is cleared and\r
1042 decreased if the Direction Flag is set. For INSB, INSW, INSD no\r
1043 operands are allowed and the size is determined by the mnemonic.\r
1044 \r
1045 Clocks Size\r
1046 Operands 808x 286 386 486 Bytes\r
1047 \r
1048 dest,port - 5 15 17 1\r
1049 dest,port (PM) - 5 9/29 10/32/30 1\r
1050 none - 5 15 17 1\r
1051 none (PM) - 5 9/29 10/32/30 1\r
1052 \r
1053 - 386+ protected mode timings depend on privilege levels.\r
1054 \r
1055 first number is the timing if: CPL ó IOPL\r
1056 second number is the timing if: CPL > IOPL\r
1057 third number is the timing if: virtual mode on 486 processor\r
1058 \r
1059 \r
1060 INT - Interrupt\r
1061 \r
1062 Usage: INT num\r
1063 Modifies flags: TF IF\r
1064 \r
1065 Initiates a software interrupt by pushing the flags, clearing the\r
1066 Trap and Interrupt Flags, pushing CS followed by IP and loading\r
1067 CS:IP with the value found in the interrupt vector table. Execution\r
1068 then begins at the location addressed by the new CS:IP\r
1069 \r
1070 Clocks Size\r
1071 Operands 808x 286 386 486 Bytes\r
1072 \r
1073 3 (constant) 52/72 23+m 33 26 2\r
1074 3 (prot. mode, same priv.) - 40+m 59 44 2 \r
1075 3 (prot. mode, more priv.) - 78+m 99 71 2\r
1076 3 (from VM86 to PL 0) - - 119 82 2\r
1077 3 (prot. mode via task gate) - 167+m TS 37+TS 2\r
1078 immed8 51/71 23+m 37 30 1\r
1079 immed8 (prot. mode, same priv.) - 40+m 59 44 1\r
1080 immed8 (prot. mode, more priv.) - 78+m 99 71 1\r
1081 immed8 (from VM86 to PL 0) - - 119 86 1\r
1082 immed8 (prot. mode, via task gate) - 167+m TS 37+TS 1\r
1084 \r
1085 Usage: INTO\r
1086 Modifies flags: IF TF\r
1087 \r
1088 If the Overflow Flag is set this instruction generates an INT 4\r
1089 which causes the code addressed by 0000:0010 to be executed.\r
1090 \r
1091 Clocks Size\r
1092 Operands 808x 286 386 486 Bytes\r
1093 \r
1094 none: jump 53/73 24+m 35 28 1\r
1095 no jump 4 3 3 3\r
1096 (prot. mode, same priv.) - - 59 46 1\r
1097 (prot. mode, more priv.) - - 99 73 1\r
1098 (from VM86 to PL 0) - - 119 84 1\r
1099 (prot. mode, via task gate) - TS 39+TS 1\r
1100 \r
1101 \r
1102 INVD - Invalidate Cache (486+)\r
1103 \r
1104 Usage: INVD\r
1105 Modifies flags: none\r
1106 \r
1107 Flushes CPU internal cache. Issues special function bus cycle\r
1108 which indicates to flush external caches. Data in write-back\r
1109 external caches is lost.\r
1110 \r
1111 Clocks Size\r
1112 Operands 808x 286 386 486 Bytes\r
1113 \r
1114 none - - - 4 2\r
1115 \r
1116 \r
1117 INVLPG - Invalidate Translation Look-Aside Buffer Entry (486+)\r
1118 \r
1119 Usage: INVLPG\r
1120 Modifies flags: none\r
1121 \r
1122 Invalidates a single page table entry in the Translation\r
1123 Look-Aside Buffer. Intel warns that this instruction may be\r
1124 implemented differently on future processors.\r
1125 \r
1126 Clocks Size\r
1127 Operands 808x 286 386 486 Bytes\r
1128 \r
1129 none - - - 12 2\r
1130 \r
1131 - timing is for TLB entry hit only.\r
1132 \r
1133 \r
1134 IRET/IRETD - Interrupt Return\r
1135 \r
1136 Usage: IRET\r
1137 IRETD (386+)\r
1138 Modifies flags: AF CF DF IF PF SF TF ZF\r
1139 \r
1140 Returns control to point of interruption by popping IP, CS\r
1141 and then the Flags from the stack and continues execution at\r
1142 this location. CPU exception interrupts will return to the\r
1143 instruction that cause the exception because the CS:IP placed\r
1144 on the stack during the interrupt is the address of the offending\r
1145 instruction.\r
1146 \r
1147 Clocks Size\r
1148 Operands 808x 286 386 486 Bytes\r
1149 \r
1150 iret 32/44 17+m 22 15 1\r
1151 iret (prot. mode) - 31+m 38 15 1\r
1152 iret (to less privilege) - 55+m 82 36 1\r
1153 iret (different task, NT=1) - 169+m TS TS+32 1\r
1154 iretd - - 22/38 15 1\r
1155 iretd (to less privilege) - - 82 36 1\r
1156 iretd (to VM86 mode) - - 60 15 1\r
1157 iretd (different task, NT=1) - - TS TS+32 1\r
1158 \r
1159 - 386 timings are listed as real-mode/protected-mode\r
1161 \r
1162 Mnemonic Meaning Jump Condition\r
1163 \r
1164 JA Jump if Above CF=0 and ZF=0\r
1165 JAE Jump if Above or Equal CF=0\r
1166 JB Jump if Below CF=1\r
1167 JBE Jump if Below or Equal CF=1 or ZF=1\r
1168 JC Jump if Carry CF=1\r
1169 JCXZ Jump if CX Zero CX=0\r
1170 JE Jump if Equal ZF=1\r
1171 JG Jump if Greater (signed) ZF=0 and SF=OF\r
1172 JGE Jump if Greater or Equal (signed) SF=OF\r
1173 JL Jump if Less (signed) SF != OF\r
1174 JLE Jump if Less or Equal (signed) ZF=1 or SF != OF\r
1175 JMP Unconditional Jump unconditional\r
1176 JNA Jump if Not Above CF=1 or ZF=1\r
1177 JNAE Jump if Not Above or Equal CF=1\r
1178 JNB Jump if Not Below CF=0\r
1179 JNBE Jump if Not Below or Equal CF=0 and ZF=0\r
1180 JNC Jump if Not Carry CF=0\r
1181 JNE Jump if Not Equal ZF=0\r
1182 JNG Jump if Not Greater (signed) ZF=1 or SF != OF\r
1183 JNGE Jump if Not Greater or Equal (signed) SF != OF\r
1184 JNL Jump if Not Less (signed) SF=OF\r
1185 JNLE Jump if Not Less or Equal (signed) ZF=0 and SF=OF\r
1186 JNO Jump if Not Overflow (signed) OF=0\r
1187 JNP Jump if No Parity PF=0\r
1188 JNS Jump if Not Signed (signed) SF=0\r
1189 JNZ Jump if Not Zero ZF=0\r
1190 JO Jump if Overflow (signed) OF=1\r
1191 JP Jump if Parity PF=1\r
1192 JPE Jump if Parity Even PF=1\r
1193 JPO Jump if Parity Odd PF=0\r
1194 JS Jump if Signed (signed) SF=1\r
1195 JZ Jump if Zero ZF=1\r
1196 \r
1197 Clocks Size\r
1198 Operands 808x 286 386 486 Bytes\r
1199 \r
1200 Jx: jump 16 7+m 7+m 3 2\r
1201 no jump 4 3 3 1\r
1202 Jx near-label - - 7+m 3 4\r
1203 no jump - - 3 1\r
1204 \r
1205 - It's a good programming practice to organize code so the\r
1206 expected case is executed without a jump since the actual\r
1207 jump takes longer to execute than falling through the test.\r
1208 - see JCXZ and JMP for their respective timings\r
1209 \r
1210 \r
1211 JCXZ/JECXZ - Jump if Register (E)CX is Zero\r
1212 \r
1213 Usage: JCXZ label\r
1214 JECXZ label (386+)\r
1215 Modifies flags: None\r
1216 \r
1217 Causes execution to branch to "label" if register CX is zero. Uses\r
1218 unsigned comparision.\r
1219 \r
1220 Clocks Size\r
1221 Operands 808x 286 386 486 Bytes\r
1222 \r
1223 label: jump 18 8+m 9+m 8 2\r
1224 no jump 6 4 5 5\r
1226 \r
1227 Usage: JMP target\r
1228 Modifies flags: None\r
1229 \r
1230 Unconditionally transfers control to "label". Jumps by default\r
1231 are within -32768 to 32767 bytes from the instruction following\r
1232 the jump. NEAR and SHORT jumps cause the IP to be updated while FAR\r
1233 jumps cause CS and IP to be updated.\r
1234 \r
1235 Clocks\r
1236 Operands 808x 286 386 486\r
1237 \r
1238 rel8 (relative) 15 7+m 7+m 3\r
1239 rel16 (relative) 15 7+m 7+m 3\r
1240 rel32 (relative) - - 7+m 3\r
1241 reg16 (near, register indirect) 11 7+m 7+m 5\r
1242 reg32 (near, register indirect) - - 7+m 5\r
1243 mem16 (near, mem indirect) 18+EA 11+m 10+m 5\r
1244 mem32 (near, mem indirect) 24+EA 15+m 10+m 5\r
1245 ptr16:16 (far, dword immed) - - 12+m 17\r
1246 ptr16:16 (far, PM dword immed) - - 27+m 19\r
1247 ptr16:16 (call gate, same priv.) - 38+m 45+m 32\r
1248 ptr16:16 (via TSS) - 175+m TS 42+TS\r
1249 ptr16:16 (via task gate) - 180+m TS 43+TS\r
1250 mem16:16 (far, indirect) - - 43+m 13\r
1251 mem16:16 (far, PM indirect) - - 31+m 18\r
1252 mem16:16 (call gate, same priv.) - 41+m 49+m 31\r
1253 mem16:16 (via TSS) - 178+m 5+TS 41+TS\r
1254 mem16:16 (via task gate) - 183+m 5+TS 42+TS\r
1255 ptr16:32 (far, 6 byte immed) - - 12+m 13\r
1256 ptr16:32 (far, PM 6 byte immed) - - 27+m 18\r
1257 ptr16:32 (call gate, same priv.) - - 45+m 31\r
1258 ptr16:32 (via TSS) - - TS 42+TS\r
1259 ptr16:32 (via task state) - - TS 43+TS\r
1260 m16:32 (far, address at dword) - - 43+m 13\r
1261 m16:32 (far, address at dword) - - 31+m 18\r
1262 m16:32 (call gate, same priv.) - - 49+m 31\r
1263 m16:32 (via TSS) - - 5+TS 41+TS\r
1264 m16:32 (via task state) - - 5+TS 42+TS\r
1265 \r
1266 \r
1267 LAHF - Load Register AH From Flags\r
1268 \r
1269 Usage: LAHF\r
1270 Modifies flags: None\r
1271 \r
1272 Copies bits 0-7 of the flags register into AH. This includes flags\r
1273 AF, CF, PF, SF and ZF other bits are undefined.\r
1274 \r
1275 AH := SF ZF xx AF xx PF xx CF\r
1276 \r
1277 Clocks Size\r
1278 Operands 808x 286 386 486 Bytes\r
1279 \r
1280 none 4 2 2 3 1\r
1281 \r
1282 \r
1283 LAR - Load Access Rights (286+ protected)\r
1284 \r
1285 Usage: LAR dest,src\r
1286 Modifies flags: ZF\r
1287 \r
1288 The high byte of the of the destination register is overwritten by\r
1289 the value of the access rights byte and the low order byte is zeroed\r
1290 depending on the selection in the source operand. The Zero Flag is\r
1291 set if the load operation is successful.\r
1292 \r
1293 Clocks Size\r
1294 Operands 808x 286 386 486 Bytes\r
1295 \r
1296 reg16,reg16 - 14 15 11 3\r
1297 reg32,reg32 - - 15 11 3\r
1298 reg16,mem16 - 16 16 11 3-7\r
1299 reg32,mem32 - - 16 11 3-7\r
1301 \r
1302 Usage: LDS dest,src\r
1303 Modifies flags: None\r
1304 \r
1305 Loads 32-bit pointer from memory source to destination register\r
1306 and DS. The offset is placed in the destination register and the\r
1307 segment is placed in DS. To use this instruction the word at the\r
1308 lower memory address must contain the offset and the word at the\r
1309 higher address must contain the segment. This simplifies the loading\r
1310 of far pointers from the stack and the interrupt vector table.\r
1311 \r
1312 Clocks Size\r
1313 Operands 808x 286 386 486 Bytes\r
1314 \r
1315 reg16,mem32 16+EA 7 7 6 2-4\r
1316 reg,mem (PM) - - 22 12 5-7\r
1317 \r
1318 \r
1319 LEA - Load Effective Address\r
1320 \r
1321 Usage: LEA dest,src\r
1322 Modifies flags: None\r
1323 \r
1324 Transfers offset address of "src" to the destination register.\r
1325 \r
1326 Clocks Size\r
1327 Operands 808x 286 386 486 Bytes\r
1328 \r
1329 reg,mem 2+EA 3 2 1 2-4\r
1330 \r
1331 - the MOV instruction can often save clock cycles when used in\r
1332 place of LEA on 8088 processors\r
1333 \r
1334 \r
1335 LEAVE - Restore Stack for Procedure Exit (80188+)\r
1336 \r
1337 Usage: LEAVE\r
1338 Modifies flags: None\r
1339 \r
1340 Releases the local variables created by the previous ENTER\r
1341 instruction by restoring SP and BP to their condition before\r
1342 the procedure stack frame was initialized.\r
1343 \r
1344 Clocks Size\r
1345 Operands 808x 286 386 486 Bytes\r
1346 \r
1347 none - 5 4 5 1\r
1348 \r
1349 \r
1350 LES - Load Pointer Using ES\r
1351 \r
1352 Usage: LES dest,src\r
1353 Modifies flags: None\r
1354 \r
1355 Loads 32-bit pointer from memory source to destination register\r
1356 and ES. The offset is placed in the destination register and the\r
1357 segment is placed in ES. To use this instruction the word at the\r
1358 lower memory address must contain the offset and the word at the\r
1359 higher address must contain the segment. This simplifies the loading\r
1360 of far pointers from the stack and the interrupt vector table.\r
1361 \r
1362 Clocks Size\r
1363 Operands 808x 286 386 486 Bytes\r
1364 \r
1365 reg,mem 16+EA 7 7 6 2-4 (W88=24+EA)\r
1366 reg,mem (PM) - - 22 12 5-7\r
1368 \r
1369 Usage: LFS dest,src\r
1370 Modifies flags: None\r
1371 \r
1372 Loads 32-bit pointer from memory source to destination register\r
1373 and FS. The offset is placed in the destination register and the\r
1374 segment is placed in FS. To use this instruction the word at the\r
1375 lower memory address must contain the offset and the word at the\r
1376 higher address must contain the segment. This simplifies the loading\r
1377 of far pointers from the stack and the interrupt vector table.\r
1378 \r
1379 Clocks Size\r
1380 Operands 808x 286 386 486 Bytes\r
1381 \r
1382 reg,mem - - 7 6 5-7\r
1383 reg,mem (PM) - - 22 12 5-7\r
1384 \r
1385 \r
1386 LGDT - Load Global Descriptor Table (286+ privileged)\r
1387 \r
1388 Usage: LGDT src\r
1389 Modifies flags: None\r
1390 \r
1391 Loads a value from an operand into the Global Descriptor Table\r
1392 (GDT) register.\r
1393 \r
1394 Clocks Size\r
1395 Operands 808x 286 386 486 Bytes\r
1396 \r
1397 mem64 - 11 11 11 5\r
1398 \r
1399 \r
1400 LIDT - Load Interrupt Descriptor Table (286+ privileged)\r
1401 \r
1402 Usage: LIDT src\r
1403 Modifies flags: None\r
1404 \r
1405 Loads a value from an operand into the Interrupt Descriptor Table\r
1406 (IDT) register.\r
1407 \r
1408 Clocks Size\r
1409 Operands 808x 286 386 486 Bytes\r
1410 \r
1411 mem64 - 12 11 11 5\r
1412 \r
1413 \r
1414 LGS - Load Pointer Using GS (386+)\r
1415 \r
1416 Usage: LGS dest,src\r
1417 Modifies flags: None\r
1418 \r
1419 Loads 32-bit pointer from memory source to destination register\r
1420 and GS. The offset is placed in the destination register and the\r
1421 segment is placed in GS. To use this instruction the word at the\r
1422 lower memory address must contain the offset and the word at the\r
1423 higher address must contain the segment. This simplifies the loading\r
1424 of far pointers from the stack and the interrupt vector table.\r
1425 \r
1426 Clocks Size\r
1427 Operands 808x 286 386 486 Bytes\r
1428 \r
1429 reg,mem - - 7 6 5-7\r
1430 reg,mem (PM) - - 22 12 5-7\r
1432 \r
1433 Usage: LLDT src\r
1434 Modifies flags: None\r
1435 \r
1436 Loads a value from an operand into the Local Descriptor Table \r
1437 Register (LDTR).\r
1438 \r
1439 Clocks Size\r
1440 Operands 808x 286 386 486 Bytes\r
1441 \r
1442 reg16 - 17 20 11 3\r
1443 mem16 - 19 24 11 5\r
1444 \r
1445 \r
1446 LMSW - Load Machine Status Word (286+ privileged)\r
1447 \r
1448 Usage: LMSW src\r
1449 Modifies flags: None\r
1450 \r
1451 Loads the Machine Status Word (MSW) from data found at "src"\r
1452 \r
1453 Clocks Size\r
1454 Operands 808x 286 386 486 Bytes\r
1455 \r
1456 reg16 - 3 10 13 3\r
1457 mem16 - 6 13 13 5\r
1458 \r
1459 \r
1460 LOCK - Lock Bus\r
1461 \r
1462 Usage: LOCK\r
1463 LOCK: (386+ prefix)\r
1464 Modifies flags: None\r
1465 \r
1466 This instruction is a prefix that causes the CPU assert bus lock\r
1467 signal during the execution of the next instruction. Used to\r
1468 avoid two processors from updating the same data location. The\r
1469 286 always asserts lock during an XCHG with memory operands. This\r
1470 should only be used to lock the bus prior to XCHG, MOV, IN and\r
1471 OUT instructions.\r
1472 \r
1473 Clocks Size\r
1474 Operands 808x 286 386 486 Bytes\r
1475 \r
1476 none 2 0 0 1 1\r
1477 \r
1478 \r
1479 LODS - Load String (Byte, Word or Double)\r
1480 \r
1481 Usage: LODS src\r
1482 LODSB\r
1483 LODSW\r
1484 LODSD (386+)\r
1485 Modifies flags: None\r
1486 \r
1487 Transfers string element addressed by DS:SI (even if an operand is\r
1488 supplied) to the accumulator. SI is incremented based on the size\r
1489 of the operand or based on the instruction used. If the Direction\r
1490 Flag is set SI is decremented, if the Direction Flag is clear SI\r
1491 is incremented. Use with REP prefixes.\r
1492 \r
1493 Clocks Size\r
1494 Operands 808x 286 386 486 Bytes\r
1495 \r
1496 src 12/16 5 5 5 1\r
1498 \r
1499 Usage: LOOP label\r
1500 Modifies flags: None\r
1501 \r
1502 Decrements CX by 1 and transfers control to "label" if CX is not\r
1503 Zero. The "label" operand must be within -128 or 127 bytes of the\r
1504 instruction following the loop instruction\r
1505 \r
1506 Clocks Size\r
1507 Operands 808x 286 386 486 Bytes\r
1508 \r
1509 label: jump 18 8+m 11+m 6 2\r
1510 no jump 5 4 ? 2\r
1511 \r
1512 \r
1513 LOOPE/LOOPZ - Loop While Equal / Loop While Zero\r
1514 \r
1515 Usage: LOOPE label\r
1516 LOOPZ label\r
1517 Modifies flags: None\r
1518 \r
1519 Decrements CX by 1 (without modifying the flags) and transfers\r
1520 control to "label" if CX != 0 and the Zero Flag is set. The\r
1521 "label" operand must be within -128 or 127 bytes of the instruction\r
1522 following the loop instruction.\r
1523 \r
1524 Clocks Size\r
1525 Operands 808x 286 386 486 Bytes\r
1526 \r
1527 label: jump 18 8+m 11+m 9 2\r
1528 no jump 5 4 ? 6\r
1529 \r
1530 \r
1531 LOOPNZ/LOOPNE - Loop While Not Zero / Loop While Not Equal\r
1532 \r
1533 Usage: LOOPNZ label\r
1534 LOOPNE label\r
1535 Modifies flags: None\r
1536 \r
1537 Decrements CX by 1 (without modifying the flags) and transfers\r
1538 control to "label" if CX != 0 and the Zero Flag is clear. The\r
1539 "label" operand must be within -128 or 127 bytes of the instruction\r
1540 following the loop instruction.\r
1541 \r
1542 Clocks Size\r
1543 Operands 808x 286 386 486 Bytes\r
1544 \r
1545 label: jump 19 8+m 11+m 9 2\r
1546 no jump 5 4 ? 6\r
1547 \r
1548 \r
1549 LSL - Load Segment Limit (286+ protected)\r
1550 \r
1551 Usage: LSL dest,src\r
1552 Modifies flags: ZF\r
1553 \r
1554 Loads the segment limit of a selector into the destination register\r
1555 if the selector is valid and visible at the current privilege level.\r
1556 If loading is successful the Zero Flag is set, otherwise it is\r
1557 cleared.\r
1558 \r
1559 Clocks Size\r
1560 Operands 808x 286 386 486 Bytes\r
1561 \r
1562 reg16,reg16 - 14 20/25 10 3\r
1563 reg32,reg32 - - 20/25 10 3\r
1564 reg16,mem16 - 16 21/26 10 5\r
1565 reg32,mem32 - - 21/26 10 5\r
1566 \r
1567 - 386 times are listed "byte granular" / "page granular"\r
1569 \r
1570 Usage: LSS dest,src\r
1571 Modifies flags: None\r
1572 \r
1573 Loads 32-bit pointer from memory source to destination register\r
1574 and SS. The offset is placed in the destination register and the\r
1575 segment is placed in SS. To use this instruction the word at the\r
1576 lower memory address must contain the offset and the word at the\r
1577 higher address must contain the segment. This simplifies the loading\r
1578 of far pointers from the stack and the interrupt vector table.\r
1579 \r
1580 Clocks Size\r
1581 Operands 808x 286 386 486 Bytes\r
1582 \r
1583 reg,mem - - 7 6 5-7\r
1584 reg,mem (PM) - - 22 12 5-7\r
1585 \r
1586 \r
1587 LTR - Load Task Register (286+ privileged)\r
1588 \r
1589 Usage: LTR src\r
1590 Modifies flags: None\r
1591 \r
1592 Loads the current task register with the value specified in "src".\r
1593 \r
1594 Clocks Size\r
1595 Operands 808x 286 386 486 Bytes\r
1596 \r
1597 reg16 - 17 23 20 3\r
1598 mem16 - 19 27 20 5\r
1599 \r
1600 \r
1601 MOV - Move Byte or Word\r
1602 \r
1603 Usage: MOV dest,src\r
1604 Modifies flags: None\r
1605 \r
1606 Copies byte or word from the source operand to the destination\r
1607 operand. If the destination is SS interrupts are disabled except\r
1608 on early buggy 808x CPUs. Some CPUs disable interrupts if the\r
1609 destination is any of the segment registers\r
1610 \r
1611 Clocks Size\r
1612 Operands 808x 286 386 486 Bytes\r
1613 \r
1614 reg,reg 2 2 2 1 2\r
1615 mem,reg 9+EA 3 2 1 2-4 (W88=13+EA)\r
1616 reg,mem 8+EA 5 4 1 2-4 (W88=12+EA)\r
1617 mem,immed 10+EA 3 2 1 3-6 (W88=14+EA)\r
1618 reg,immed 4 2 2 1 2-3\r
1619 mem,accum 10 3 2 1 3 (W88=14)\r
1620 accum,mem 10 5 4 1 3 (W88=14)\r
1621 segreg,reg16 2 2 2 3 2\r
1622 segreg,mem16 8+EA 5 5 9 2-4 (W88=12+EA)\r
1623 reg16,segreg 2 2 2 3 2\r
1624 mem16,segreg 9+EA 3 2 3 2-4 (W88=13+EA)\r
1625 reg32,CR0/CR2/CR3 - - 6 4\r
1626 CR0,reg32 - - 10 16\r
1627 CR2,reg32 - - 4 4 3\r
1628 CR3,reg32 - - 5 4 3\r
1629 reg32,DR0/DR1/DR2/DR3 - 22 10 3\r
1630 reg32,DR6/DR7 - - 22 10 3\r
1631 DR0/DR1/DR2/DR3,reg32 - 22 11 3\r
1632 DR6/DR7,reg32 - - 16 11 3\r
1633 reg32,TR6/TR7 - - 12 4 3\r
1634 TR6/TR7,reg32 - - 12 4 3\r
1635 reg32,TR3 3\r
1636 TR3,reg32 6\r
1637 \r
1638 - when the 386 special registers are used all operands are 32 bits\r
1640 \r
1641 Usage: MOVS dest,src\r
1642 MOVSB\r
1643 MOVSW\r
1644 MOVSD (386+)\r
1645 Modifies flags: None\r
1646 \r
1647 Copies data from addressed by DS:SI (even if operands are given) to\r
1648 the location ES:DI destination and updates SI and DI based on the\r
1649 size of the operand or instruction used. SI and DI are incremented\r
1650 when the Direction Flag is cleared and decremented when the Direction\r
1651 Flag is Set. Use with REP prefixes.\r
1652 \r
1653 Clocks Size\r
1654 Operands 808x 286 386 486 Bytes\r
1655 \r
1656 dest,src 18 5 7 7 1 (W88=26)\r
1657 \r
1658 \r
1659 MOVSX - Move with Sign Extend (386+)\r
1660 \r
1661 Usage: MOVSX dest,src\r
1662 Modifies flags: None\r
1663 \r
1664 Copies the value of the source operand to the destination register\r
1665 with the sign extended.\r
1666 \r
1667 Clocks Size\r
1668 Operands 808x 286 386 486 Bytes\r
1669 \r
1670 reg,reg - - 3 3 3\r
1671 reg,mem - - 6 3 3-7\r
1672 \r
1673 \r
1674 MOVZX - Move with Zero Extend (386+)\r
1675 \r
1676 Usage: MOVZX dest,src\r
1677 Modifies flags: None\r
1678 \r
1679 Copies the value of the source operand to the destination register\r
1680 with the zeroes extended.\r
1681 \r
1682 Clocks Size\r
1683 Operands 808x 286 386 486 Bytes\r
1684 \r
1685 reg,reg - - 3 3 3\r
1686 reg,mem - - 6 3 3-7\r
1687 \r
1688 \r
1689 MUL - Unsigned Multiply\r
1690 \r
1691 Usage: MUL src\r
1692 Modifies flags: CF OF (AF,PF,SF,ZF undefined)\r
1693 \r
1694 Unsigned multiply of the accumulator by the source. If "src" is\r
1695 a byte value, then AL is used as the other multiplicand and the\r
1696 result is placed in AX. If "src" is a word value, then AX is\r
1697 multiplied by "src" and DX:AX receives the result. If "src" is\r
1698 a double word value, then EAX is multiplied by "src" and EDX:EAX\r
1699 receives the result. The 386+ uses an early out algorithm which\r
1700 makes multiplying any size value in EAX as fast as in the 8 or 16\r
1701 bit registers.\r
1702 \r
1703 Clocks Size\r
1704 Operands 808x 286 386 486 Bytes\r
1705 \r
1706 reg8 70-77 13 9-14 13-18 2\r
1707 reg16 118-113 21 9-22 13-26 2\r
1708 reg32 - - 9-38 13-42 2-4\r
1709 mem8 (76-83)+EA 16 12-17 13-18 2-4\r
1710 mem16 (124-139)+EA 24 12-25 13-26 2-4\r
1711 mem32 - - 12-21 13-42 2-4\r
1713 \r
1714 Usage: NEG dest\r
1715 Modifies flags: AF CF OF PF SF ZF\r
1716 \r
1717 Subtracts the destination from 0 and saves the 2s complement of\r
1718 "dest" back into "dest".\r
1719 \r
1720 Clocks Size\r
1721 Operands 808x 286 386 486 Bytes\r
1722 \r
1723 reg 3 2 2 1 2\r
1724 mem 16+EA 7 6 3 2-4 (W88=24+EA)\r
1725 \r
1726 \r
1727 NOP - No Operation (90h)\r
1728 \r
1729 Usage: NOP\r
1730 Modifies flags: None\r
1731 \r
1732 This is a do nothing instruction. It results in occupation of both\r
1733 space and time and is most useful for patching code segments.\r
1734 (This is the original XCHG AL,AL instruction)\r
1735 \r
1736 Clocks Size\r
1737 Operands 808x 286 386 486 Bytes\r
1738 \r
1739 none 3 3 3 1 1\r
1740 \r
1741 \r
1742 NOT - One's Compliment Negation (Logical NOT)\r
1743 \r
1744 Usage: NOT dest\r
1745 Modifies flags: None\r
1746 \r
1747 Inverts the bits of the "dest" operand forming the 1s complement.\r
1748 \r
1749 Clocks Size\r
1750 Operands 808x 286 386 486 Bytes\r
1751 \r
1752 reg 3 2 2 1 2\r
1753 mem 16+EA 7 6 3 2-4 (W88=24+EA)\r
1754 \r
1755 \r
1756 OR - Inclusive Logical OR\r
1757 \r
1758 Usage: OR dest,src\r
1759 Modifies flags: CF OF PF SF ZF (AF undefined)\r
1760 \r
1761 Logical inclusive OR of the two operands returning the result in\r
1762 the destination. Any bit set in either operand will be set in the\r
1763 destination.\r
1764 \r
1765 Clocks Size\r
1766 Operands 808x 286 386 486 Bytes\r
1767 \r
1768 reg,reg 3 2 2 1 2\r
1769 mem,reg 16+EA 7 7 3 2-4 (W88=24+EA)\r
1770 reg,mem 9+EA 7 6 2 2-4 (W88=13+EA)\r
1771 reg,immed 4 3 2 1 3-4\r
1772 mem8,immed8 17+EA 7 7 3 3-6\r
1773 mem16,immed16 25+EA 7 7 3 3-6\r
1774 accum,immed 4 3 2 1 2-3\r
1776 \r
1777 Usage: OUT port,accum\r
1778 Modifies flags: None\r
1779 \r
1780 Transfers byte in AL,word in AX or dword in EAX to the specified\r
1781 hardware port address. If the port number is in the range of 0-255\r
1782 it can be specified as an immediate. If greater than 255 then the\r
1783 port number must be specified in DX. Since the PC only decodes 10\r
1784 bits of the port address, values over 1023 can only be decoded by\r
1785 third party vendor equipment and also map to the port range 0-1023.\r
1786 \r
1787 Clocks Size\r
1788 Operands 808x 286 386 486 Bytes\r
1789 \r
1790 immed8,accum 10/14 3 10 16 2\r
1791 immed8,accum (PM) - - 4/24 11/31/29 2\r
1792 DX,accum 8/12 3 11 16 1\r
1793 DX,accum (PM) - - 5/25 10/30/29 1\r
1794 \r
1795 - 386+ protected mode timings depend on privilege levels.\r
1796 \r
1797 first number is the timing when: CPL ó IOPL\r
1798 second number is the timing when: CPL > IOPL\r
1799 third number is the timing when: virtual mode on 486 processor\r
1800 \r
1801 \r
1802 OUTS - Output String to Port (80188+)\r
1803 \r
1804 Usage: OUTS port,src\r
1805 OUTSB\r
1806 OUTSW\r
1807 OUTSD (386+)\r
1808 Modifies flags: None\r
1809 \r
1810 Transfers a byte, word or doubleword from "src" to the hardware\r
1811 port specified in DX. For instructions with no operands the "src"\r
1812 is located at DS:SI and SI is incremented or decremented by the\r
1813 size of the operand or the size dictated by the instruction format.\r
1814 When the Direction Flag is set SI is decremented, when clear, SI is\r
1815 incremented. If the port number is in the range of 0-255 it can\r
1816 be specified as an immediate. If greater than 255 then the port\r
1817 number must be specified in DX. Since the PC only decodes 10 bits\r
1818 of the port address, values over 1023 can only be decoded by third\r
1819 party vendor equipment and also map to the port range 0-1023.\r
1820 \r
1821 Clocks Size\r
1822 Operands 808x 286 386 486 Bytes\r
1823 \r
1824 port,src - 5 14 17 1\r
1825 port,src (PM) - - 8/28 10/32/30 1\r
1826 \r
1827 - 386+ protected mode timings depend on privilege levels.\r
1828 \r
1829 first number is the timing when: CPL ó IOPL\r
1830 second number is the timing when: CPL > IOPL\r
1831 third number is the timing when: virtual mode on 486 processor\r
1832 \r
1833 \r
1834 POP - Pop Word off Stack\r
1835 \r
1836 Usage: POP dest\r
1837 Modifies flags: None\r
1838 \r
1839 Transfers word at the current stack top (SS:SP) to the destination\r
1840 then increments SP by two to point to the new stack top. CS is not\r
1841 a valid destination.\r
1842 \r
1843 Clocks Size\r
1844 Operands 808x 286 386 486 Bytes\r
1845 \r
1846 reg16 8 5 4 4 1\r
1847 reg32 4 - - 4 1\r
1848 segreg 8 5 7 3 1\r
1849 mem16 17+EA 5 5 6 2-4\r
1850 mem32 5 - - 6 2-4\r
1852 \r
1853 Usage: POPA\r
1854 POPAD (386+)\r
1855 Modifies flags: None\r
1856 \r
1857 Pops the top 8 words off the stack into the 8 general purpose 16/32\r
1858 bit registers. Registers are popped in the following order: (E)DI,\r
1859 (E)SI, (E)BP, (E)SP, (E)DX, (E)CX and (E)AX. The (E)SP value popped\r
1860 from the stack is actually discarded.\r
1861 \r
1862 Clocks Size\r
1863 Operands 808x 286 386 486 Bytes\r
1864 \r
1865 none - 19 24 9 1\r
1866 \r
1867 \r
1868 POPF/POPFD - Pop Flags off Stack\r
1869 \r
1870 Usage: POPF\r
1871 POPFD (386+)\r
1872 Modifies flags: all flags\r
1873 \r
1874 Pops word/doubleword from stack into the Flags Register and then\r
1875 increments SP by 2 (for POPF) or 4 (for POPFD).\r
1876 \r
1877 Clocks Size\r
1878 Operands 808x 286 386 486 Bytes\r
1879 \r
1880 none 8/12 5 5 9 1 (W88=12)\r
1881 none (PM) - - 5 6 1\r
1882 \r
1883 \r
1884 PUSH - Push Word onto Stack\r
1885 \r
1886 Usage: PUSH src\r
1887 PUSH immed (80188+ only)\r
1888 Modifies flags: None\r
1889 \r
1890 Decrements SP by the size of the operand (two or four, byte values\r
1891 are sign extended) and transfers one word from source to the stack\r
1892 top (SS:SP).\r
1893 \r
1894 Clocks Size\r
1895 Operands 808x 286 386 486 Bytes\r
1896 \r
1897 reg16 11/15 3 2 1 1\r
1898 reg32 - - 2 1 1\r
1899 mem16 16+EA 5 5 4 2-4 (W88=24+EA)\r
1900 mem32 - - 5 4 2-4\r
1901 segreg 10/14 3 2 3 1\r
1902 immed - 3 2 1 2-3\r
1903 \r
1904 \r
1905 PUSHA/PUSHAD - Push All Registers onto Stack (80188+)\r
1906 \r
1907 Usage: PUSHA\r
1908 PUSHAD (386+)\r
1909 Modifies flags: None\r
1910 \r
1911 Pushes all general purpose registers onto the stack in the following\r
1912 order: (E)AX, (E)CX, (E)DX, (E)BX, (E)SP, (E)BP, (E)SI, (E)DI. The\r
1913 value of SP is the value before the actual push of SP.\r
1914 \r
1915 Clocks Size\r
1916 Operands 808x 286 386 486 Bytes\r
1917 \r
1918 none - 19 24 11 1\r
1920 \r
1921 Usage: PUSHF\r
1922 PUSHFD (386+)\r
1923 Modifies flags: None\r
1924 \r
1925 Transfers the Flags Register onto the stack. PUSHF saves a 16 bit\r
1926 value while PUSHFD saves a 32 bit value.\r
1927 \r
1928 Clocks Size\r
1929 Operands 808x 286 386 486 Bytes\r
1930 \r
1931 none 10/14 3 4 4 1\r
1932 none (PM) - - 4 3 1\r
1933 \r
1934 \r
1935 RCL - Rotate Through Carry Left\r
1936 \r
1937 Usage: RCL dest,count\r
1938 Modifies flags: CF OF\r
1939 \r
1940 ÚÄ¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿\r
1941 ÚÄþ³C³<þÄÄþ³7 <ÄÄÄÄÄÄÄÄÄÄ 0³<Ä¿\r
1942 ³ ÀÄÙ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ ³\r
1943 ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ\r
1944 \r
1945 Rotates the bits in the destination to the left "count" times with\r
1946 all data pushed out the left side re-entering on the right. The\r
1947 Carry Flag holds the last bit rotated out.\r
1948 \r
1949 Clocks Size\r
1950 Operands 808x 286 386 486 Bytes\r
1951 \r
1952 reg,1 2 2 9 3 2\r
1953 mem,1 15+EA 7 10 4 2-4 (W88=23+EA)\r
1954 reg,CL 8+4n 5+n 9 8-30 2\r
1955 mem,CL 20+EA+4n 8+n 10 9-31 2-4 (W88=28+EA+4n)\r
1956 reg,immed8 - 5+n 9 8-30 3\r
1957 mem,immed8 - 8+n 10 9-31 3-5\r
1958 \r
1959 \r
1960 RCR - Rotate Through Carry Right\r
1961 \r
1962 Usage: RCR dest,count\r
1963 Modifies flags: CF OF\r
1964 \r
1965 ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ ÚÄ¿\r
1966 ÚÄ>³7 þÄÄÄÄÄÄÄÄÄ> 0³þÄÄÄ>³C³þÄ¿\r
1967 ³ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ ÀÄÙ ³\r
1968 ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ\r
1969 \r
1970 Rotates the bits in the destination to the right "count" times with\r
1971 all data pushed out the right side re-entering on the left. The\r
1972 Carry Flag holds the last bit rotated out.\r
1973 \r
1974 Clocks Size\r
1975 Operands 808x 286 386 486 Bytes\r
1976 \r
1977 reg,1 2 2 9 3 2\r
1978 mem,1 15+EA 7 10 4 2-4 (W88=23+EA)\r
1979 reg,CL 8+4n 5+n 9 8-30 2\r
1980 mem,CL 20+EA+4n 8+n 10 9-31 2-4 (W88=28+EA+4n)\r
1981 reg,immed8 - 5+n 9 8-30 3\r
1982 mem,immed8 - 8+n 10 9-31 3-5\r
1984 \r
1985 Usage: REP\r
1986 Modifies flags: None\r
1987 \r
1988 Repeats execution of string instructions while CX != 0. After\r
1989 each string operation, CX is decremented and the Zero Flag is\r
1990 tested. The combination of a repeat prefix and a segment override\r
1991 on CPU's before the 386 may result in errors if an interrupt occurs\r
1992 before CX=0. The following code shows code that is susceptible to\r
1993 this and how to avoid it:\r
1994 \r
1995 again: rep movs byte ptr ES:[DI],ES:[SI] ; vulnerable instr.\r
1996 jcxz next ; continue if REP successful\r
1997 loop again ; interrupt goofed count\r
1998 next:\r
1999 \r
2000 Clocks Size\r
2001 Operands 808x 286 386 486 Bytes\r
2002 \r
2003 none 2 2 2 1\r
2004 \r
2005 \r
2006 REPE/REPZ - Repeat Equal / Repeat Zero\r
2007 \r
2008 Usage: REPE\r
2009 REPZ\r
2010 Modifies flags: None\r
2011 \r
2012 Repeats execution of string instructions while CX != 0 and the Zero\r
2013 Flag is set. CX is decremented and the Zero Flag tested after\r
2014 each string operation. The combination of a repeat prefix and a\r
2015 segment override on processors other than the 386 may result in\r
2016 errors if an interrupt occurs before CX=0.\r
2017 \r
2018 Clocks Size\r
2019 Operands 808x 286 386 486 Bytes\r
2020 \r
2021 none 2 2 2 1\r
2022 \r
2023 \r
2024 REPNE/REPNZ - Repeat Not Equal / Repeat Not Zero\r
2025 \r
2026 Usage: REPNE\r
2027 REPNZ\r
2028 Modifies flags: None\r
2029 \r
2030 Repeats execution of string instructions while CX != 0 and the Zero\r
2031 Flag is clear. CX is decremented and the Zero Flag tested after\r
2032 each string operation. The combination of a repeat prefix and a\r
2033 segment override on processors other than the 386 may result in\r
2034 errors if an interrupt occurs before CX=0.\r
2035 \r
2036 Clocks Size\r
2037 Operands 808x 286 386 486 Bytes\r
2038 \r
2039 none 2 2 2 1\r
2041 \r
2042 Usage: RET nBytes\r
2043 RETF nBytes\r
2044 RETN nBytes\r
2045 Modifies flags: None\r
2046 \r
2047 Transfers control from a procedure back to the instruction address\r
2048 saved on the stack. "n bytes" is an optional number of bytes to\r
2049 release. Far returns pop the IP followed by the CS, while near\r
2050 returns pop only the IP register.\r
2051 \r
2052 Clocks Size\r
2053 Operands 808x 286 386 486 Bytes\r
2054 \r
2055 retn 16/20 11+m 10+m 5 1\r
2056 retn immed 20/24 11+m 10+m 5 3\r
2057 retf 26/34 15+m 18+m 13 1\r
2058 retf (PM, same priv.) - 32+m 18 1\r
2059 retf (PM, lesser priv.) - 68 33 1\r
2060 retf immed 25/33 15+m 18+m 14 3\r
2061 retf immed (PM, same priv.) 32+m 17 1\r
2062 retf immed (PM, lesser priv.) 68 33 1\r
2063 \r
2064 \r
2065 ROL - Rotate Left\r
2066 \r
2067 Usage: ROL dest,count\r
2068 Modifies flags: CF OF\r
2069 \r
2070 ÚÄ¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿\r
2071 ³C³<þÂÄþ³7 <ÄÄÄÄÄÄÄÄÄÄ 0³<Ä¿\r
2072 ÀÄÙ ³ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ ³\r
2073 ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ\r
2074 \r
2075 Rotates the bits in the destination to the left "count" times with\r
2076 all data pushed out the left side re-entering on the right. The\r
2077 Carry Flag will contain the value of the last bit rotated out.\r
2078 \r
2079 Clocks Size\r
2080 Operands 808x 286 386 486 Bytes\r
2081 \r
2082 reg,1 2 2 3 3 2\r
2083 mem,1 15+EA 7 7 4 2-4 (W88=23+EA)\r
2084 reg,CL 8+4n 5+n 3 3 2\r
2085 mem,CL 20+EA+4n 8+n 7 4 2-4 (W88=28+EA+4n)\r
2086 reg,immed8 - 5+n 3 2 3\r
2087 mem,immed8 - 8+n 7 4 3-5\r
2088 \r
2089 \r
2090 ROR - Rotate Right\r
2091 \r
2092 Usage: ROR dest,count\r
2093 Modifies flags: CF OF\r
2094 \r
2095 ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ ÚÄ¿\r
2096 ÚÄ>³7 þÄÄÄÄÄÄÄÄÄ> 0³þÄÂÄ>³C³ \r
2097 ³ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ ³ ÀÄÙ \r
2098 ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ \r
2099 \r
2100 Rotates the bits in the destination to the right "count" times with\r
2101 all data pushed out the right side re-entering on the left. The\r
2102 Carry Flag will contain the value of the last bit rotated out.\r
2103 \r
2104 Clocks Size\r
2105 Operands 808x 286 386 486 Bytes\r
2106 \r
2107 reg,1 2 2 3 3 2\r
2108 mem,1 15+EA 7 7 4 2-4 (W88=23+EA)\r
2109 reg,CL 8+4n 5+n 3 3 2\r
2110 mem,CL 20+EA+4n 8+n 7 4 2-4 (W88=28+EA+4n)\r
2111 reg,immed8 - 5+n 3 2 3\r
2112 mem,immed8 - 8+n 7 4 3-5\r
2114 \r
2115 Usage: SAHF\r
2116 Modifies flags: AF CF PF SF ZF\r
2117 \r
2118 Transfers bits 0-7 of AH into the Flags Register. This includes\r
2119 AF, CF, PF, SF and ZF.\r
2120 \r
2121 Clocks Size\r
2122 Operands 808x 286 386 486 Bytes\r
2123 \r
2124 none 4 2 3 2 1\r
2125 \r
2126 \r
2127 SAL/SHL - Shift Arithmetic Left / Shift Logical Left\r
2128 \r
2129 Usage: SAL dest,count\r
2130 SHL dest,count\r
2131 Modifies flags: CF OF PF SF ZF (AF undefined)\r
2132 \r
2133 ÚÄ¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ ÚÄ¿\r
2134 ³C³<ÄÄÄþ³7 <ÄÄÄÄÄÄÄÄÄÄ 0³<ÄÄÄþ³0³\r
2135 ÀÄÙ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ ÀÄÙ\r
2136 \r
2137 Shifts the destination left by "count" bits with zeroes shifted\r
2138 in on right. The Carry Flag contains the last bit shifted out.\r
2139 \r
2140 Clocks Size\r
2141 Operands 808x 286 386 486 Bytes\r
2142 \r
2143 reg,1 2 2 3 3 2\r
2144 mem,1 15+EA 7 7 4 2-4 (W88=23+EA)\r
2145 reg,CL 8+4n 5+n 3 3 2\r
2146 mem,CL 20+EA+4n 8+n 7 4 2-4 (W88=28+EA+4n)\r
2147 reg,immed8 - 5+n 3 2 3\r
2148 mem,immed8 - 8+n 7 4 3-5\r
2149 \r
2150 \r
2151 SAR - Shift Arithmetic Right\r
2152 \r
2153 Usage: SAR dest,count\r
2154 Modifies flags: CF OF PF SF ZF (AF undefined)\r
2155 \r
2156 ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ ÚÄ¿\r
2157 ÚÄþ³7 ÄÄÄÄÄÄÄÄÄÄ> 0³ÄÄÄþ>³C³\r
2158 ³ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ ÀÄÙ\r
2159 ÀÄÄÄ^\r
2160 \r
2161 Shifts the destination right by "count" bits with the current sign\r
2162 bit replicated in the leftmost bit. The Carry Flag contains the\r
2163 last bit shifted out.\r
2164 \r
2165 Clocks Size\r
2166 Operands 808x 286 386 486 Bytes\r
2167 \r
2168 reg,1 2 2 3 3 2\r
2169 mem,1 15+EA 7 7 4 2-4 (W88=23+EA)\r
2170 reg,CL 8+4n 5+n 3 3 2\r
2171 mem,CL 20+EA+4n 8+n 7 4 2-4 (W88=28+EA+4n)\r
2172 reg,immed8 - 5+n 3 2 3\r
2173 mem,immed8 - 8+n 7 4 3-5\r
2175 \r
2176 Usage: SBB dest,src\r
2177 Modifies flags: AF CF OF PF SF ZF\r
2178 \r
2179 Subtracts the source from the destination, and subtracts 1 extra if\r
2180 the Carry Flag is set. Results are returned in "dest".\r
2181 \r
2182 Clocks Size\r
2183 Operands 808x 286 386 486 Bytes\r
2184 \r
2185 reg,reg 3 2 2 1 2\r
2186 mem,reg 16+EA 7 6 3 2-4 (W88=24+EA)\r
2187 reg,mem 9+EA 7 7 2 2-4 (W88=13+EA)\r
2188 reg,immed 4 3 2 1 3-4\r
2189 mem,immed 17+EA 7 7 3 3-6 (W88=25+EA)\r
2190 accum,immed 4 3 2 1 2-3\r
2191 \r
2192 \r
2193 SCAS - Scan String (Byte, Word or Doubleword)\r
2194 \r
2195 Usage: SCAS string\r
2196 SCASB\r
2197 SCASW\r
2198 SCASD (386+)\r
2199 Modifies flags: AF CF OF PF SF ZF\r
2200 \r
2201 Compares value at ES:DI (even if operand is specified) from the\r
2202 accumulator and sets the flags similar to a subtraction. DI is\r
2203 incremented/decremented based on the instruction format (or\r
2204 operand size) and the state of the Direction Flag. Use with REP\r
2205 prefixes.\r
2206 \r
2207 Clocks Size\r
2208 Operands 808x 286 386 486 Bytes\r
2209 \r
2210 string 15 7 7 6 1 (W88=19)\r
2211 \r
2212 \r
2213 SETAE/SETNB - Set if Above or Equal / Set if Not Below (386+)\r
2214 \r
2215 Usage: SETAE dest\r
2216 SETNB dest\r
2217 (unsigned, 386+)\r
2218 Modifies flags: none\r
2219 \r
2220 Sets the byte in the operand to 1 if the Carry Flag is clear\r
2221 otherwise sets the operand to 0.\r
2222 \r
2223 Clocks Size\r
2224 Operands 808x 286 386 486 Bytes\r
2225 \r
2226 reg8 - - 4 3 3\r
2227 mem8 - - 5 4 3\r
2228 \r
2229 \r
2230 SETB/SETNAE - Set if Below / Set if Not Above or Equal (386+)\r
2231 \r
2232 Usage: SETB dest\r
2233 SETNAE dest\r
2234 (unsigned, 386+)\r
2235 Modifies flags: none\r
2236 \r
2237 Sets the byte in the operand to 1 if the Carry Flag is set\r
2238 otherwise sets the operand to 0.\r
2239 \r
2240 Clocks Size\r
2241 Operands 808x 286 386 486 Bytes\r
2242 \r
2243 reg8 - - 4 3 3\r
2244 mem8 - - 5 4 3\r
2246 \r
2247 Usage: SETBE dest\r
2248 SETNA dest\r
2249 (unsigned, 386+)\r
2250 Modifies flags: none\r
2251 \r
2252 Sets the byte in the operand to 1 if the Carry Flag or the Zero\r
2253 Flag is set, otherwise sets the operand to 0.\r
2254 \r
2255 Clocks Size\r
2256 Operands 808x 286 386 486 Bytes\r
2257 \r
2258 reg8 - - 4 3 3\r
2259 mem8 - - 5 4 3\r
2260 \r
2261 \r
2262 SETE/SETZ - Set if Equal / Set if Zero (386+)\r
2263 \r
2264 Usage: SETE dest\r
2265 SETZ dest\r
2266 Modifies flags: none\r
2267 \r
2268 Sets the byte in the operand to 1 if the Zero Flag is set,\r
2269 otherwise sets the operand to 0.\r
2270 \r
2271 Clocks Size\r
2272 Operands 808x 286 386 486 Bytes\r
2273 \r
2274 reg8 - - 4 3 3\r
2275 mem8 - - 5 4 3\r
2276 \r
2277 \r
2278 SETNE/SETNZ - Set if Not Equal / Set if Not Zero (386+)\r
2279 \r
2280 Usage: SETNE dest\r
2281 SETNZ dest\r
2282 Modifies flags: none\r
2283 \r
2284 Sets the byte in the operand to 1 if the Zero Flag is clear,\r
2285 otherwise sets the operand to 0.\r
2286 \r
2287 Clocks Size\r
2288 Operands 808x 286 386 486 Bytes\r
2289 \r
2290 reg8 - - 4 3 3\r
2291 mem8 - - 5 4 3\r
2292 \r
2293 \r
2294 SETL/SETNGE - Set if Less / Set if Not Greater or Equal (386+)\r
2295 \r
2296 Usage: SETL dest\r
2297 SETNGE dest\r
2298 (signed, 386+)\r
2299 Modifies flags: none\r
2300 \r
2301 Sets the byte in the operand to 1 if the Sign Flag is not equal\r
2302 to the Overflow Flag, otherwise sets the operand to 0.\r
2303 \r
2304 Clocks Size\r
2305 Operands 808x 286 386 486 Bytes\r
2306 \r
2307 reg8 - - 4 3 3\r
2308 mem8 - - 5 4 3\r
2310 \r
2311 Usage: SETGE dest\r
2312 SETNL dest\r
2313 (signed, 386+)\r
2314 Modifies flags: none\r
2315 \r
2316 Sets the byte in the operand to 1 if the Sign Flag equals the\r
2317 Overflow Flag, otherwise sets the operand to 0.\r
2318 \r
2319 Clocks Size\r
2320 Operands 808x 286 386 486 Bytes\r
2321 \r
2322 reg8 - - 4 3 3\r
2323 mem8 - - 5 4 3\r
2324 \r
2325 \r
2326 SETLE/SETNG - Set if Less or Equal / Set if Not greater or Equal (386+)\r
2327 \r
2328 Usage: SETLE dest\r
2329 SETNG dest\r
2330 (signed, 386+)\r
2331 Modifies flags: none\r
2332 \r
2333 Sets the byte in the operand to 1 if the Zero Flag is set or the\r
2334 Sign Flag is not equal to the Overflow Flag, otherwise sets the\r
2335 operand to 0.\r
2336 \r
2337 Clocks Size\r
2338 Operands 808x 286 386 486 Bytes\r
2339 \r
2340 reg8 - - 4 3 3\r
2341 mem8 - - 5 4 3\r
2342 \r
2343 \r
2344 SETG/SETNLE - Set if Greater / Set if Not Less or Equal (386+)\r
2345 \r
2346 Usage: SETG dest\r
2347 SETNLE dest\r
2348 (signed, 386+)\r
2349 Modifies flags: none\r
2350 \r
2351 Sets the byte in the operand to 1 if the Zero Flag is clear or the\r
2352 Sign Flag equals to the Overflow Flag, otherwise sets the operand\r
2353 to 0.\r
2354 \r
2355 Clocks Size\r
2356 Operands 808x 286 386 486 Bytes\r
2357 \r
2358 reg8 - - 4 3 3\r
2359 mem8 - - 5 4 3\r
2360 \r
2361 \r
2362 SETS - Set if Signed (386+)\r
2363 \r
2364 Usage: SETS dest\r
2365 Modifies flags: none\r
2366 \r
2367 Sets the byte in the operand to 1 if the Sign Flag is set, otherwise\r
2368 sets the operand to 0.\r
2369 \r
2370 Clocks Size\r
2371 Operands 808x 286 386 486 Bytes\r
2372 \r
2373 reg8 - - 4 3 3\r
2374 mem8 - - 5 4 3\r
2376 \r
2377 Usage: SETNS dest\r
2378 Modifies flags: none\r
2379 \r
2380 Sets the byte in the operand to 1 if the Sign Flag is clear,\r
2381 otherwise sets the operand to 0.\r
2382 \r
2383 Clocks Size\r
2384 Operands 808x 286 386 486 Bytes\r
2385 \r
2386 reg8 - - 4 3 3\r
2387 mem8 - - 5 4 3\r
2388 \r
2389 \r
2390 SETC - Set if Carry (386+)\r
2391 \r
2392 Usage: SETC dest\r
2393 Modifies flags: none\r
2394 \r
2395 Sets the byte in the operand to 1 if the Carry Flag is set,\r
2396 otherwise sets the operand to 0.\r
2397 \r
2398 Clocks Size\r
2399 Operands 808x 286 386 486 Bytes\r
2400 \r
2401 reg8 - - 4 3 3\r
2402 mem8 - - 5 4 3\r
2403 \r
2404 \r
2405 SETNC - Set if Not Carry (386+)\r
2406 \r
2407 Usage: SETNC dest\r
2408 Modifies flags: none\r
2409 \r
2410 Sets the byte in the operand to 1 if the Carry Flag is clear,\r
2411 otherwise sets the operand to 0.\r
2412 \r
2413 Clocks Size\r
2414 Operands 808x 286 386 486 Bytes\r
2415 \r
2416 reg8 - - 4 3 3\r
2417 mem8 - - 5 4 3\r
2418 \r
2419 \r
2420 SETO - Set if Overflow (386+)\r
2421 \r
2422 Usage: SETO dest\r
2423 Modifies flags: none\r
2424 \r
2425 Sets the byte in the operand to 1 if the Overflow Flag is set,\r
2426 otherwise sets the operand to 0.\r
2427 \r
2428 Clocks Size\r
2429 Operands 808x 286 386 486 Bytes\r
2430 \r
2431 reg8 - - 4 3 3\r
2432 mem8 - - 5 4 3\r
2433 \r
2434 \r
2435 SETNO - Set if Not Overflow (386+)\r
2436 \r
2437 Usage: SETNO dest\r
2438 Modifies flags: none\r
2439 \r
2440 Sets the byte in the operand to 1 if the Overflow Flag is clear,\r
2441 otherwise sets the operand to 0.\r
2442 \r
2443 Clocks Size\r
2444 Operands 808x 286 386 486 Bytes\r
2445 \r
2446 reg8 - - 4 3 3\r
2447 mem8 - - 5 4 3\r
2449 \r
2450 Usage: SETP dest\r
2451 SETPE dest\r
2452 Modifies flags: none\r
2453 \r
2454 Sets the byte in the operand to 1 if the Parity Flag is set,\r
2455 otherwise sets the operand to 0.\r
2456 \r
2457 Clocks Size\r
2458 Operands 808x 286 386 486 Bytes\r
2459 \r
2460 reg8 - - 4 3 3\r
2461 mem8 - - 5 4 3\r
2462 \r
2463 \r
2464 SETNP/SETPO - Set if No Parity / Set if Parity Odd (386+)\r
2465 \r
2466 Usage: SETNP dest\r
2467 SETPO dest\r
2468 Modifies flags: none\r
2469 \r
2470 Sets the byte in the operand to 1 if the Parity Flag is clear,\r
2471 otherwise sets the operand to 0.\r
2472 \r
2473 Clocks Size\r
2474 Operands 808x 286 386 486 Bytes\r
2475 \r
2476 reg8 - - 4 3 3\r
2477 mem8 - - 5 4 3\r
2478 \r
2479 \r
2480 SGDT - Store Global Descriptor Table (286+ privileged)\r
2481 \r
2482 Usage: SGDT dest\r
2483 Modifies flags: none\r
2484 \r
2485 Stores the Global Descriptor Table (GDT) Register into the\r
2486 specified operand.\r
2487 \r
2488 Clocks Size\r
2489 Operands 808x 286 386 486 Bytes\r
2490 \r
2491 mem64 - 11 9 10 5\r
2492 \r
2493 \r
2494 SIDT - Store Interrupt Descriptor Table (286+ privileged)\r
2495 \r
2496 Usage: SIDT dest\r
2497 Modifies flags: none\r
2498 \r
2499 Stores the Interrupt Descriptor Table (IDT) Register into the\r
2500 specified operand.\r
2501 \r
2502 Clocks Size\r
2503 Operands 808x 286 386 486 Bytes\r
2504 \r
2505 mem64 - 12 9 10 5\r
2506 \r
2507 \r
2508 SHL - Shift Logical Left\r
2509 \r
2510 See: SAL\r
2512 \r
2513 Usage: SHR dest,count\r
2514 Modifies flags: CF OF PF SF ZF (AF undefined)\r
2515 \r
2516 ÚÄ¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ ÚÄ¿\r
2517 ³0³ÄÄÄþ>³7 ÄÄÄÄÄÄÄÄÄÄ> 0³ÄÄÄþ>³C³\r
2518 ÀÄÙ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ ÀÄÙ\r
2519 \r
2520 Shifts the destination right by "count" bits with zeroes shifted\r
2521 in on the left. The Carry Flag contains the last bit shifted out.\r
2522 \r
2523 Clocks Size\r
2524 Operands 808x 286 386 486 Bytes\r
2525 \r
2526 reg,1 2 2 3 2\r
2527 mem,1 15+EA 7 7 2-4 (W88=23+EA)\r
2528 reg,CL 8+4n 5+n 3 2\r
2529 mem,CL 20+EA+4n 8+n 7 2-4 (W88=28+EA+4n)\r
2530 reg,immed8 - 5+n 3 3\r
2531 mem,immed8 - 8+n 7 3-5\r
2532 \r
2533 \r
2534 SHLD/SHRD - Double Precision Shift (386+)\r
2535 \r
2536 Usage: SHLD dest,src,count\r
2537 SHRD dest,src,count\r
2538 Modifies flags: CF PF SF ZF (OF,AF undefined)\r
2539 \r
2540 SHLD shifts "dest" to the left "count" times and the bit positions\r
2541 opened are filled with the most significant bits of "src". SHRD\r
2542 shifts "dest" to the right "count" times and the bit positions\r
2543 opened are filled with the least significant bits of the second\r
2544 operand. Only the 5 lower bits of "count" are used.\r
2545 \r
2546 Clocks Size\r
2547 Operands 808x 286 386 486 Bytes\r
2548 \r
2549 reg16,reg16,immed8 - - 3 2 4\r
2550 reg32,reg32,immed8 - - 3 2 4\r
2551 mem16,reg16,immed8 - - 7 3 6\r
2552 mem32,reg32,immed8 - - 7 3 6\r
2553 reg16,reg16,CL - - 3 3 3\r
2554 reg32,reg32,CL - - 3 3 3\r
2555 mem16,reg16,CL - - 7 4 5\r
2556 mem32,reg32,CL - - 7 4 5\r
2557 \r
2558 \r
2559 SLDT - Store Local Descriptor Table (286+ privileged)\r
2560 \r
2561 Usage: SLDT dest\r
2562 Modifies flags: none\r
2563 \r
2564 Stores the Local Descriptor Table (LDT) Register into the\r
2565 specified operand.\r
2566 \r
2567 Clocks Size\r
2568 Operands 808x 286 386 486 Bytes\r
2569 \r
2570 reg16 - 2 2 2 3\r
2571 mem16 - 2 2 3 5\r
2572 \r
2573 \r
2574 SMSW - Store Machine Status Word (286+ privileged)\r
2575 \r
2576 Usage: SMSW dest\r
2577 Modifies flags: none\r
2578 \r
2579 Store Machine Status Word (MSW) into "dest".\r
2580 \r
2581 Clocks Size\r
2582 Operands 808x 286 386 486 Bytes\r
2583 \r
2584 reg16 - 2 10 2 3\r
2585 mem16 - 3 3 3 5\r
2587 \r
2588 Usage: STC\r
2589 Modifies flags: CF\r
2590 \r
2591 Sets the Carry Flag to 1.\r
2592 \r
2593 Clocks Size\r
2594 Operands 808x 286 386 486 Bytes\r
2595 \r
2596 none 2 2 2 2 1\r
2597 \r
2598 \r
2599 STD - Set Direction Flag\r
2600 \r
2601 Usage: STD\r
2602 Modifies flags: DF\r
2603 \r
2604 Sets the Direction Flag to 1 causing string instructions to\r
2605 auto-decrement SI and DI instead of auto-increment.\r
2606 \r
2607 Clocks Size\r
2608 Operands 808x 286 386 486 Bytes\r
2609 \r
2610 none 2 2 2 2 1\r
2611 \r
2612 \r
2613 STI - Set Interrupt Flag (Enable Interrupts)\r
2614 \r
2615 Usage: STI\r
2616 Modifies flags: IF\r
2617 \r
2618 Sets the Interrupt Flag to 1, which enables recognition of all\r
2619 hardware interrupts. If an interrupt is generated by a hardware\r
2620 device, an End of Interrupt (EOI) must also be issued to enable\r
2621 other hardware interrupts of the same or lower priority.\r
2622 \r
2623 Clocks Size\r
2624 Operands 808x 286 386 486 Bytes\r
2625 \r
2626 none 2 2 2 5 1\r
2627 \r
2628 \r
2629 STOS - Store String (Byte, Word or Doubleword)\r
2630 \r
2631 Usage: STOS dest\r
2632 STOSB\r
2633 STOSW\r
2634 STOSD\r
2635 Modifies flags: None\r
2636 \r
2637 Stores value in accumulator to location at ES:(E)DI (even if operand\r
2638 is given). (E)DI is incremented/decremented based on the size of\r
2639 the operand (or instruction format) and the state of the Direction\r
2640 Flag. Use with REP prefixes.\r
2641 \r
2642 Clocks Size\r
2643 Operands 808x 286 386 486 Bytes\r
2644 \r
2645 dest 11 3 4 5 1 (W88=15)\r
2646 \r
2647 \r
2648 STR - Store Task Register (286+ privileged)\r
2649 \r
2650 Usage: STR dest\r
2651 Modifies flags: None\r
2652 \r
2653 Stores the current Task Register to the specified operand.\r
2654 \r
2655 Clocks Size\r
2656 Operands 808x 286 386 486 Bytes\r
2657 \r
2658 reg16 - 2 2 2 3\r
2659 mem16 - 3 2 3 5\r
2661 \r
2662 Usage: SUB dest,src\r
2663 Modifies flags: AF CF OF PF SF ZF\r
2664 \r
2665 The source is subtracted from the destination and the result is\r
2666 stored in the destination.\r
2667 \r
2668 Clocks Size\r
2669 Operands 808x 286 386 486 Bytes\r
2670 \r
2671 reg,reg 3 2 2 1 2\r
2672 mem,reg 16+EA 7 6 3 2-4 (W88=24+EA)\r
2673 reg,mem 9+EA 7 7 2 2-4 (W88=13+EA)\r
2674 reg,immed 4 3 2 1 3-4\r
2675 mem,immed 17+EA 7 7 3 3-6 (W88=25+EA)\r
2676 accum,immed 4 3 2 1 2-3\r
2677 \r
2678 \r
2679 TEST - Test For Bit Pattern\r
2680 \r
2681 Usage: TEST dest,src\r
2682 Modifies flags: CF OF PF SF ZF (AF undefined)\r
2683 \r
2684 Performs a logical AND of the two operands updating the flags\r
2685 register without saving the result.\r
2686 \r
2687 Clocks Size\r
2688 Operands 808x 286 386 486 Bytes\r
2689 \r
2690 reg,reg 3 2 1 1 2\r
2691 reg,mem 9+EA 6 5 1 2-4 (W88=13+EA)\r
2692 mem,reg 9+EA 6 5 2 2-4 (W88=13+EA)\r
2693 reg,immed 5 3 2 1 3-4\r
2694 mem,immed 11+EA 6 5 2 3-6\r
2695 accum,immed 4 3 2 1 2-3\r
2696 \r
2697 \r
2698 VERR - Verify Read (286+ protected)\r
2699 \r
2700 Usage: VERR src\r
2701 Modifies flags: ZF\r
2702 \r
2703 Verifies the specified segment selector is valid and is readable\r
2704 at the current privilege level. If the segment is readable,\r
2705 the Zero Flag is set, otherwise it is cleared.\r
2706 \r
2707 Clocks Size\r
2708 Operands 808x 286 386 486 Bytes\r
2709 \r
2710 reg16 - 14 10 11 3\r
2711 mem16 - 16 11 11 5\r
2712 \r
2713 \r
2714 VERW - Verify Write (286+ protected)\r
2715 \r
2716 Usage: VERW src\r
2717 Modifies flags: ZF\r
2718 \r
2719 Verifies the specified segment selector is valid and is ratable\r
2720 at the current privilege level. If the segment is writable,\r
2721 the Zero Flag is set, otherwise it is cleared.\r
2722 \r
2723 Clocks Size\r
2724 Operands 808x 286 386 486 Bytes\r
2725 \r
2726 reg16 - 14 15 11 3\r
2727 mem16 - 16 16 11 5\r
2729 \r
2730 Usage: WAIT\r
2731 FWAIT\r
2732 Modifies flags: None\r
2733 \r
2734 CPU enters wait state until the coprocessor signals it has finished\r
2735 its operation. This instruction is used to prevent the CPU from\r
2736 accessing memory that may be temporarily in use by the coprocessor.\r
2737 WAIT and FWAIT are identical.\r
2738 \r
2739 Clocks Size\r
2740 Operands 808x 286 386 486 Bytes\r
2741 \r
2742 none 4 3 6+ 1-3 1\r
2743 \r
2744 \r
2745 WBINVD - Write-Back and Invalidate Cache (486+)\r
2746 \r
2747 Usage: WBINVD\r
2748 Modifies flags: None\r
2749 \r
2750 Flushes internal cache, then signals the external cache to write\r
2751 back current data followed by a signal to flush the external cache.\r
2752 \r
2753 Clocks Size\r
2754 Operands 808x 286 386 486 Bytes\r
2755 \r
2756 none - - - 5 2\r
2757 \r
2758 \r
2759 XCHG - Exchange\r
2760 \r
2761 Usage: XCHG dest,src\r
2762 Modifies flags: None\r
2763 \r
2764 Exchanges contents of source and destination.\r
2765 \r
2766 Clocks Size\r
2767 Operands 808x 286 386 486 Bytes\r
2768 \r
2769 reg,reg 4 3 3 3 2\r
2770 mem,reg 17+EA 5 5 5 2-4 (W88=25+EA)\r
2771 reg,mem 17+EA 5 5 3 2-4 (W88=25+EA)\r
2772 accum,reg 3 3 3 3 1\r
2773 reg,accum 3 3 3 3 1\r
2774 \r
2775 \r
2776 XLAT/XLATB - Translate\r
2777 \r
2778 Usage: XLAT translation-table\r
2779 XLATB (masm 5.x)\r
2780 Modifies flags: None\r
2781 \r
2782 Replaces the byte in AL with byte from a user table addressed by\r
2783 BX. The original value of AL is the index into the translate table.\r
2784 The best way to discripe this is MOV AL,[BX+AL]\r
2785 \r
2786 Clocks Size\r
2787 Operands 808x 286 386 486 Bytes\r
2788 \r
2789 table offset 11 5 5 4 1\r
2791 \r
2792 Usage: XOR dest,src\r
2793 Modifies flags: CF OF PF SF ZF (AF undefined)\r
2794 \r
2795 Performs a bitwise exclusive OR of the operands and returns\r
2796 the result in the destination.\r
2797 \r
2798 Clocks Size\r
2799 Operands 808x 286 386 486 Bytes\r
2800 \r
2801 reg,reg 3 2 2 1 2\r
2802 mem,reg 16+EA 7 6 3 2-4 (W88=24+EA)\r
2803 reg,mem 9+EA 7 7 2 2-4 (W88=13+EA)\r
2804 reg,immed 4 3 2 1 3-4\r
2805 mem,immed 17+EA 7 7 3 3-6 (W88=25+EA)\r
2806 accum,immed 4 3 2 1 2-3\r
2807 \x1a