1 /* $NetBSD: if_egreg.h,v 1.3.66.1 2005/03/04 16:43:13 skrll Exp $ */
4 * Copyright (c) 1993 Dean Huxley (dean@fsa.ca)
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Dean Huxley.
18 * 4. The name of Dean Huxley may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * Register offsets from base.
36 #define EG_COMMAND 0x00
37 #define EG_STATUS 0x02
39 #define EG_CONTROL 0x06
42 * Host Control Register bits
43 * EG_CTL_ATTN - does a soft reset
44 * EG_CTL_FLSH - flushes the data register
45 * EG_CTL_RESET - does a hard reset
46 * EG_CTL_DMAE - Used with DIR bit, enables DMA transfers to/from data reg.
47 * EG_CTL_DIR - if clear then host -> adapter, if set then adapter -> host
48 * EG_CTL_TCEN - terminal count enable. enables host interrupt after DMA.
49 * EG_CTL_CMDE - command reg interrupt enable. (when it is written)
50 * EG_CTL_HSF1 - Host status flag 1
51 * EG_CTL_HSF2 - Host status flag 2
54 #define EG_CTL_ATTN 0x80
55 #define EG_CTL_FLSH 0x40
56 #define EG_CTL_RESET (EG_CTL_ATTN|EG_CTL_FLSH)
57 #define EG_CTL_DMAE 0x20
58 #define EG_CTL_DIR 0x10
59 #define EG_CTL_TCEN 0x08
60 #define EG_CTL_CMDE 0x04
61 #define EG_CTL_HSF2 0x02
62 #define EG_CTL_HSF1 0x01
65 * Host Status Register bits
66 * EG_STAT_HRDY - Data Register ready
67 * EG_STAT_HCRE - Host Command Register empty
68 * EG_STAT_ACRF - Adapter Command register full
69 * EG_STAT_DIR - Direction flag, 0 = host -> adapter, 1 = adapter -> host
70 * EG_STAT_DONE - DMA done
71 * EG_STAT_ASF1 - Adapter status flag 1
72 * EG_STAT_ASF2 - Adapter status flag 2
73 * EG_STAT_ASF3 - Adapter status flag 3
76 #define EG_STAT_HRDY 0x80
77 #define EG_STAT_HCRE 0x40
78 #define EG_STAT_ACRF 0x20
79 #define EG_STAT_DIR 0x10
80 #define EG_STAT_DONE 0x08
81 #define EG_STAT_ASF3 0x04
82 #define EG_STAT_ASF2 0x02
83 #define EG_STAT_ASF1 0x01
85 #define EG_PCB_NULL 0x00
86 #define EG_PCB_ACCEPT 0x01
87 #define EG_PCB_REJECT 0x02
88 #define EG_PCB_DONE 0x03
89 #define EG_PCB_STAT 0x03
91 #define EG_CMD_CONFIG82586 0x02
92 #define EG_CMD_GETEADDR 0x03
93 #define EG_CMD_RECVPACKET 0x08
94 #define EG_CMD_SENDPACKET 0x09
95 #define EG_CMD_GETSTATS 0x0a
96 #define EG_CMD_SETEADDR 0x10
97 #define EG_CMD_GETINFO 0x11
99 #define EG_RSP_CONFIG82586 0x32
100 #define EG_RSP_GETEADDR 0x33
101 #define EG_RSP_RECVPACKET 0x38
102 #define EG_RSP_SENDPACKET 0x39
103 #define EG_RSP_GETSTATS 0x3a
104 #define EG_RSP_SETEADDR 0x40
105 #define EG_RSP_GETINFO 0x41