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1 /* $NetBSD: memcreg.h,v 1.2 2002/03/24 23:37:43 bjh21 Exp $ */
2 /*-
3 * Copyright (c) 1997, 1998 Ben Harris
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28 /*
29 * memcreg.h - Acorn/ARM MEMC (Anna/VC2304/VL2304/MEMC1A/VL2304A/VL86C110/VY86C110)
30 * registers
31 */
33 #ifndef _ARM26_MEMCREG_H
34 #define _ARM26_MEMCREG_H
36 /*
37 * Accessing the MEMC is a little odd. It's not connected to the data
38 * bus, so the register and the new value are coded into an address.
39 * Thus, to set a register, OR together the register specifier and the
40 * new value, and write any word to the resultant address.
41 */
43 #define MEMC_WRITE(value) *(volatile u_int32_t *)value = 0
45 /*
46 * This information is mostly derived from:
47 * MEMC Datasheet
48 * Published by Acorn Computers Limited.
49 * Part no 0460,019
50 * Issue No 1.0
51 * 30 September 1986
52 * ISBN 1 85250 025 6
53 *
54 * Thanks must go to Jeanette Draper at ARM Ltd
55 * <jeanette.draper@arm.com> for finding it for me.
56 *
57 * Information on master/slave MEMCs came from Tony Duell
58 * <ard@p850ug1.demon.co.uk>, who has a copy of the MEMC1A data
59 * sheet and might photocopy it for me one day.
60 */
62 /* General memory-map layout provided by MEMC */
63 #define MEMC_PHYS_BASE ((void *)0x02000000)
64 #define MEMC_IO_BASE ((void *)0x03000000)
65 #define MEMC_VIDC_BASE ((void *)0x03400000)
66 #define MEMC_ROM_LOW_BASE ((void *)0x03400000)
67 #define MEMC_ROM_HIGH_BASE ((void *)0x03800000)
69 /*
70 * Each MEMC can manage 4Mb in 128 pages. The memory map only has
71 * space for 16Mb of physical RAM.
72 */
73 #define MEMC_MAX_PHYSPAGES 512
75 /*
76 * DMA address generator control registers. Addresses (>>4) go in
77 * bits 2-16, and must thus be in the bottom 512k of physical RAM.
78 */
79 #define MEMC_DMA_MAX 0x00080000
80 /* Video */
81 #define MEMC_VINIT 0x03600000
82 #define MEMC_VSTART 0x03620000
83 #define MEMC_VEND 0x03640000
84 /* Cursor */
85 #define MEMC_CINIT 0x03660000
86 /* Sound */
87 #define MEMC_SSTARTN 0x03680000
88 #define MEMC_SENDN 0x036A0000
89 #define MEMC_SPTR 0x036C0000
90 #define MEMC_SET_PTR(reg,addr) (reg | (addr >> 2))
92 /* MEMC control register (sec 6.5) */
93 #define MEMC_CONTROL 0x036E0000
95 /* Page size */
96 #define MEMC_CTL_PGSZ_MASK 0x0000000C
97 #define MEMC_CTL_PGSZ_4K 0x00000000
98 #define MEMC_CTL_PGSZ_8K 0x00000004
99 #define MEMC_CTL_PGSZ_16K 0x00000008
100 #define MEMC_CTL_PGSZ_32K 0x0000000C
102 /* ROM speeds; low and high banks, relative to RAM speed */
103 #define MEMC_CTL_LROMSPD_MASK 0x00000030
104 #define MEMC_CTL_LROMSPD_4N 0x00000000
105 #define MEMC_CTL_LROMSPD_3N 0x00000010
106 #define MEMC_CTL_LROMSPD_2N 0x00000020
107 #define MEMC_CTL_LROMSPD_PAGED 0x00000030
109 #define MEMC_CTL_HROMSPD_MASK 0x000000C0
110 #define MEMC_CTL_HROMSPD_4N 0x00000000
111 #define MEMC_CTL_HROMSPD_3N 0x00000040
112 #define MEMC_CTL_HROMSPD_2N 0x00000080
113 #define MEMC_CTL_HROMSPD_PAGED 0x000000C0
115 /* DRAM refresh control */
116 #define MEMC_CTL_RFRSH_MASK 0x00000300
117 #define MEMC_CTL_RFRSH_NONE 0x00000000
118 #define MEMC_CTL_RFRSH_FLYBACK 0x00000100
119 #define MEMC_CTL_RFRSH_CONTIN 0x00000300
121 /* Enable video DMA */
122 #define MEMC_CTL_VIDEODMA 0x00000400
123 /* Enable sound DMA */
124 #define MEMC_CTL_SOUNDDMA 0x00000800
125 /* Operating System Mode Select */
126 #define MEMC_CTL_OSMODE 0x00001000
128 /* Test mode */
129 /* This should never be set in a running system */
130 #define MEMC_CTL_TESTMODE 0x00002000
132 /*
133 * Address translation control
134 */
136 /* Absolute address of translation table */
137 #define MEMC_TRANS_BASE 0x03800000
139 /*
140 * MEMC translation entries are painful, and vary with the page size
141 * in use. Here, ppn is the physical page number, lpn is the logical
142 * page number and ppl is the page protection level.
143 *
144 * The list of transformations at the start of each macro is copied
145 * verbatim from the MEMC datasheet (Figure 5) with the exception of
146 * the entries for PPN[7] and PPN[8]. In dual-MEMC situations, PPN[7]
147 * selects between master and slave MEMCs, and is mapped to A[7] whatever
148 * the page size (though Acorn machines always use 32k pages with dual
149 * MEMCs). The Archimedes 540 can have up to 16Mb of RAM, and arranges
150 * this by having several address lines go through PALs on their way to the
151 * MEMCs. The upshot of this is that for the purposes of setting the
152 * translation tables, PPN[8] maps to A[12]. The A540 always has 32kb pages.
153 */
155 /* Page protection levels (data sheet section 6.6) */
156 /*-
157 * PPL
158 * Mode 00 01 10 11
159 * SVC R/W R/W R/W R/W
160 * OS R/W R/W R R
161 * User R/W R - -
162 */
164 #define MEMC_PPL_RDWR 0
165 #define MEMC_PPL_RDONLY 1
166 #define MEMC_PPL_NOACCESS 2
168 /*-
169 * 4k pages:
170 * PPN[7] -> A[7] (MEMC1a)
171 * PPN[6:0] -> A[6:0]
172 * PPL[1:0] -> A[9:8]
173 * LPN[12:11] -> A[11:10]
174 * LPN[10:0] -> A[22:12]
175 */
176 #define MEMC_TRANS_ENTRY_4K(ppn, lpn, ppl) \
177 (MEMC_TRANS_BASE | \
178 ((ppn) & 0xff) | \
179 ((ppl) & 0x3) << 8 | \
180 ((lpn) & 0x7ff) << 12 | \
181 ((lpn) & 0x1800) >> 1)
182 /*-
183 * 8k pages:
184 * PPN[7] -> A[7] (MEMC1a)
185 * PPN[6] -> A[0]
186 * PPN[5:0] -> A[6:1]
187 * PPL[1:0] -> A[9:8]
188 * LPN[11:10] -> A[11:10]
189 * LPN[9:0] -> A[22:13]
190 */
191 #define MEMC_TRANS_ENTRY_8K(ppn, lpn, ppl) \
192 (MEMC_TRANS_BASE | \
193 ((ppn) & 0x80) | \
194 ((ppn) & 0x40) >> 6 | \
195 ((ppn) & 0x3f) << 1 | \
196 ((ppl) & 0x3) << 8 | \
197 ((lpn) & 0xc00)) | \
198 ((lpn) & 0x3ff) << 13)
199 /*-
200 * 16k pages:
201 * PPN[7] -> A[7] (MEMC1a)
202 * PPN[6:5] -> A[1:0]
203 * PPN[4:0] -> A[6:2]
204 * PPL[1:0] -> A[9:8]
205 * LPN[10:9] -> A[11:10]
206 * LPN[9:0] -> A[22:14]
207 */
208 #define MEMC_TRANS_ENTRY_16K(ppn, lpn, ppl) \
209 (MEMC_TRANS_BASE | \
210 ((ppn) & 0x80) | \
211 ((ppn) & 0x60) >> 5 | \
212 ((ppn) & 0x1f) << 2 | \
213 ((ppl) & 0x3) << 8 | \
214 ((lpn) & 0x600) << 1 | \
215 ((lpn) & 0x1ff) << 14)
216 /*-
217 * 32k pages (here, the MEMC descends into madness...):
218 * PPN[8] -> A[12] (A540)
219 * PPN[7] -> A[7] (MEMC1a)
220 * PPN[6] -> A[1]
221 * PPN[5] -> A[2]
222 * PPN[4] -> A[0]
223 * PPN[3:0] -> A[6:3]
224 * PPL[1:0] -> A[9:8]
225 * LPN[9:8] -> A[11:10]
226 * LPN[7:0] -> A[22:15]
227 */
228 #define MEMC_TRANS_ENTRY_32K(ppn, lpn, ppl) \
229 (MEMC_TRANS_BASE | \
230 ((ppn) & 0x100) << 4 | \
231 ((ppn) & 0x80) | \
232 ((ppn) & 0x40) >> 5 | \
233 ((ppn) & 0x20) >> 3 | \
234 ((ppn) & 0x10) >> 4 | \
235 ((ppn) & 0x0f) << 3 | \
236 ((ppl) & 0x3) << 8 | \
237 ((lpn) & 0x300) << 2 | \
238 ((lpn) & 0x0ff) << 15)
240 #endif