sys/arch/amiga/dev/cbiisc.c

   1 /*      $NetBSD: cbiisc.c,v 1.28 2009/10/21 23:53:38 snj Exp $ */
   2
   3 /*
   4  * Copyright (c) 1997 Michael L. Hitch
   5  * Copyright (c) 1982, 1990 The Regents of the University of California.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. Neither the name of the University nor the names of its contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  *
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __KERNEL_RCSID(0, "$NetBSD: cbiisc.c,v 1.28 2009/10/21 23:53:38 snj Exp $");
  36
  37 #include <sys/types.h>
  38 #include <sys/param.h>
  39 #include <sys/systm.h>
  40 #include <sys/kernel.h>
  41 #include <sys/errno.h>
  42 #include <sys/ioctl.h>
  43 #include <sys/device.h>
  44 #include <sys/buf.h>
  45 #include <sys/proc.h>
  46 #include <sys/queue.h>
  47
  48 #include <uvm/uvm_extern.h>
  49
  50 #include <dev/scsipi/scsi_all.h>
  51 #include <dev/scsipi/scsipi_all.h>
  52 #include <dev/scsipi/scsiconf.h>
  53 #include <dev/scsipi/scsi_message.h>
  54
  55 #include <machine/cpu.h>
  56 #include <machine/param.h>
  57
  58 #include <dev/ic/ncr53c9xreg.h>
  59 #include <dev/ic/ncr53c9xvar.h>
  60
  61 #include <amiga/amiga/isr.h>
  62 #include <amiga/dev/cbiiscvar.h>
  63 #include <amiga/dev/zbusvar.h>
  64
  65 #ifdef __powerpc__
  66 #define badaddr(a)      badaddr_read(a, 2, NULL)
  67 #endif
  68
  69 int     cbiiscmatch(device_t, cfdata_t, void *);
  70 void    cbiiscattach(device_t, device_t, void *);
  71
  72 /* Linkup to the rest of the kernel */
  73 CFATTACH_DECL_NEW(cbiisc, sizeof(struct cbiisc_softc),
  74     cbiiscmatch, cbiiscattach, NULL, NULL);
  75
  76 /*
  77  * Functions and the switch for the MI code.
  78  */
  79 uint8_t cbiisc_read_reg(struct ncr53c9x_softc *, int);
  80 void    cbiisc_write_reg(struct ncr53c9x_softc *, int, uint8_t);
  81 int     cbiisc_dma_isintr(struct ncr53c9x_softc *);
  82 void    cbiisc_dma_reset(struct ncr53c9x_softc *);
  83 int     cbiisc_dma_intr(struct ncr53c9x_softc *);
  84 int     cbiisc_dma_setup(struct ncr53c9x_softc *, uint8_t **,
  85             size_t *, int, size_t *);
  86 void    cbiisc_dma_go(struct ncr53c9x_softc *);
  87 void    cbiisc_dma_stop(struct ncr53c9x_softc *);
  88 int     cbiisc_dma_isactive(struct ncr53c9x_softc *);
  89
  90 struct ncr53c9x_glue cbiisc_glue = {
  91         cbiisc_read_reg,
  92         cbiisc_write_reg,
  93         cbiisc_dma_isintr,
  94         cbiisc_dma_reset,
  95         cbiisc_dma_intr,
  96         cbiisc_dma_setup,
  97         cbiisc_dma_go,
  98         cbiisc_dma_stop,
  99         cbiisc_dma_isactive,
 100         NULL,
 101 };
 102
 103 /* Maximum DMA transfer length to reduce impact on high-speed serial input */
 104 u_long cbiisc_max_dma = 1024;
 105 extern int ser_open_speed;
 106
 107 u_long cbiisc_cnt_pio = 0;      /* number of PIO transfers */
 108 u_long cbiisc_cnt_dma = 0;      /* number of DMA transfers */
 109 u_long cbiisc_cnt_dma2 = 0;     /* number of DMA transfers broken up */
 110 u_long cbiisc_cnt_dma3 = 0;     /* number of pages combined */
 111
 112 #ifdef DEBUG
 113 struct {
 114         uint8_t hardbits;
 115         uint8_t status;
 116         uint8_t xx;
 117         uint8_t yy;
 118 } cbiisc_trace[128];
 119 int cbiisc_trace_ptr = 0;
 120 int cbiisc_trace_enable = 1;
 121 void cbiisc_dump(void);
 122 #endif
 123
 124 /*
 125  * if we are a Phase5 CyberSCSI II
 126  */
 127 int
 128 cbiiscmatch(device_t parent, cfdata_t cf, void *aux)
 129 {
 130         struct zbus_args *zap;
 131         volatile uint8_t *regs;
 132
 133         zap = aux;
 134         if (zap->manid != 0x2140 || zap->prodid != 25)
 135                 return 0;
 136         regs = &((volatile uint8_t *)zap->va)[0x1ff03];
 137         if (badaddr((void *)__UNVOLATILE(regs)))
 138                 return 0;
 139         regs[NCR_CFG1 * 4] = 0;
 140         regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
 141         delay(5);
 142         if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
 143                 return 0;
 144         return 1;
 145 }
 146
 147 /*
 148  * Attach this instance, and then all the sub-devices
 149  */
 150 void
 151 cbiiscattach(device_t parent, device_t self, void *aux)
 152 {
 153         struct cbiisc_softc *csc = device_private(self);
 154         struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x;
 155         struct zbus_args  *zap;
 156         extern u_long scsi_nosync;
 157         extern int shift_nosync;
 158         extern int ncr53c9x_debug;
 159
 160         /*
 161          * Set up the glue for MI code early; we use some of it here.
 162          */
 163         sc->sc_dev = self;
 164         sc->sc_glue = &cbiisc_glue;
 165
 166         /*
 167          * Save the regs
 168          */
 169         zap = aux;
 170         csc->sc_reg = &((volatile uint8_t *)zap->va)[0x1ff03];
 171         csc->sc_dmabase = &csc->sc_reg[0x80];
 172
 173         sc->sc_freq = 40;               /* Clocked at 40 MHz */
 174
 175         aprint_normal(": address %p", csc->sc_reg);
 176
 177         sc->sc_id = 7;
 178
 179         /*
 180          * It is necessary to try to load the 2nd config register here,
 181          * to find out what rev the FAS chip is, else the ncr53c9x_reset
 182          * will not set up the defaults correctly.
 183          */
 184         sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
 185         sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
 186         sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
 187         sc->sc_rev = NCR_VARIANT_FAS216;
 188
 189         /*
 190          * This is the value used to start sync negotiations
 191          * Note that the NCR register "SYNCTP" is programmed
 192          * in "clocks per byte", and has a minimum value of 4.
 193          * The SCSI period used in negotiation is one-fourth
 194          * of the time (in nanoseconds) needed to transfer one byte.
 195          * Since the chip's clock is given in MHz, we have the following
 196          * formula: 4 * period = (1000 / freq) * 4
 197          */
 198         sc->sc_minsync = 1000 / sc->sc_freq;
 199
 200         /*
 201          * get flags from -I argument and set cf_flags.
 202          * NOTE: low 8 bits are to disable disconnect, and the next
 203          *       8 bits are to disable sync.
 204          */
 205         device_cfdata(self)->cf_flags |= (scsi_nosync >> shift_nosync)
 206             & 0xffff;
 207         shift_nosync += 16;
 208
 209         /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
 210         ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
 211         shift_nosync += 16;
 212
 213 #if 1
 214         if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
 215                 sc->sc_minsync = 0;
 216 #endif
 217
 218         /* Really no limit, but since we want to fit into the TCR... */
 219         sc->sc_maxxfer = 64 * 1024;
 220
 221         /*
 222          * Configure interrupts.
 223          */
 224         csc->sc_isr.isr_intr = ncr53c9x_intr;
 225         csc->sc_isr.isr_arg  = sc;
 226         csc->sc_isr.isr_ipl  = 2;
 227         add_isr(&csc->sc_isr);
 228
 229         /*
 230          * Now try to attach all the sub-devices
 231          */
 232         sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
 233         sc->sc_adapter.adapt_minphys = minphys;
 234         ncr53c9x_attach(sc);
 235 }
 236
 237 /*
 238  * Glue functions.
 239  */
 240
 241 uint8_t
 242 cbiisc_read_reg(struct ncr53c9x_softc *sc, int reg)
 243 {
 244         struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
 245
 246         return csc->sc_reg[reg * 4];
 247 }
 248
 249 void
 250 cbiisc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)
 251 {
 252         struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
 253         uint8_t v = val;
 254
 255         csc->sc_reg[reg * 4] = v;
 256 #ifdef DEBUG
 257 if (cbiisc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ &&
 258   reg == NCR_CMD/* && csc->sc_active*/) {
 259   cbiisc_trace[(cbiisc_trace_ptr - 1) & 127].yy = v;
 260 /*  printf(" cmd %x", v);*/
 261 }
 262 #endif
 263 }
 264
 265 int
 266 cbiisc_dma_isintr(struct ncr53c9x_softc *sc)
 267 {
 268         struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
 269
 270         if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
 271                 return 0;
 272
 273         if (sc->sc_state == NCR_CONNECTED)
 274                 csc->sc_reg[0x40] = CBIISC_PB_LED;
 275         else
 276                 csc->sc_reg[0x40] = 0;
 277
 278 #ifdef DEBUG
 279 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbiisc_trace_enable) {
 280   cbiisc_trace[cbiisc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4];
 281   cbiisc_trace[cbiisc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4];
 282   cbiisc_trace[cbiisc_trace_ptr].yy = csc->sc_active;
 283   cbiisc_trace_ptr = (cbiisc_trace_ptr + 1) & 127;
 284 }
 285 #endif
 286         return 1;
 287 }
 288
 289 void
 290 cbiisc_dma_reset(struct ncr53c9x_softc *sc)
 291 {
 292         struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
 293
 294         csc->sc_active = 0;
 295 }
 296
 297 int
 298 cbiisc_dma_intr(struct ncr53c9x_softc *sc)
 299 {
 300         register struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
 301         register int    cnt;
 302
 303         NCR_DMA(("cbiisc_dma_intr: cnt %d int %x stat %x fifo %d ",
 304             csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
 305             csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
 306         if (csc->sc_active == 0) {
 307                 printf("cbiisc_intr--inactive DMA\n");
 308                 return -1;
 309         }
 310
 311         /* update sc_dmaaddr and sc_pdmalen */
 312         cnt = csc->sc_reg[NCR_TCL * 4];
 313         cnt += csc->sc_reg[NCR_TCM * 4] << 8;
 314         cnt += csc->sc_reg[NCR_TCH * 4] << 16;
 315         if (!csc->sc_datain) {
 316                 cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
 317                 csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
 318         }
 319         cnt = csc->sc_dmasize - cnt;    /* number of bytes transferred */
 320         NCR_DMA(("DMA xferred %d\n", cnt));
 321         if (csc->sc_xfr_align) {
 322                 memcpy(*csc->sc_dmaaddr, csc->sc_alignbuf, cnt);
 323                 csc->sc_xfr_align = 0;
 324         }
 325         *csc->sc_dmaaddr += cnt;
 326         *csc->sc_pdmalen -= cnt;
 327         csc->sc_active = 0;
 328         return 0;
 329 }
 330
 331 int
 332 cbiisc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len,
 333                  int datain, size_t *dmasize)
 334 {
 335         struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
 336         paddr_t pa;
 337         uint8_t *ptr;
 338         size_t xfer;
 339
 340         csc->sc_dmaaddr = addr;
 341         csc->sc_pdmalen = len;
 342         csc->sc_datain = datain;
 343         csc->sc_dmasize = *dmasize;
 344         /*
 345          * DMA can be nasty for high-speed serial input, so limit the
 346          * size of this DMA operation if the serial port is running at
 347          * a high speed (higher than 19200 for now - should be adjusted
 348          * based on CPU type and speed?).
 349          * XXX - add serial speed check XXX
 350          */
 351         if (ser_open_speed > 19200 && cbiisc_max_dma != 0 &&
 352             csc->sc_dmasize > cbiisc_max_dma)
 353                 csc->sc_dmasize = cbiisc_max_dma;
 354         ptr = *addr;                    /* Kernel virtual address */
 355         pa = kvtop(ptr);                /* Physical address of DMA */
 356         xfer = min(csc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1)));
 357         csc->sc_xfr_align = 0;
 358         /*
 359          * If output and unaligned, stuff odd byte into FIFO
 360          */
 361         if (datain == 0 && (int)ptr & 1) {
 362                 NCR_DMA(("cbiisc_dma_setup: align byte written to fifo\n"));
 363                 pa++;
 364                 xfer--;                 /* XXXX CHECK THIS !!!! XXXX */
 365                 csc->sc_reg[NCR_FIFO * 4] = *ptr++;
 366         }
 367         /*
 368          * If unaligned address, read unaligned bytes into alignment buffer
 369          */
 370         else if ((int)ptr & 1) {
 371                 pa = kvtop((void *)&csc->sc_alignbuf);
 372                 xfer = csc->sc_dmasize = min(xfer, sizeof(csc->sc_alignbuf));
 373                 NCR_DMA(("cbiisc_dma_setup: align read by %d bytes\n", xfer));
 374                 csc->sc_xfr_align = 1;
 375         }
 376 ++cbiisc_cnt_dma;               /* number of DMA operations */
 377
 378         while (xfer < csc->sc_dmasize) {
 379                 if ((pa + xfer) != kvtop(*addr + xfer))
 380                         break;
 381                 if ((csc->sc_dmasize - xfer) < PAGE_SIZE)
 382                         xfer = csc->sc_dmasize;
 383                 else
 384                         xfer += PAGE_SIZE;
 385 ++cbiisc_cnt_dma3;
 386         }
 387 if (xfer != *len)
 388   ++cbiisc_cnt_dma2;
 389
 390         csc->sc_dmasize = xfer;
 391         *dmasize = csc->sc_dmasize;
 392         csc->sc_pa = pa;
 393 #if defined(M68040) || defined(M68060)
 394         if (mmutype == MMU_68040) {
 395                 if (csc->sc_xfr_align) {
 396                         dma_cachectl(csc->sc_alignbuf,
 397                             sizeof(csc->sc_alignbuf));
 398                 }
 399                 else
 400                         dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize);
 401         }
 402 #endif
 403
 404         if (csc->sc_datain)
 405                 pa &= ~1;
 406         else
 407                 pa |= 1;
 408         csc->sc_dmabase[0] = (uint8_t)(pa >> 24);
 409         csc->sc_dmabase[4] = (uint8_t)(pa >> 16);
 410         csc->sc_dmabase[8] = (uint8_t)(pa >> 8);
 411         csc->sc_dmabase[12] = (uint8_t)(pa);
 412         csc->sc_active = 1;
 413         return 0;
 414 }
 415
 416 void
 417 cbiisc_dma_go(struct ncr53c9x_softc *sc)
 418 {
 419 }
 420
 421 void
 422 cbiisc_dma_stop(struct ncr53c9x_softc *sc)
 423 {
 424 }
 425
 426 int
 427 cbiisc_dma_isactive(struct ncr53c9x_softc *sc)
 428 {
 429         struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
 430
 431         return csc->sc_active;
 432 }
 433
 434 #ifdef DEBUG
 435 void
 436 cbiisc_dump(void)
 437 {
 438         int i;
 439
 440         i = cbiisc_trace_ptr;
 441         printf("cbiisc_trace dump: ptr %x\n", cbiisc_trace_ptr);
 442         do {
 443                 if (cbiisc_trace[i].hardbits == 0) {
 444                         i = (i + 1) & 127;
 445                         continue;
 446                 }
 447                 printf("%02x%02x%02x%02x(", cbiisc_trace[i].hardbits,
 448                     cbiisc_trace[i].status, cbiisc_trace[i].xx, cbiisc_trace[i].yy);
 449                 if (cbiisc_trace[i].status & NCRSTAT_INT)
 450                         printf("NCRINT/");
 451                 if (cbiisc_trace[i].status & NCRSTAT_TC)
 452                         printf("NCRTC/");
 453                 switch(cbiisc_trace[i].status & NCRSTAT_PHASE) {
 454                 case 0:
 455                         printf("dataout"); break;
 456                 case 1:
 457                         printf("datain"); break;
 458                 case 2:
 459                         printf("cmdout"); break;
 460                 case 3:
 461                         printf("status"); break;
 462                 case 6:
 463                         printf("msgout"); break;
 464                 case 7:
 465                         printf("msgin"); break;
 466                 default:
 467                         printf("phase%d?", cbiisc_trace[i].status & NCRSTAT_PHASE);
 468                 }
 469                 printf(") ");
 470                 i = (i + 1) & 127;
 471         } while (i != cbiisc_trace_ptr);
 472         printf("\n");
 473 }
 474 #endif