sys/arch/amiga/dev/grf_etreg.h

   1 /*      $NetBSD: grf_etreg.h,v 1.6 2005/12/24 20:06:47 perry Exp $      */
   2
   3 /*
   4  * Copyright (c) 1996 Tobias Abt
   5  * Copyright (c) 1995 Ezra Story
   6  * Copyright (c) 1995 Kari Mettinen
   7  * Copyright (c) 1994 Markus Wild
   8  * Copyright (c) 1994 Lutz Vieweg
   9  * All rights reserved.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  * 3. All advertising materials mentioning features or use of this software
  20  *    must display the following acknowledgement:
  21  *      This product includes software developed by Lutz Vieweg.
  22  * 4. The name of the author may not be used to endorse or promote products
  23  *    derived from this software without specific prior written permission
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  26  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  27  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  28  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  29  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  30  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  34  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #ifndef _GRF_ETREG_H
  38 #define _GRF_ETREG_H
  39
  40 /*
  41  * Written & Copyright by Kari Mettinen, Ezra Story.
  42  *
  43  * This is derived from Cirrus driver source
  44  */
  45
  46 /* Extension to grfvideo_mode to support text modes.
  47  * This can be passed to both text & gfx functions
  48  * without worry.  If gv.depth == 4, then the extended
  49  * fields for a text mode are present.
  50  */
  51 struct grfettext_mode {
  52         struct grfvideo_mode gv;
  53         unsigned short  fx;             /* font x dimension */
  54         unsigned short  fy;             /* font y dimension */
  55         unsigned short  cols;           /* screen dimensions */
  56         unsigned short  rows;
  57         void            *fdata;         /* font data */
  58         unsigned short  fdstart;
  59         unsigned short  fdend;
  60 };
  61
  62
  63 /* Tseng boards types, stored in ettype in grf_et.c.
  64  * used to decide how to handle Pass-through, etc.
  65  */
  66
  67 #define OMNIBUS         2181
  68 #define DOMINO          2167
  69 #define MERLIN          2117
  70
  71 /* VGA controller types */
  72 #define ET4000  0
  73 #define ETW32   1
  74
  75 /* DAC types */
  76 #define SIERRA11483     0       /* Sierra 11483 HiColor DAC */
  77 #define SIERRA15025     1       /* Sierra 15025 TrueColor DAC */
  78 #define MUSICDAC        2       /* MUSIC TrueColor DAC */
  79 #define MERLINDAC       3       /* Merlin's BrookTree TrueColor DAC */
  80 #define ATT20C491       4       /* AT&T 20c491 TrueColor DAC */
  81
  82 /* read VGA register */
  83 #define vgar(ba, reg) (*(((volatile unsigned char *)ba)+reg))
  84
  85 /* write VGA register */
  86 #define vgaw(ba, reg, val) \
  87         *(((volatile unsigned char *)ba)+reg) = ((unsigned char)val)
  88
  89 /*
  90  * defines for the used register addresses (mw)
  91  *
  92  * NOTE: there are some registers that have different addresses when
  93  *       in mono or color mode. We only support color mode, and thus
  94  *       some addresses won't work in mono-mode!
  95  *
  96  * General and VGA-registers taken from retina driver. Fixed a few
  97  * bugs in it. (SR and GR read address is Port + 1, NOT Port)
  98  *
  99  */
 100
 101 /* General Registers: */
 102 #define GREG_STATUS0_R          0x03C2
 103 #define GREG_STATUS1_R          0x03DA
 104 #define GREG_MISC_OUTPUT_R      0x03CC
 105 #define GREG_MISC_OUTPUT_W      0x03C2
 106 #define GREG_FEATURE_CONTROL_R  0x03CA
 107 #define GREG_FEATURE_CONTROL_W  0x03DA
 108 #define GREG_POS                0x0102
 109 #define GREG_HERCULESCOMPAT     0x03BF
 110 #define GREG_VIDEOSYSENABLE     0x03C3
 111 #define GREG_DISPMODECONTROL    0x03D8
 112 #define GREG_COLORSELECT        0x03D9
 113 #define GREG_ATNTMODECONTROL    0x03DE
 114 #define GREG_SEGMENTSELECT      0x03CD
 115 #define GREG_SEGMENTSELECT2     0x03CB
 116
 117 /* ETW32 special */
 118 #define W32mappedRegs 0xfff00
 119
 120 /* MMU */
 121 #define MMU_APERTURE0 0x80000
 122 #define MMU_APERTURE1 0xa0000
 123 #define MMU_APERTURE2 0xc0000
 124
 125 /* Accellerator */
 126
 127 /* Attribute Controller: */
 128 #define ACT_ADDRESS             0x03C0
 129 #define ACT_ADDRESS_R           0x03C1
 130 #define ACT_ADDRESS_W           0x03C0
 131 #define ACT_ADDRESS_RESET       0x03DA
 132 #define ACT_ID_PALETTE0         0x00
 133 #define ACT_ID_PALETTE1         0x01
 134 #define ACT_ID_PALETTE2         0x02
 135 #define ACT_ID_PALETTE3         0x03
 136 #define ACT_ID_PALETTE4         0x04
 137 #define ACT_ID_PALETTE5         0x05
 138 #define ACT_ID_PALETTE6         0x06
 139 #define ACT_ID_PALETTE7         0x07
 140 #define ACT_ID_PALETTE8         0x08
 141 #define ACT_ID_PALETTE9         0x09
 142 #define ACT_ID_PALETTE10        0x0A
 143 #define ACT_ID_PALETTE11        0x0B
 144 #define ACT_ID_PALETTE12        0x0C
 145 #define ACT_ID_PALETTE13        0x0D
 146 #define ACT_ID_PALETTE14        0x0E
 147 #define ACT_ID_PALETTE15        0x0F
 148 #define ACT_ID_ATTR_MODE_CNTL   0x10
 149 #define ACT_ID_OVERSCAN_COLOR   0x11
 150 #define ACT_ID_COLOR_PLANE_ENA  0x12
 151 #define ACT_ID_HOR_PEL_PANNING  0x13
 152 #define ACT_ID_COLOR_SELECT     0x14
 153 #define ACT_ID_MISCELLANEOUS    0x16
 154
 155 /* Graphics Controller: */
 156 #define GCT_ADDRESS             0x03CE
 157 #define GCT_ADDRESS_R           0x03CF
 158 #define GCT_ADDRESS_W           0x03CF
 159 #define GCT_ID_SET_RESET        0x00
 160 #define GCT_ID_ENABLE_SET_RESET 0x01
 161 #define GCT_ID_COLOR_COMPARE    0x02
 162 #define GCT_ID_DATA_ROTATE      0x03
 163 #define GCT_ID_READ_MAP_SELECT  0x04
 164 #define GCT_ID_GRAPHICS_MODE    0x05
 165 #define GCT_ID_MISC             0x06
 166 #define GCT_ID_COLOR_XCARE      0x07
 167 #define GCT_ID_BITMASK          0x08
 168
 169 /* Sequencer: */
 170 #define SEQ_ADDRESS             0x03C4
 171 #define SEQ_ADDRESS_R           0x03C5
 172 #define SEQ_ADDRESS_W           0x03C5
 173 #define SEQ_ID_RESET            0x00
 174 #define SEQ_ID_CLOCKING_MODE    0x01
 175 #define SEQ_ID_MAP_MASK         0x02
 176 #define SEQ_ID_CHAR_MAP_SELECT  0x03
 177 #define SEQ_ID_MEMORY_MODE      0x04
 178 #define SEQ_ID_STATE_CONTROL    0x06
 179 #define SEQ_ID_AUXILIARY_MODE   0x07
 180
 181 /* don't know about them right now...
 182 #define TEXT_PLANE_CHAR         0x01
 183 #define TEXT_PLANE_ATTR         0x02
 184 #define TEXT_PLANE_FONT         0x04
 185 */
 186
 187 /* CRT Controller: */
 188 #define CRT_ADDRESS             0x03D4
 189 #define CRT_ADDRESS_R           0x03D5
 190 #define CRT_ADDRESS_W           0x03D5
 191 #define CRT_ID_HOR_TOTAL        0x00
 192 #define CRT_ID_HOR_DISP_ENA_END 0x01
 193 #define CRT_ID_START_HOR_BLANK  0x02
 194 #define CRT_ID_END_HOR_BLANK    0x03
 195 #define CRT_ID_START_HOR_RETR   0x04
 196 #define CRT_ID_END_HOR_RETR     0x05
 197 #define CRT_ID_VER_TOTAL        0x06
 198 #define CRT_ID_OVERFLOW         0x07
 199 #define CRT_ID_PRESET_ROW_SCAN  0x08
 200 #define CRT_ID_MAX_ROW_ADDRESS  0x09
 201 #define CRT_ID_CURSOR_START     0x0A
 202 #define CRT_ID_CURSOR_END       0x0B
 203 #define CRT_ID_START_ADDR_HIGH  0x0C
 204 #define CRT_ID_START_ADDR_LOW   0x0D
 205 #define CRT_ID_CURSOR_LOC_HIGH  0x0E
 206 #define CRT_ID_CURSOR_LOC_LOW   0x0F
 207 #define CRT_ID_START_VER_RETR   0x10
 208 #define CRT_ID_END_VER_RETR     0x11
 209 #define CRT_ID_VER_DISP_ENA_END 0x12
 210 #define CRT_ID_OFFSET           0x13
 211 #define CRT_ID_UNDERLINE_LOC    0x14
 212 #define CRT_ID_START_VER_BLANK  0x15
 213 #define CRT_ID_END_VER_BLANK    0x16
 214 #define CRT_ID_MODE_CONTROL     0x17
 215 #define CRT_ID_LINE_COMPARE     0x18
 216
 217 #define CRT_ID_SEGMENT_COMP     0x30
 218 #define CRT_ID_GENERAL_PURPOSE  0x31
 219 #define CRT_ID_RASCAS_CONFIG    0x32
 220 #define CRT_ID_EXT_START        0x33
 221 #define CRT_ID_6845_COMPAT      0x34
 222 #define CRT_ID_OVERFLOW_HIGH    0x35
 223 #define CRT_ID_VIDEO_CONFIG1    0x36
 224 #define CRT_ID_VIDEO_CONFIG2    0x37
 225 #define CRT_ID_HOR_OVERFLOW     0x3f
 226
 227 /* IMAGE port */
 228 #define IMA_ADDRESS             0x217a
 229 #define IMA_ADDRESS_R           0x217b
 230 #define IMA_ADDRESS_W           0x217b
 231 #define IMA_STARTADDRESSLOW     0xf0
 232 #define IMA_STARTADDRESSMIDDLE  0xf1
 233 #define IMA_STARTADDRESSHIGH    0xf2
 234 #define IMA_TRANSFERLENGTHLOW   0xf3
 235 #define IMA_TRANSFERLENGTHHIGH  0xf4
 236 #define IMA_ROWOFFSETLOW        0xf5
 237 #define IMA_ROWOFFSETHIGH       0xf6
 238 #define IMA_PORTCONTROL         0xf7
 239
 240 /* Pass-through */
 241 #define PASS_ADDRESS            0x8000
 242 #define PASS_ADDRESS_W          0x8000
 243 #define PASS_ADDRESS_DOM        0xa000
 244 #define PASS_ADDRESS_DOMW       0xb000
 245
 246 /* Video DAC */
 247 #define VDAC_ADDRESS            0x03c8
 248 #define VDAC_ADDRESS_W          0x03c8
 249 #define VDAC_ADDRESS_R          0x03c7
 250 #define VDAC_STATE              0x03c7
 251 #define VDAC_DATA               0x03c9
 252 #define VDAC_MASK               0x03c6
 253 #define HDR                     0x03c6  /* Hidden DAC register, 4 reads to access */
 254
 255 #define VDAC_COMMAND            0x03c6
 256 #define VDAC_XINDEX             0x03c7
 257 #define VDAC_XDATA              0x03c8
 258
 259 #define MERLIN_VDAC_INDEX       0x01
 260 #define MERLIN_VDAC_COLORS      0x05
 261 #define MERLIN_VDAC_SPRITE      0x09
 262 #define MERLIN_VDAC_DATA        0x19
 263 #define MERLIN_SWITCH_REG       0x0401
 264
 265 #define WGfx(ba, idx, val) \
 266         do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0)
 267
 268 #define WSeq(ba, idx, val) \
 269         do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0)
 270
 271 #define WCrt(ba, idx, val) \
 272         do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0)
 273
 274 #define WIma(ba, idx, val) \
 275         do { vgaw(ba, IMA_ADDRESS, idx); vgaw(ba, IMA_ADDRESS_W , val); } while (0)
 276
 277 #define WAttr(ba, idx, val) \
 278         do { \
 279                 if(vgar(ba, GREG_STATUS1_R)); \
 280                 vgaw(ba, ACT_ADDRESS_W, idx); \
 281                 vgaw(ba, ACT_ADDRESS_W, val); \
 282         } while (0)
 283
 284 #define SetTextPlane(ba, m) \
 285         do { \
 286                 WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 ); \
 287                 WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3))); \
 288         } while (0)
 289
 290 #define setMerlinDACmode(ba, mode) \
 291         do { \
 292                 vgaw(ba, MERLIN_VDAC_DATA,  mode | \
 293                         (vgar(ba, MERLIN_VDAC_DATA) & 0x0f)); \
 294         } while (0)
 295
 296 /* Special wakeup/passthrough registers on graphics boards
 297  *
 298  * The methods have diverged a bit for each board, so
 299  * WPass(P) has been converted into a set of specific
 300  * inline functions.
 301  */
 302 static inline void RegWakeup(volatile void *ba) {
 303         extern int ettype;
 304
 305         switch (ettype) {
 306             case OMNIBUS:
 307                 vgaw(ba, PASS_ADDRESS_W, 0x00);
 308                 break;
 309             case DOMINO:
 310                 vgaw(ba, PASS_ADDRESS_DOM, 0x00);
 311                 break;
 312             case MERLIN:
 313                 break;
 314         }
 315         delay(200000);
 316 }
 317
 318
 319 static inline void RegOnpass(volatile void *ba) {
 320         extern int ettype;
 321         extern unsigned char pass_toggle;
 322         extern unsigned char Merlin_switch;
 323
 324         switch (ettype) {
 325             case OMNIBUS:
 326                 vgaw(ba, PASS_ADDRESS_W, 0x00);
 327                 break;
 328             case DOMINO:
 329                 vgaw(ba, PASS_ADDRESS_DOMW, 0x00);
 330                 break;
 331             case MERLIN:
 332                 Merlin_switch &= 0xfe;
 333                 vgaw(ba, MERLIN_SWITCH_REG, Merlin_switch);
 334                 break;
 335         }
 336         pass_toggle = 1;
 337         delay(200000);
 338 }
 339
 340
 341 static inline void RegOffpass(volatile void *ba) {
 342         extern int ettype;
 343         extern unsigned char pass_toggle;
 344         extern unsigned char Merlin_switch;
 345
 346         switch (ettype) {
 347             case OMNIBUS:
 348                 vgaw(ba, PASS_ADDRESS_W, 0x01);
 349                 break;
 350             case DOMINO:
 351                 vgaw(ba, PASS_ADDRESS_DOM, 0x00);
 352                 break;
 353             case MERLIN:
 354                 Merlin_switch |= 0x01;
 355                 vgaw(ba, MERLIN_SWITCH_REG, Merlin_switch);
 356                 break;
 357         }
 358         pass_toggle = 0;
 359         delay(200000);
 360 }
 361
 362 static inline unsigned char RAttr(volatile void *ba, short idx) {
 363         if(vgar(ba, GREG_STATUS1_R));
 364         vgaw(ba, ACT_ADDRESS_W, idx);
 365         return vgar (ba, ACT_ADDRESS_R);
 366 }
 367
 368 static inline unsigned char RSeq(volatile void *ba, short idx) {
 369         vgaw (ba, SEQ_ADDRESS, idx);
 370         return vgar (ba, SEQ_ADDRESS_R);
 371 }
 372
 373 static inline unsigned char RCrt(volatile void *ba, short idx) {
 374         vgaw (ba, CRT_ADDRESS, idx);
 375         return vgar (ba, CRT_ADDRESS_R);
 376 }
 377
 378 static inline unsigned char RGfx(volatile void *ba, short idx) {
 379         vgaw(ba, GCT_ADDRESS, idx);
 380         return vgar (ba, GCT_ADDRESS_R);
 381 }
 382
 383 int     et_mode(register struct grf_softc *gp, u_long cmd, void *arg,
 384                 u_long a2, int a3);
 385 int     et_load_mon(struct grf_softc *gp, struct grfettext_mode *gv);
 386 int     grfet_cnprobe(void);
 387 void    grfet_iteinit(struct grf_softc *gp);
 388
 389 #endif /* _GRF_ETREG_H */