Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / ata / ata.c
blobd91ab6286d05d832f7077993a5db4431e89ac14c
1 /* $NetBSD: ata.c,v 1.109 2009/11/12 19:20:08 dyoung Exp $ */
3 /*
4 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: ata.c,v 1.109 2009/11/12 19:20:08 dyoung Exp $");
30 #include "opt_ata.h"
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/device.h>
37 #include <sys/conf.h>
38 #include <sys/fcntl.h>
39 #include <sys/proc.h>
40 #include <sys/pool.h>
41 #include <sys/kthread.h>
42 #include <sys/errno.h>
43 #include <sys/ataio.h>
44 #include <sys/kmem.h>
45 #include <sys/simplelock.h>
46 #include <sys/intr.h>
47 #include <sys/bus.h>
48 #include <sys/once.h>
50 #include <dev/ata/ataconf.h>
51 #include <dev/ata/atareg.h>
52 #include <dev/ata/atavar.h>
53 #include <dev/ic/wdcvar.h> /* for PIOBM */
55 #include "locators.h"
57 #include "atapibus.h"
58 #include "ataraid.h"
60 #if NATARAID > 0
61 #include <dev/ata/ata_raidvar.h>
62 #endif
64 #define DEBUG_FUNCS 0x08
65 #define DEBUG_PROBE 0x10
66 #define DEBUG_DETACH 0x20
67 #define DEBUG_XFERS 0x40
68 #ifdef ATADEBUG
69 int atadebug_mask = 0;
70 #define ATADEBUG_PRINT(args, level) \
71 if (atadebug_mask & (level)) \
72 printf args
73 #else
74 #define ATADEBUG_PRINT(args, level)
75 #endif
77 static struct pool ata_xfer_pool;
80 * A queue of atabus instances, used to ensure the same bus probe order
81 * for a given hardware configuration at each boot.
83 struct atabus_initq_head atabus_initq_head =
84 TAILQ_HEAD_INITIALIZER(atabus_initq_head);
85 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER;
87 /* kernel thread probing devices on a atabus. Only one probing at once */
88 struct lwp *atabus_configlwp;
90 /*****************************************************************************
91 * ATA bus layer.
93 * ATA controllers attach an atabus instance, which handles probing the bus
94 * for drives, etc.
95 *****************************************************************************/
97 dev_type_open(atabusopen);
98 dev_type_close(atabusclose);
99 dev_type_ioctl(atabusioctl);
101 const struct cdevsw atabus_cdevsw = {
102 atabusopen, atabusclose, noread, nowrite, atabusioctl,
103 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER
106 extern struct cfdriver atabus_cd;
108 static void atabus_childdetached(device_t, device_t);
109 static bool atabus_resume(device_t, pmf_qual_t);
110 static bool atabus_suspend(device_t, pmf_qual_t);
111 static void atabusconfig_thread(void *);
114 * atabusprint:
116 * Autoconfiguration print routine used by ATA controllers when
117 * attaching an atabus instance.
120 atabusprint(void *aux, const char *pnp)
122 struct ata_channel *chan = aux;
124 if (pnp)
125 aprint_normal("atabus at %s", pnp);
126 aprint_normal(" channel %d", chan->ch_channel);
128 return (UNCONF);
132 * ataprint:
134 * Autoconfiguration print routine.
137 ataprint(void *aux, const char *pnp)
139 struct ata_device *adev = aux;
141 if (pnp)
142 aprint_normal("wd at %s", pnp);
143 aprint_normal(" drive %d", adev->adev_drv_data->drive);
145 return (UNCONF);
149 * ata_channel_attach:
151 * Common parts of attaching an atabus to an ATA controller channel.
153 void
154 ata_channel_attach(struct ata_channel *chp)
157 if (chp->ch_flags & ATACH_DISABLED)
158 return;
160 /* XXX callout_destroy */
161 callout_init(&chp->ch_callout, 0);
163 TAILQ_INIT(&chp->ch_queue->queue_xfer);
164 chp->ch_queue->queue_freeze = 0;
165 chp->ch_queue->queue_flags = 0;
166 chp->ch_queue->active_xfer = NULL;
168 chp->atabus = config_found_ia(chp->ch_atac->atac_dev, "ata", chp,
169 atabusprint);
172 static void
173 atabusconfig(struct atabus_softc *atabus_sc)
175 struct ata_channel *chp = atabus_sc->sc_chan;
176 struct atac_softc *atac = chp->ch_atac;
177 struct atabus_initq *atabus_initq = NULL;
178 int i, s, error;
180 /* we are in the atabus's thread context */
181 s = splbio();
182 chp->ch_flags |= ATACH_TH_RUN;
183 splx(s);
185 /* Probe for the drives. */
186 /* XXX for SATA devices we will power up all drives at once */
187 (*atac->atac_probe)(chp);
189 ATADEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n",
190 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags),
191 DEBUG_PROBE);
193 /* next operations will occurs in a separate thread */
194 s = splbio();
195 chp->ch_flags &= ~ATACH_TH_RUN;
196 splx(s);
198 /* Make sure the devices probe in atabus order to avoid jitter. */
199 simple_lock(&atabus_interlock);
200 while(1) {
201 atabus_initq = TAILQ_FIRST(&atabus_initq_head);
202 if (atabus_initq->atabus_sc == atabus_sc)
203 break;
204 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0,
205 &atabus_interlock);
207 simple_unlock(&atabus_interlock);
209 /* If no drives, abort here */
210 for (i = 0; i < chp->ch_ndrive; i++)
211 if ((chp->ch_drive[i].drive_flags & DRIVE) != 0)
212 break;
213 if (i == chp->ch_ndrive)
214 goto out;
216 /* Shortcut in case we've been shutdown */
217 if (chp->ch_flags & ATACH_SHUTDOWN)
218 goto out;
221 if ((error = kthread_create(PRI_NONE, 0, NULL, atabusconfig_thread,
222 atabus_sc, &atabus_configlwp,
223 "%scnf", device_xname(atac->atac_dev))) != 0)
224 aprint_error_dev(atac->atac_dev,
225 "unable to create config thread: error %d\n", error);
226 return;
228 out:
229 simple_lock(&atabus_interlock);
230 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq);
231 simple_unlock(&atabus_interlock);
233 free(atabus_initq, M_DEVBUF);
234 wakeup(&atabus_initq_head);
236 ata_delref(chp);
238 config_pending_decr();
242 * atabus_configthread: finish attach of atabus's childrens, in a separate
243 * kernel thread.
245 static void
246 atabusconfig_thread(void *arg)
248 struct atabus_softc *atabus_sc = arg;
249 struct ata_channel *chp = atabus_sc->sc_chan;
250 struct atac_softc *atac = chp->ch_atac;
251 int i, s;
252 struct atabus_initq *atabus_initq = NULL;
254 simple_lock(&atabus_interlock);
255 atabus_initq = TAILQ_FIRST(&atabus_initq_head);
256 simple_unlock(&atabus_interlock);
257 KASSERT(atabus_initq->atabus_sc == atabus_sc);
259 * Attach an ATAPI bus, if needed.
261 for (i = 0; i < chp->ch_ndrive; i++) {
262 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) {
263 #if NATAPIBUS > 0
264 (*atac->atac_atapibus_attach)(atabus_sc);
265 #else
267 * Fake the autoconfig "not configured" message
269 aprint_normal("atapibus at %s not configured\n",
270 device_xname(atac->atac_dev));
271 chp->atapibus = NULL;
272 s = splbio();
273 for (i = 0; i < chp->ch_ndrive; i++)
274 chp->ch_drive[i].drive_flags &= ~DRIVE_ATAPI;
275 splx(s);
276 #endif
277 break;
281 for (i = 0; i < chp->ch_ndrive; i++) {
282 struct ata_device adev;
283 if ((chp->ch_drive[i].drive_flags &
284 (DRIVE_ATA | DRIVE_OLD)) == 0) {
285 continue;
287 memset(&adev, 0, sizeof(struct ata_device));
288 adev.adev_bustype = atac->atac_bustype_ata;
289 adev.adev_channel = chp->ch_channel;
290 adev.adev_openings = 1;
291 adev.adev_drv_data = &chp->ch_drive[i];
292 chp->ata_drives[i] = config_found_ia(atabus_sc->sc_dev,
293 "ata_hl", &adev, ataprint);
294 if (chp->ata_drives[i] != NULL)
295 ata_probe_caps(&chp->ch_drive[i]);
296 else {
297 s = splbio();
298 chp->ch_drive[i].drive_flags &=
299 ~(DRIVE_ATA | DRIVE_OLD);
300 splx(s);
304 /* now that we know the drives, the controller can set its modes */
305 if (atac->atac_set_modes) {
306 (*atac->atac_set_modes)(chp);
307 ata_print_modes(chp);
309 #if NATARAID > 0
310 if (atac->atac_cap & ATAC_CAP_RAID)
311 for (i = 0; i < chp->ch_ndrive; i++)
312 if (chp->ata_drives[i] != NULL)
313 ata_raid_check_component(chp->ata_drives[i]);
314 #endif /* NATARAID > 0 */
317 * reset drive_flags for unattached devices, reset state for attached
318 * ones
320 s = splbio();
321 for (i = 0; i < chp->ch_ndrive; i++) {
322 if (chp->ch_drive[i].drv_softc == NULL)
323 chp->ch_drive[i].drive_flags = 0;
324 else
325 chp->ch_drive[i].state = 0;
327 splx(s);
329 simple_lock(&atabus_interlock);
330 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq);
331 simple_unlock(&atabus_interlock);
333 free(atabus_initq, M_DEVBUF);
334 wakeup(&atabus_initq_head);
336 ata_delref(chp);
338 config_pending_decr();
339 kthread_exit(0);
343 * atabus_thread:
345 * Worker thread for the ATA bus.
347 static void
348 atabus_thread(void *arg)
350 struct atabus_softc *sc = arg;
351 struct ata_channel *chp = sc->sc_chan;
352 struct ata_xfer *xfer;
353 int i, s;
355 s = splbio();
356 chp->ch_flags |= ATACH_TH_RUN;
359 * Probe the drives. Reset all flags to 0 to indicate to controllers
360 * that can re-probe that all drives must be probed..
362 * Note: ch_ndrive may be changed during the probe.
364 for (i = 0; i < ATA_MAXDRIVES; i++)
365 chp->ch_drive[i].drive_flags = 0;
366 splx(s);
368 atabusconfig(sc);
370 s = splbio();
371 for (;;) {
372 if ((chp->ch_flags & (ATACH_TH_RESET | ATACH_SHUTDOWN)) == 0 &&
373 (chp->ch_queue->active_xfer == NULL ||
374 chp->ch_queue->queue_freeze == 0)) {
375 chp->ch_flags &= ~ATACH_TH_RUN;
376 (void) tsleep(&chp->ch_thread, PRIBIO, "atath", 0);
377 chp->ch_flags |= ATACH_TH_RUN;
379 if (chp->ch_flags & ATACH_SHUTDOWN) {
380 break;
382 if (chp->ch_flags & ATACH_TH_RESET) {
384 * ata_reset_channel() will freeze 2 times, so
385 * unfreeze one time. Not a problem as we're at splbio
387 chp->ch_queue->queue_freeze--;
388 ata_reset_channel(chp, AT_WAIT | chp->ch_reset_flags);
389 } else if (chp->ch_queue->active_xfer != NULL &&
390 chp->ch_queue->queue_freeze == 1) {
392 * Caller has bumped queue_freeze, decrease it.
394 chp->ch_queue->queue_freeze--;
395 xfer = chp->ch_queue->active_xfer;
396 KASSERT(xfer != NULL);
397 (*xfer->c_start)(xfer->c_chp, xfer);
398 } else if (chp->ch_queue->queue_freeze > 1)
399 panic("ata_thread: queue_freeze");
401 splx(s);
402 chp->ch_thread = NULL;
403 wakeup(&chp->ch_flags);
404 kthread_exit(0);
408 * atabus_match:
410 * Autoconfiguration match routine.
412 static int
413 atabus_match(device_t parent, cfdata_t cf, void *aux)
415 struct ata_channel *chp = aux;
417 if (chp == NULL)
418 return (0);
420 if (cf->cf_loc[ATACF_CHANNEL] != chp->ch_channel &&
421 cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT)
422 return (0);
424 return (1);
427 static int
428 atabus_xferpool_init(void)
431 pool_init(&ata_xfer_pool, sizeof(struct ata_xfer), 0, 0, 0, "ataspl",
432 NULL, IPL_BIO);
433 return 0;
437 * atabus_attach:
439 * Autoconfiguration attach routine.
441 static void
442 atabus_attach(device_t parent, device_t self, void *aux)
444 struct atabus_softc *sc = device_private(self);
445 struct ata_channel *chp = aux;
446 struct atabus_initq *initq;
447 static ONCE_DECL(poolinit_ctrl);
448 int error;
450 sc->sc_chan = chp;
452 aprint_normal("\n");
453 aprint_naive("\n");
455 sc->sc_dev = self;
457 if (ata_addref(chp))
458 return;
460 RUN_ONCE(&poolinit_ctrl, atabus_xferpool_init);
462 initq = malloc(sizeof(*initq), M_DEVBUF, M_WAITOK);
463 initq->atabus_sc = sc;
464 TAILQ_INSERT_TAIL(&atabus_initq_head, initq, atabus_initq);
465 config_pending_incr();
467 if ((error = kthread_create(PRI_NONE, 0, NULL, atabus_thread, sc,
468 &chp->ch_thread, "%s", device_xname(self))) != 0)
469 aprint_error_dev(self,
470 "unable to create kernel thread: error %d\n", error);
472 if (!pmf_device_register(self, atabus_suspend, atabus_resume))
473 aprint_error_dev(self, "couldn't establish power handler\n");
477 * atabus_detach:
479 * Autoconfiguration detach routine.
481 static int
482 atabus_detach(device_t self, int flags)
484 struct atabus_softc *sc = device_private(self);
485 struct ata_channel *chp = sc->sc_chan;
486 device_t dev = NULL;
487 int s, i, error = 0;
489 /* Shutdown the channel. */
490 s = splbio(); /* XXX ALSO NEED AN INTERLOCK HERE. */
491 chp->ch_flags |= ATACH_SHUTDOWN;
492 splx(s);
494 wakeup(&chp->ch_thread);
496 while (chp->ch_thread != NULL)
497 (void) tsleep(&chp->ch_flags, PRIBIO, "atadown", 0);
501 * Detach atapibus and its children.
503 if ((dev = chp->atapibus) != NULL) {
504 ATADEBUG_PRINT(("atabus_detach: %s: detaching %s\n",
505 device_xname(self), device_xname(dev)), DEBUG_DETACH);
507 error = config_detach(dev, flags);
508 if (error)
509 goto out;
510 KASSERT(chp->atapibus == NULL);
514 * Detach our other children.
516 for (i = 0; i < chp->ch_ndrive; i++) {
517 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI)
518 continue;
519 if ((dev = chp->ata_drives[i]) != NULL) {
520 ATADEBUG_PRINT(("%s.%d: %s: detaching %s\n", __func__,
521 __LINE__, device_xname(self), device_xname(dev)),
522 DEBUG_DETACH);
523 KASSERT(chp->ch_drive[i].drv_softc ==
524 chp->ata_drives[i]);
525 error = config_detach(dev, flags);
526 if (error)
527 goto out;
528 KASSERT(chp->ata_drives[i] == NULL);
532 out:
533 #ifdef ATADEBUG
534 if (dev != NULL && error != 0)
535 ATADEBUG_PRINT(("%s: %s: error %d detaching %s\n", __func__,
536 device_xname(self), error, device_xname(dev)),
537 DEBUG_DETACH);
538 #endif /* ATADEBUG */
540 return (error);
543 void
544 atabus_childdetached(device_t self, device_t child)
546 bool found = false;
547 struct atabus_softc *sc = device_private(self);
548 struct ata_channel *chp = sc->sc_chan;
549 int i;
552 * atapibus detached.
554 if (child == chp->atapibus) {
555 chp->atapibus = NULL;
556 found = true;
560 * Detach our other children.
562 for (i = 0; i < chp->ch_ndrive; i++) {
563 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI)
564 continue;
565 if (child == chp->ata_drives[i]) {
566 KASSERT(chp->ata_drives[i] ==
567 chp->ch_drive[i].drv_softc);
568 chp->ata_drives[i] = NULL;
569 chp->ch_drive[i].drv_softc = NULL;
570 chp->ch_drive[i].drive_flags = 0;
571 found = true;
575 if (!found)
576 panic("%s: unknown child %p", device_xname(self),
577 (const void *)child);
580 CFATTACH_DECL3_NEW(atabus, sizeof(struct atabus_softc),
581 atabus_match, atabus_attach, atabus_detach, NULL, NULL,
582 atabus_childdetached, DVF_DETACH_SHUTDOWN);
584 /*****************************************************************************
585 * Common ATA bus operations.
586 *****************************************************************************/
588 /* Get the disk's parameters */
590 ata_get_params(struct ata_drive_datas *drvp, u_int8_t flags,
591 struct ataparams *prms)
593 struct ata_command ata_c;
594 struct ata_channel *chp = drvp->chnl_softc;
595 struct atac_softc *atac = chp->ch_atac;
596 char *tb;
597 int i, rv;
598 u_int16_t *p;
600 ATADEBUG_PRINT(("%s\n", __func__), DEBUG_FUNCS);
602 tb = kmem_zalloc(DEV_BSIZE, KM_SLEEP);
603 memset(prms, 0, sizeof(struct ataparams));
604 memset(&ata_c, 0, sizeof(struct ata_command));
606 if (drvp->drive_flags & DRIVE_ATA) {
607 ata_c.r_command = WDCC_IDENTIFY;
608 ata_c.r_st_bmask = WDCS_DRDY;
609 ata_c.r_st_pmask = WDCS_DRQ;
610 ata_c.timeout = 3000; /* 3s */
611 } else if (drvp->drive_flags & DRIVE_ATAPI) {
612 ata_c.r_command = ATAPI_IDENTIFY_DEVICE;
613 ata_c.r_st_bmask = 0;
614 ata_c.r_st_pmask = WDCS_DRQ;
615 ata_c.timeout = 10000; /* 10s */
616 } else {
617 ATADEBUG_PRINT(("ata_get_parms: no disks\n"),
618 DEBUG_FUNCS|DEBUG_PROBE);
619 rv = CMD_ERR;
620 goto out;
622 ata_c.flags = AT_READ | flags;
623 ata_c.data = tb;
624 ata_c.bcount = DEV_BSIZE;
625 if ((*atac->atac_bustype_ata->ata_exec_command)(drvp,
626 &ata_c) != ATACMD_COMPLETE) {
627 ATADEBUG_PRINT(("ata_get_parms: wdc_exec_command failed\n"),
628 DEBUG_FUNCS|DEBUG_PROBE);
629 rv = CMD_AGAIN;
630 goto out;
632 if (ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) {
633 ATADEBUG_PRINT(("ata_get_parms: ata_c.flags=0x%x\n",
634 ata_c.flags), DEBUG_FUNCS|DEBUG_PROBE);
635 rv = CMD_ERR;
636 goto out;
638 /* if we didn't read any data something is wrong */
639 if ((ata_c.flags & AT_XFDONE) == 0) {
640 rv = CMD_ERR;
641 goto out;
644 /* Read in parameter block. */
645 memcpy(prms, tb, sizeof(struct ataparams));
648 * Shuffle string byte order.
649 * ATAPI NEC, Mitsumi and Pioneer drives and
650 * old ATA TDK CompactFlash cards
651 * have different byte order.
653 #if BYTE_ORDER == BIG_ENDIAN
654 # define M(n) prms->atap_model[(n) ^ 1]
655 #else
656 # define M(n) prms->atap_model[n]
657 #endif
658 if (
659 #if BYTE_ORDER == BIG_ENDIAN
661 #endif
662 ((drvp->drive_flags & DRIVE_ATAPI) ?
663 ((M(0) == 'N' && M(1) == 'E') ||
664 (M(0) == 'F' && M(1) == 'X') ||
665 (M(0) == 'P' && M(1) == 'i')) :
666 ((M(0) == 'T' && M(1) == 'D' && M(2) == 'K')))) {
667 rv = CMD_OK;
668 goto out;
670 #undef M
671 for (i = 0; i < sizeof(prms->atap_model); i += 2) {
672 p = (u_int16_t *)(prms->atap_model + i);
673 *p = bswap16(*p);
675 for (i = 0; i < sizeof(prms->atap_serial); i += 2) {
676 p = (u_int16_t *)(prms->atap_serial + i);
677 *p = bswap16(*p);
679 for (i = 0; i < sizeof(prms->atap_revision); i += 2) {
680 p = (u_int16_t *)(prms->atap_revision + i);
681 *p = bswap16(*p);
684 rv = CMD_OK;
685 out:
686 kmem_free(tb, DEV_BSIZE);
687 return rv;
691 ata_set_mode(struct ata_drive_datas *drvp, u_int8_t mode, u_int8_t flags)
693 struct ata_command ata_c;
694 struct ata_channel *chp = drvp->chnl_softc;
695 struct atac_softc *atac = chp->ch_atac;
697 ATADEBUG_PRINT(("ata_set_mode=0x%x\n", mode), DEBUG_FUNCS);
698 memset(&ata_c, 0, sizeof(struct ata_command));
700 ata_c.r_command = SET_FEATURES;
701 ata_c.r_st_bmask = 0;
702 ata_c.r_st_pmask = 0;
703 ata_c.r_features = WDSF_SET_MODE;
704 ata_c.r_count = mode;
705 ata_c.flags = flags;
706 ata_c.timeout = 1000; /* 1s */
707 if ((*atac->atac_bustype_ata->ata_exec_command)(drvp,
708 &ata_c) != ATACMD_COMPLETE)
709 return CMD_AGAIN;
710 if (ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) {
711 return CMD_ERR;
713 return CMD_OK;
716 #if NATA_DMA
717 void
718 ata_dmaerr(struct ata_drive_datas *drvp, int flags)
721 * Downgrade decision: if we get NERRS_MAX in NXFER.
722 * We start with n_dmaerrs set to NERRS_MAX-1 so that the
723 * first error within the first NXFER ops will immediatly trigger
724 * a downgrade.
725 * If we got an error and n_xfers is bigger than NXFER reset counters.
727 drvp->n_dmaerrs++;
728 if (drvp->n_dmaerrs >= NERRS_MAX && drvp->n_xfers <= NXFER) {
729 ata_downgrade_mode(drvp, flags);
730 drvp->n_dmaerrs = NERRS_MAX-1;
731 drvp->n_xfers = 0;
732 return;
734 if (drvp->n_xfers > NXFER) {
735 drvp->n_dmaerrs = 1; /* just got an error */
736 drvp->n_xfers = 1; /* restart counting from this error */
739 #endif /* NATA_DMA */
742 * freeze the queue and wait for the controller to be idle. Caller has to
743 * unfreeze/restart the queue
745 void
746 ata_queue_idle(struct ata_queue *queue)
748 int s = splbio();
749 queue->queue_freeze++;
750 while (queue->active_xfer != NULL) {
751 queue->queue_flags |= QF_IDLE_WAIT;
752 tsleep(&queue->queue_flags, PRIBIO, "qidl", 0);
754 splx(s);
758 * Add a command to the queue and start controller.
760 * MUST BE CALLED AT splbio()!
762 void
763 ata_exec_xfer(struct ata_channel *chp, struct ata_xfer *xfer)
766 ATADEBUG_PRINT(("ata_exec_xfer %p channel %d drive %d\n", xfer,
767 chp->ch_channel, xfer->c_drive), DEBUG_XFERS);
769 /* complete xfer setup */
770 xfer->c_chp = chp;
772 /* insert at the end of command list */
773 TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain);
774 ATADEBUG_PRINT(("atastart from ata_exec_xfer, flags 0x%x\n",
775 chp->ch_flags), DEBUG_XFERS);
777 * if polling and can sleep, wait for the xfer to be at head of queue
779 if ((xfer->c_flags & (C_POLL | C_WAIT)) == (C_POLL | C_WAIT)) {
780 while (chp->ch_queue->active_xfer != NULL ||
781 TAILQ_FIRST(&chp->ch_queue->queue_xfer) != xfer) {
782 xfer->c_flags |= C_WAITACT;
783 tsleep(xfer, PRIBIO, "ataact", 0);
784 xfer->c_flags &= ~C_WAITACT;
785 if (xfer->c_flags & C_FREE) {
786 ata_free_xfer(chp, xfer);
787 return;
791 atastart(chp);
795 * Start I/O on a controller, for the given channel.
796 * The first xfer may be not for our channel if the channel queues
797 * are shared.
799 * MUST BE CALLED AT splbio()!
801 void
802 atastart(struct ata_channel *chp)
804 struct atac_softc *atac = chp->ch_atac;
805 struct ata_xfer *xfer;
807 #ifdef ATA_DEBUG
808 int spl1, spl2;
810 spl1 = splbio();
811 spl2 = splbio();
812 if (spl2 != spl1) {
813 printf("atastart: not at splbio()\n");
814 panic("atastart");
816 splx(spl2);
817 splx(spl1);
818 #endif /* ATA_DEBUG */
820 /* is there a xfer ? */
821 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL)
822 return;
824 /* adjust chp, in case we have a shared queue */
825 chp = xfer->c_chp;
827 if (chp->ch_queue->active_xfer != NULL) {
828 return; /* channel aleady active */
830 if (__predict_false(chp->ch_queue->queue_freeze > 0)) {
831 if (chp->ch_queue->queue_flags & QF_IDLE_WAIT) {
832 chp->ch_queue->queue_flags &= ~QF_IDLE_WAIT;
833 wakeup(&chp->ch_queue->queue_flags);
835 return; /* queue frozen */
838 * if someone is waiting for the command to be active, wake it up
839 * and let it process the command
841 if (xfer->c_flags & C_WAITACT) {
842 ATADEBUG_PRINT(("atastart: xfer %p channel %d drive %d "
843 "wait active\n", xfer, chp->ch_channel, xfer->c_drive),
844 DEBUG_XFERS);
845 wakeup(xfer);
846 return;
848 #ifdef DIAGNOSTIC
849 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0)
850 panic("atastart: channel waiting for irq");
851 #endif
852 if (atac->atac_claim_hw)
853 if (!(*atac->atac_claim_hw)(chp, 0))
854 return;
856 ATADEBUG_PRINT(("atastart: xfer %p channel %d drive %d\n", xfer,
857 chp->ch_channel, xfer->c_drive), DEBUG_XFERS);
858 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) {
859 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET;
860 chp->ch_drive[xfer->c_drive].state = 0;
862 chp->ch_queue->active_xfer = xfer;
863 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain);
865 if (atac->atac_cap & ATAC_CAP_NOIRQ)
866 KASSERT(xfer->c_flags & C_POLL);
868 xfer->c_start(chp, xfer);
871 struct ata_xfer *
872 ata_get_xfer(int flags)
874 struct ata_xfer *xfer;
875 int s;
877 s = splbio();
878 xfer = pool_get(&ata_xfer_pool,
879 ((flags & ATAXF_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK));
880 splx(s);
881 if (xfer != NULL) {
882 memset(xfer, 0, sizeof(struct ata_xfer));
884 return xfer;
887 void
888 ata_free_xfer(struct ata_channel *chp, struct ata_xfer *xfer)
890 struct atac_softc *atac = chp->ch_atac;
891 int s;
893 if (xfer->c_flags & C_WAITACT) {
894 /* Someone is waiting for this xfer, so we can't free now */
895 xfer->c_flags |= C_FREE;
896 wakeup(xfer);
897 return;
900 #if NATA_PIOBM /* XXX wdc dependent code */
901 if (xfer->c_flags & C_PIOBM) {
902 struct wdc_softc *wdc = CHAN_TO_WDC(chp);
904 /* finish the busmastering PIO */
905 (*wdc->piobm_done)(wdc->dma_arg,
906 chp->ch_channel, xfer->c_drive);
907 chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_PIOBM_WAIT | ATACH_IRQ_WAIT);
909 #endif
911 if (atac->atac_free_hw)
912 (*atac->atac_free_hw)(chp);
913 s = splbio();
914 pool_put(&ata_xfer_pool, xfer);
915 splx(s);
919 * Kill off all pending xfers for a ata_channel.
921 * Must be called at splbio().
923 void
924 ata_kill_pending(struct ata_drive_datas *drvp)
926 struct ata_channel *chp = drvp->chnl_softc;
927 struct ata_xfer *xfer, *next_xfer;
928 int s = splbio();
930 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
931 xfer != NULL; xfer = next_xfer) {
932 next_xfer = TAILQ_NEXT(xfer, c_xferchain);
933 if (xfer->c_chp != chp || xfer->c_drive != drvp->drive)
934 continue;
935 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain);
936 (*xfer->c_kill_xfer)(chp, xfer, KILL_GONE);
939 while ((xfer = chp->ch_queue->active_xfer) != NULL) {
940 if (xfer->c_chp == chp && xfer->c_drive == drvp->drive) {
941 drvp->drive_flags |= DRIVE_WAITDRAIN;
942 (void) tsleep(&chp->ch_queue->active_xfer,
943 PRIBIO, "atdrn", 0);
944 } else {
945 /* no more xfer for us */
946 break;
949 splx(s);
953 * ata_reset_channel:
955 * Reset and ATA channel.
957 * MUST BE CALLED AT splbio()!
959 void
960 ata_reset_channel(struct ata_channel *chp, int flags)
962 struct atac_softc *atac = chp->ch_atac;
963 int drive;
965 #ifdef ATA_DEBUG
966 int spl1, spl2;
968 spl1 = splbio();
969 spl2 = splbio();
970 if (spl2 != spl1) {
971 printf("ata_reset_channel: not at splbio()\n");
972 panic("ata_reset_channel");
974 splx(spl2);
975 splx(spl1);
976 #endif /* ATA_DEBUG */
978 chp->ch_queue->queue_freeze++;
981 * If we can poll or wait it's OK, otherwise wake up the
982 * kernel thread to do it for us.
984 ATADEBUG_PRINT(("ata_reset_channel flags 0x%x ch_flags 0x%x\n",
985 flags, chp->ch_flags), DEBUG_FUNCS | DEBUG_XFERS);
986 if ((flags & (AT_POLL | AT_WAIT)) == 0) {
987 if (chp->ch_flags & ATACH_TH_RESET) {
988 /* No need to schedule a reset more than one time. */
989 chp->ch_queue->queue_freeze--;
990 return;
992 chp->ch_flags |= ATACH_TH_RESET;
993 chp->ch_reset_flags = flags & (AT_RST_EMERG | AT_RST_NOCMD);
994 wakeup(&chp->ch_thread);
995 return;
998 (*atac->atac_bustype_ata->ata_reset_channel)(chp, flags);
1000 for (drive = 0; drive < chp->ch_ndrive; drive++)
1001 chp->ch_drive[drive].state = 0;
1003 chp->ch_flags &= ~ATACH_TH_RESET;
1004 if ((flags & AT_RST_EMERG) == 0) {
1005 chp->ch_queue->queue_freeze--;
1006 atastart(chp);
1007 } else {
1008 /* make sure that we can use polled commands */
1009 TAILQ_INIT(&chp->ch_queue->queue_xfer);
1010 chp->ch_queue->queue_freeze = 0;
1011 chp->ch_queue->active_xfer = NULL;
1016 ata_addref(struct ata_channel *chp)
1018 struct atac_softc *atac = chp->ch_atac;
1019 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic;
1020 int s, error = 0;
1022 s = splbio();
1023 if (adapt->adapt_refcnt++ == 0 &&
1024 adapt->adapt_enable != NULL) {
1025 error = (*adapt->adapt_enable)(atac->atac_dev, 1);
1026 if (error)
1027 adapt->adapt_refcnt--;
1029 splx(s);
1030 return (error);
1033 void
1034 ata_delref(struct ata_channel *chp)
1036 struct atac_softc *atac = chp->ch_atac;
1037 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic;
1038 int s;
1040 s = splbio();
1041 if (adapt->adapt_refcnt-- == 1 &&
1042 adapt->adapt_enable != NULL)
1043 (void) (*adapt->adapt_enable)(atac->atac_dev, 0);
1044 splx(s);
1047 void
1048 ata_print_modes(struct ata_channel *chp)
1050 struct atac_softc *atac = chp->ch_atac;
1051 int drive;
1052 struct ata_drive_datas *drvp;
1054 for (drive = 0; drive < chp->ch_ndrive; drive++) {
1055 drvp = &chp->ch_drive[drive];
1056 if ((drvp->drive_flags & DRIVE) == 0 || drvp->drv_softc == NULL)
1057 continue;
1058 aprint_verbose("%s(%s:%d:%d): using PIO mode %d",
1059 device_xname(drvp->drv_softc),
1060 device_xname(atac->atac_dev),
1061 chp->ch_channel, drvp->drive, drvp->PIO_mode);
1062 #if NATA_DMA
1063 if (drvp->drive_flags & DRIVE_DMA)
1064 aprint_verbose(", DMA mode %d", drvp->DMA_mode);
1065 #if NATA_UDMA
1066 if (drvp->drive_flags & DRIVE_UDMA) {
1067 aprint_verbose(", Ultra-DMA mode %d", drvp->UDMA_mode);
1068 if (drvp->UDMA_mode == 2)
1069 aprint_verbose(" (Ultra/33)");
1070 else if (drvp->UDMA_mode == 4)
1071 aprint_verbose(" (Ultra/66)");
1072 else if (drvp->UDMA_mode == 5)
1073 aprint_verbose(" (Ultra/100)");
1074 else if (drvp->UDMA_mode == 6)
1075 aprint_verbose(" (Ultra/133)");
1077 #endif /* NATA_UDMA */
1078 #endif /* NATA_DMA */
1079 #if NATA_DMA || NATA_PIOBM
1080 if (0
1081 #if NATA_DMA
1082 || (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA))
1083 #endif
1084 #if NATA_PIOBM
1085 /* PIOBM capable controllers use DMA for PIO commands */
1086 || (atac->atac_cap & ATAC_CAP_PIOBM)
1087 #endif
1089 aprint_verbose(" (using DMA)");
1090 #endif /* NATA_DMA || NATA_PIOBM */
1091 aprint_verbose("\n");
1095 #if NATA_DMA
1097 * downgrade the transfer mode of a drive after an error. return 1 if
1098 * downgrade was possible, 0 otherwise.
1100 * MUST BE CALLED AT splbio()!
1103 ata_downgrade_mode(struct ata_drive_datas *drvp, int flags)
1105 struct ata_channel *chp = drvp->chnl_softc;
1106 struct atac_softc *atac = chp->ch_atac;
1107 device_t drv_dev = drvp->drv_softc;
1108 int cf_flags = device_cfdata(drv_dev)->cf_flags;
1110 /* if drive or controller don't know its mode, we can't do much */
1111 if ((drvp->drive_flags & DRIVE_MODE) == 0 ||
1112 (atac->atac_set_modes == NULL))
1113 return 0;
1114 /* current drive mode was set by a config flag, let it this way */
1115 if ((cf_flags & ATA_CONFIG_PIO_SET) ||
1116 (cf_flags & ATA_CONFIG_DMA_SET) ||
1117 (cf_flags & ATA_CONFIG_UDMA_SET))
1118 return 0;
1120 #if NATA_UDMA
1122 * If we were using Ultra-DMA mode, downgrade to the next lower mode.
1124 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) {
1125 drvp->UDMA_mode--;
1126 aprint_error_dev(drv_dev,
1127 "transfer error, downgrading to Ultra-DMA mode %d\n",
1128 drvp->UDMA_mode);
1130 #endif
1133 * If we were using ultra-DMA, don't downgrade to multiword DMA.
1135 else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) {
1136 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA);
1137 drvp->PIO_mode = drvp->PIO_cap;
1138 aprint_error_dev(drv_dev,
1139 "transfer error, downgrading to PIO mode %d\n",
1140 drvp->PIO_mode);
1141 } else /* already using PIO, can't downgrade */
1142 return 0;
1144 (*atac->atac_set_modes)(chp);
1145 ata_print_modes(chp);
1146 /* reset the channel, which will schedule all drives for setup */
1147 ata_reset_channel(chp, flags | AT_RST_NOCMD);
1148 return 1;
1150 #endif /* NATA_DMA */
1153 * Probe drive's capabilities, for use by the controller later
1154 * Assumes drvp points to an existing drive.
1156 void
1157 ata_probe_caps(struct ata_drive_datas *drvp)
1159 struct ataparams params, params2;
1160 struct ata_channel *chp = drvp->chnl_softc;
1161 struct atac_softc *atac = chp->ch_atac;
1162 device_t drv_dev = drvp->drv_softc;
1163 int i, printed, s;
1164 const char *sep = "";
1165 int cf_flags;
1167 if (ata_get_params(drvp, AT_WAIT, &params) != CMD_OK) {
1168 /* IDENTIFY failed. Can't tell more about the device */
1169 return;
1171 if ((atac->atac_cap & (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) ==
1172 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) {
1174 * Controller claims 16 and 32 bit transfers.
1175 * Re-do an IDENTIFY with 32-bit transfers,
1176 * and compare results.
1178 s = splbio();
1179 drvp->drive_flags |= DRIVE_CAP32;
1180 splx(s);
1181 ata_get_params(drvp, AT_WAIT, &params2);
1182 if (memcmp(&params, &params2, sizeof(struct ataparams)) != 0) {
1183 /* Not good. fall back to 16bits */
1184 s = splbio();
1185 drvp->drive_flags &= ~DRIVE_CAP32;
1186 splx(s);
1187 } else {
1188 aprint_verbose_dev(drv_dev, "32-bit data port\n");
1191 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */
1192 if (params.atap_ata_major > 0x01 &&
1193 params.atap_ata_major != 0xffff) {
1194 for (i = 14; i > 0; i--) {
1195 if (params.atap_ata_major & (1 << i)) {
1196 aprint_verbose_dev(drv_dev,
1197 "ATA version %d\n", i);
1198 drvp->ata_vers = i;
1199 break;
1203 #endif
1205 /* An ATAPI device is at last PIO mode 3 */
1206 if (drvp->drive_flags & DRIVE_ATAPI)
1207 drvp->PIO_mode = 3;
1210 * It's not in the specs, but it seems that some drive
1211 * returns 0xffff in atap_extensions when this field is invalid
1213 if (params.atap_extensions != 0xffff &&
1214 (params.atap_extensions & WDC_EXT_MODES)) {
1215 printed = 0;
1217 * XXX some drives report something wrong here (they claim to
1218 * support PIO mode 8 !). As mode is coded on 3 bits in
1219 * SET FEATURE, limit it to 7 (so limit i to 4).
1220 * If higher mode than 7 is found, abort.
1222 for (i = 7; i >= 0; i--) {
1223 if ((params.atap_piomode_supp & (1 << i)) == 0)
1224 continue;
1225 if (i > 4)
1226 return;
1228 * See if mode is accepted.
1229 * If the controller can't set its PIO mode,
1230 * assume the defaults are good, so don't try
1231 * to set it
1233 if (atac->atac_set_modes)
1235 * It's OK to pool here, it's fast enouth
1236 * to not bother waiting for interrupt
1238 if (ata_set_mode(drvp, 0x08 | (i + 3),
1239 AT_WAIT) != CMD_OK)
1240 continue;
1241 if (!printed) {
1242 aprint_verbose_dev(drv_dev,
1243 "drive supports PIO mode %d", i + 3);
1244 sep = ",";
1245 printed = 1;
1248 * If controller's driver can't set its PIO mode,
1249 * get the highter one for the drive.
1251 if (atac->atac_set_modes == NULL ||
1252 atac->atac_pio_cap >= i + 3) {
1253 drvp->PIO_mode = i + 3;
1254 drvp->PIO_cap = i + 3;
1255 break;
1258 if (!printed) {
1260 * We didn't find a valid PIO mode.
1261 * Assume the values returned for DMA are buggy too
1263 return;
1265 s = splbio();
1266 drvp->drive_flags |= DRIVE_MODE;
1267 splx(s);
1268 printed = 0;
1269 for (i = 7; i >= 0; i--) {
1270 if ((params.atap_dmamode_supp & (1 << i)) == 0)
1271 continue;
1272 #if NATA_DMA
1273 if ((atac->atac_cap & ATAC_CAP_DMA) &&
1274 atac->atac_set_modes != NULL)
1275 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT)
1276 != CMD_OK)
1277 continue;
1278 #endif
1279 if (!printed) {
1280 aprint_verbose("%s DMA mode %d", sep, i);
1281 sep = ",";
1282 printed = 1;
1284 #if NATA_DMA
1285 if (atac->atac_cap & ATAC_CAP_DMA) {
1286 if (atac->atac_set_modes != NULL &&
1287 atac->atac_dma_cap < i)
1288 continue;
1289 drvp->DMA_mode = i;
1290 drvp->DMA_cap = i;
1291 s = splbio();
1292 drvp->drive_flags |= DRIVE_DMA;
1293 splx(s);
1295 #endif
1296 break;
1298 if (params.atap_extensions & WDC_EXT_UDMA_MODES) {
1299 printed = 0;
1300 for (i = 7; i >= 0; i--) {
1301 if ((params.atap_udmamode_supp & (1 << i))
1302 == 0)
1303 continue;
1304 #if NATA_UDMA
1305 if (atac->atac_set_modes != NULL &&
1306 (atac->atac_cap & ATAC_CAP_UDMA))
1307 if (ata_set_mode(drvp, 0x40 | i,
1308 AT_WAIT) != CMD_OK)
1309 continue;
1310 #endif
1311 if (!printed) {
1312 aprint_verbose("%s Ultra-DMA mode %d",
1313 sep, i);
1314 if (i == 2)
1315 aprint_verbose(" (Ultra/33)");
1316 else if (i == 4)
1317 aprint_verbose(" (Ultra/66)");
1318 else if (i == 5)
1319 aprint_verbose(" (Ultra/100)");
1320 else if (i == 6)
1321 aprint_verbose(" (Ultra/133)");
1322 sep = ",";
1323 printed = 1;
1325 #if NATA_UDMA
1326 if (atac->atac_cap & ATAC_CAP_UDMA) {
1327 if (atac->atac_set_modes != NULL &&
1328 atac->atac_udma_cap < i)
1329 continue;
1330 drvp->UDMA_mode = i;
1331 drvp->UDMA_cap = i;
1332 s = splbio();
1333 drvp->drive_flags |= DRIVE_UDMA;
1334 splx(s);
1336 #endif
1337 break;
1340 aprint_verbose("\n");
1343 s = splbio();
1344 drvp->drive_flags &= ~DRIVE_NOSTREAM;
1345 if (drvp->drive_flags & DRIVE_ATAPI) {
1346 if (atac->atac_cap & ATAC_CAP_ATAPI_NOSTREAM)
1347 drvp->drive_flags |= DRIVE_NOSTREAM;
1348 } else {
1349 if (atac->atac_cap & ATAC_CAP_ATA_NOSTREAM)
1350 drvp->drive_flags |= DRIVE_NOSTREAM;
1352 splx(s);
1354 /* Try to guess ATA version here, if it didn't get reported */
1355 if (drvp->ata_vers == 0) {
1356 #if NATA_UDMA
1357 if (drvp->drive_flags & DRIVE_UDMA)
1358 drvp->ata_vers = 4; /* should be at last ATA-4 */
1359 else
1360 #endif
1361 if (drvp->PIO_cap > 2)
1362 drvp->ata_vers = 2; /* should be at last ATA-2 */
1364 cf_flags = device_cfdata(drv_dev)->cf_flags;
1365 if (cf_flags & ATA_CONFIG_PIO_SET) {
1366 s = splbio();
1367 drvp->PIO_mode =
1368 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF;
1369 drvp->drive_flags |= DRIVE_MODE;
1370 splx(s);
1372 #if NATA_DMA
1373 if ((atac->atac_cap & ATAC_CAP_DMA) == 0) {
1374 /* don't care about DMA modes */
1375 return;
1377 if (cf_flags & ATA_CONFIG_DMA_SET) {
1378 s = splbio();
1379 if ((cf_flags & ATA_CONFIG_DMA_MODES) ==
1380 ATA_CONFIG_DMA_DISABLE) {
1381 drvp->drive_flags &= ~DRIVE_DMA;
1382 } else {
1383 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >>
1384 ATA_CONFIG_DMA_OFF;
1385 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE;
1387 splx(s);
1389 #if NATA_UDMA
1390 if ((atac->atac_cap & ATAC_CAP_UDMA) == 0) {
1391 /* don't care about UDMA modes */
1392 return;
1394 if (cf_flags & ATA_CONFIG_UDMA_SET) {
1395 s = splbio();
1396 if ((cf_flags & ATA_CONFIG_UDMA_MODES) ==
1397 ATA_CONFIG_UDMA_DISABLE) {
1398 drvp->drive_flags &= ~DRIVE_UDMA;
1399 } else {
1400 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >>
1401 ATA_CONFIG_UDMA_OFF;
1402 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE;
1404 splx(s);
1406 #endif /* NATA_UDMA */
1407 #endif /* NATA_DMA */
1410 /* management of the /dev/atabus* devices */
1412 atabusopen(dev_t dev, int flag, int fmt,
1413 struct lwp *l)
1415 struct atabus_softc *sc;
1416 int error;
1418 sc = device_lookup_private(&atabus_cd, minor(dev));
1419 if (sc == NULL)
1420 return (ENXIO);
1422 if (sc->sc_flags & ATABUSCF_OPEN)
1423 return (EBUSY);
1425 if ((error = ata_addref(sc->sc_chan)) != 0)
1426 return (error);
1428 sc->sc_flags |= ATABUSCF_OPEN;
1430 return (0);
1435 atabusclose(dev_t dev, int flag, int fmt,
1436 struct lwp *l)
1438 struct atabus_softc *sc =
1439 device_lookup_private(&atabus_cd, minor(dev));
1441 ata_delref(sc->sc_chan);
1443 sc->sc_flags &= ~ATABUSCF_OPEN;
1445 return (0);
1449 atabusioctl(dev_t dev, u_long cmd, void *addr, int flag,
1450 struct lwp *l)
1452 struct atabus_softc *sc =
1453 device_lookup_private(&atabus_cd, minor(dev));
1454 struct ata_channel *chp = sc->sc_chan;
1455 int min_drive, max_drive, drive;
1456 int error;
1457 int s;
1460 * Enforce write permission for ioctls that change the
1461 * state of the bus. Host adapter specific ioctls must
1462 * be checked by the adapter driver.
1464 switch (cmd) {
1465 case ATABUSIOSCAN:
1466 case ATABUSIODETACH:
1467 case ATABUSIORESET:
1468 if ((flag & FWRITE) == 0)
1469 return (EBADF);
1472 switch (cmd) {
1473 case ATABUSIORESET:
1474 s = splbio();
1475 ata_reset_channel(sc->sc_chan, AT_WAIT | AT_POLL);
1476 splx(s);
1477 error = 0;
1478 break;
1479 case ATABUSIOSCAN:
1481 #if 0
1482 struct atabusioscan_args *a=
1483 (struct atabusioscan_args *)addr;
1484 #endif
1485 if ((chp->ch_drive[0].drive_flags & DRIVE_OLD) ||
1486 (chp->ch_drive[1].drive_flags & DRIVE_OLD))
1487 return (EOPNOTSUPP);
1488 return (EOPNOTSUPP);
1490 case ATABUSIODETACH:
1492 struct atabusioscan_args *a=
1493 (struct atabusioscan_args *)addr;
1494 if ((chp->ch_drive[0].drive_flags & DRIVE_OLD) ||
1495 (chp->ch_drive[1].drive_flags & DRIVE_OLD))
1496 return (EOPNOTSUPP);
1497 switch (a->at_dev) {
1498 case -1:
1499 min_drive = 0;
1500 max_drive = 1;
1501 break;
1502 case 0:
1503 case 1:
1504 min_drive = max_drive = a->at_dev;
1505 break;
1506 default:
1507 return (EINVAL);
1509 for (drive = min_drive; drive <= max_drive; drive++) {
1510 if (chp->ch_drive[drive].drv_softc != NULL) {
1511 error = config_detach(
1512 chp->ch_drive[drive].drv_softc, 0);
1513 if (error)
1514 return (error);
1515 KASSERT(chp->ch_drive[drive].drv_softc == NULL);
1518 error = 0;
1519 break;
1521 default:
1522 error = ENOTTY;
1524 return (error);
1527 static bool
1528 atabus_suspend(device_t dv, pmf_qual_t qual)
1530 struct atabus_softc *sc = device_private(dv);
1531 struct ata_channel *chp = sc->sc_chan;
1533 ata_queue_idle(chp->ch_queue);
1535 return true;
1538 static bool
1539 atabus_resume(device_t dv, pmf_qual_t qual)
1541 struct atabus_softc *sc = device_private(dv);
1542 struct ata_channel *chp = sc->sc_chan;
1543 int s;
1546 * XXX joerg: with wdc, the first channel unfreezes the controler.
1547 * Move this the reset and queue idling into wdc.
1549 s = splbio();
1550 if (chp->ch_queue->queue_freeze == 0) {
1551 splx(s);
1552 return true;
1554 KASSERT(chp->ch_queue->queue_freeze > 0);
1555 /* unfreeze the queue and reset drives */
1556 chp->ch_queue->queue_freeze--;
1557 ata_reset_channel(chp, AT_WAIT);
1558 splx(s);
1560 return true;