Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / cardbus / siisata_cardbus.c
blob413d43f5af110385990bf0f2322a7f0a96dc1124
1 /* $NetBSD: siisata_cardbus.c,v 1.2 2009/10/19 18:41:12 bouyer Exp $ */
2 /* Id: siisata_pci.c,v 1.11 2008/05/21 16:20:11 jakllsch Exp */
4 /*
5 * Copyright (c) 2006 Manuel Bouyer.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 /*-
30 * Copyright (c) 2007, 2008 Jonathan A. Kollasch.
31 * All rights reserved.
33 * Redistribution and use in source and binary forms, with or without
34 * modification, are permitted provided that the following conditions
35 * are met:
36 * 1. Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * 2. Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in the
40 * documentation and/or other materials provided with the distribution.
42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
43 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
44 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
45 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
46 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
47 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
48 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
49 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
50 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
51 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 #include <sys/cdefs.h>
58 #include <sys/types.h>
59 #include <sys/malloc.h>
60 #include <sys/param.h>
61 #include <sys/kernel.h>
62 #include <sys/systm.h>
64 #include <uvm/uvm_extern.h>
66 #include <dev/cardbus/cardbusvar.h>
67 #include <dev/pci/pcidevs.h>
68 #include <dev/ic/siisatavar.h>
70 #define cardbus_devinfo pci_devinfo
72 struct siisata_cardbus_softc {
73 struct siisata_softc si_sc;
74 cardbus_chipset_tag_t sc_cc;
75 cardbus_function_tag_t sc_cf;
76 cardbus_devfunc_t sc_ct;
78 bus_size_t sc_grsize;
79 bus_size_t sc_prsize;
80 void *sc_ih;
83 static int siisata_cardbus_match(device_t, cfdata_t, void *);
84 static void siisata_cardbus_attach(device_t, device_t, void *);
85 static int siisata_cardbus_detach(device_t, int);
86 static bool siisata_cardbus_resume(device_t, pmf_qual_t);
88 static const struct siisata_cardbus_product {
89 cardbus_vendor_id_t scp_vendor;
90 cardbus_product_id_t scp_product;
91 int scp_ports;
92 int scp_chip;
94 } siisata_cardbus_products[] = {
96 PCI_VENDOR_CMDTECH, PCI_PRODUCT_CMDTECH_3124,
97 4, 3124
100 0, 0,
101 0, 0
105 CFATTACH_DECL_NEW(siisata_cardbus, sizeof(struct siisata_cardbus_softc),
106 siisata_cardbus_match, siisata_cardbus_attach, siisata_cardbus_detach,
107 NULL);
109 static const struct siisata_cardbus_product *
110 siisata_cardbus_lookup(const struct cardbus_attach_args *ca)
112 const struct siisata_cardbus_product *scp;
114 for (scp = siisata_cardbus_products; scp->scp_ports > 0; scp++) {
115 if (CARDBUS_VENDOR(ca->ca_id) == scp->scp_vendor &&
116 CARDBUS_PRODUCT(ca->ca_id) == scp->scp_product)
117 return scp;
119 return NULL;
122 static int
123 siisata_cardbus_match(device_t parent, cfdata_t match, void *aux)
125 struct cardbus_attach_args *ca = aux;
127 if (siisata_cardbus_lookup(ca) != NULL)
128 return 3;
130 return 0;
133 static void
134 siisata_cardbus_attach(device_t parent, device_t self, void *aux)
136 struct cardbus_attach_args *ca = aux;
137 struct cardbus_softc *cbsc = device_private(parent);
138 struct siisata_cardbus_softc *csc = device_private(self);
139 struct siisata_softc *sc = &csc->si_sc;
140 cardbus_devfunc_t ct = ca->ca_ct;
141 cardbus_chipset_tag_t cc = ct->ct_cc;
142 cardbus_function_tag_t cf = ct->ct_cf;
143 cardbusreg_t csr;
144 const struct siisata_cardbus_product *scp;
145 bus_space_tag_t memt;
146 bus_space_handle_t memh;
147 bus_addr_t base;
148 bus_size_t grsize, prsize;
149 uint32_t gcreg;
150 char devinfo[256];
152 sc->sc_atac.atac_dev = self;
154 csc->sc_cc = cc;
155 csc->sc_cf = cf;
156 csc->sc_ct = ct;
158 cardbus_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo));
159 aprint_naive(": SATA-II HBA\n");
160 aprint_normal(": %s\n", devinfo);
163 * XXXX
164 * Our BAR0/BAR1 type is 64bit Memory. Cardbus_mapreg_map() don't
165 * support 64bit Memory. We map ourself...
167 /* map bar0 */
169 #define SIISATA_BAR0_SIZE 128
170 grsize = SIISATA_BAR0_SIZE;
171 csr =
172 cardbus_conf_read(cc, cf, ca->ca_tag, SIISATA_CARDBUS_BAR0);
173 base = PCI_MAPREG_MEM_ADDR(csr);
174 memt = cbsc->sc_memt;
175 if ((*cf->cardbus_space_alloc)(cc, cbsc->sc_rbus_memt, base,
176 grsize, grsize - 1, grsize, 0, &base, &memh)) {
177 aprint_error(
178 "%s: unable to map device global registers\n",
179 SIISATANAME(sc));
180 return;
182 cardbus_conf_write(cc, cf, ca->ca_tag, SIISATA_CARDBUS_BAR0,
183 base);
185 sc->sc_grt = memt;
186 sc->sc_grh = memh;
187 csc->sc_grsize = grsize;
189 /* map bar1 */
191 #define SIISATA_BAR1_SIZE (32 * 1024)
192 prsize = SIISATA_BAR1_SIZE;
193 base = PCI_MAPREG_MEM_ADDR(cardbus_conf_read(cc, cf, ca->ca_tag,
194 SIISATA_CARDBUS_BAR1));
195 memt = cbsc->sc_memt;
196 if ((*cf->cardbus_space_alloc)(cc, cbsc->sc_rbus_memt, base,
197 prsize, prsize - 1, prsize, 0, &base, &memh)) {
198 cardbus_conf_write(cc, cf, ca->ca_tag,
199 SIISATA_CARDBUS_BAR0, 0);
200 (*cf->cardbus_space_free)(cc, cbsc->sc_rbus_memt,
201 sc->sc_grh, grsize);
202 aprint_error(
203 "%s: unable to map device port registers\n",
204 SIISATANAME(sc));
205 return;
207 cardbus_conf_write(cc, cf, ca->ca_tag, SIISATA_CARDBUS_BAR1,
208 base);
210 sc->sc_prt = memt;
211 sc->sc_prh = memh;
212 csc->sc_prsize = prsize;
214 sc->sc_dmat = ca->ca_dmat;
216 /* map interrupt */
217 csc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_BIO,
218 siisata_intr, sc);
219 if (csc->sc_ih == NULL) {
220 cardbus_conf_write(cc, cf, ca->ca_tag, SIISATA_CARDBUS_BAR0, 0);
221 (*cf->cardbus_space_free)(cc, cbsc->sc_rbus_memt, sc->sc_grh,
222 grsize);
223 cardbus_conf_write(cc, cf, ca->ca_tag, SIISATA_CARDBUS_BAR1, 0);
224 (*cf->cardbus_space_free)(cc, cbsc->sc_rbus_memt, sc->sc_prh,
225 prsize);
226 aprint_error("%s: couldn't establish interrupt\n",
227 SIISATANAME(sc));
228 return;
231 /* fill in number of ports on this device */
232 scp = siisata_cardbus_lookup(ca);
233 if (scp != NULL)
234 sc->sc_atac.atac_nchannels = scp->scp_ports;
235 else
236 /* _match() should prevent us from getting here */
237 panic("siisata: the universe might be falling apart!\n");
239 /* enable bus mastering in case the firmware didn't */
240 csr = cardbus_conf_read(cc, cf, ca->ca_tag, CARDBUS_COMMAND_STATUS_REG);
241 csr |= CARDBUS_COMMAND_MASTER_ENABLE;
242 csr |= CARDBUS_COMMAND_MEM_ENABLE;
243 cardbus_conf_write(cc, cf, ca->ca_tag, CARDBUS_COMMAND_STATUS_REG, csr);
245 gcreg = GRREAD(sc, GR_GC);
247 /* CardBus supports only 32-bit 33MHz */
248 KASSERT(!(gcreg &
249 (GR_GC_REQ64|GR_GC_DEVSEL|GR_GC_STOP|GR_GC_TRDY|GR_GC_M66EN)));
251 aprint_normal("%s: SiI%d on 32-bit, 33MHz PCI (CardBus).",
252 SIISATANAME(sc), scp->scp_chip);
253 if (gcreg & GR_GC_3GBPS)
254 aprint_normal(" 3.0Gb/s capable.\n");
255 else
256 aprint_normal("\n");
258 siisata_attach(sc);
260 if (!pmf_device_register(self, NULL, siisata_cardbus_resume))
261 aprint_error_dev(self, "couldn't establish power handler\n");
264 static int
265 siisata_cardbus_detach(device_t self, int flags)
267 struct cardbus_softc *cbsc = device_private(device_parent(self));
268 struct siisata_cardbus_softc *csc = device_private(self);
269 struct siisata_softc *sc = &csc->si_sc;
270 struct cardbus_devfunc *ct = csc->sc_ct;
271 cardbus_chipset_tag_t cc = ct->ct_cc;
272 cardbus_function_tag_t cf = ct->ct_cf;
273 cardbustag_t ctag = cardbus_make_tag(cc, cf, cbsc->sc_bus, ct->ct_func);
274 int rv;
276 rv = siisata_detach(sc, flags);
277 if (rv)
278 return (rv);
279 if (csc->sc_ih != NULL) {
280 cardbus_intr_disestablish(csc->sc_cc, csc->sc_cf, csc->sc_ih);
281 csc->sc_ih = NULL;
283 if (csc->sc_grsize) {
284 cardbus_conf_write(cc, cf, ctag, SIISATA_CARDBUS_BAR0, 0);
285 (*cf->cardbus_space_free)(cc, cbsc->sc_rbus_memt, sc->sc_grh,
286 csc->sc_grsize);
287 csc->sc_grsize = 0;
289 if (csc->sc_prsize) {
290 cardbus_conf_write(cc, cf, ctag, SIISATA_CARDBUS_BAR1, 0);
291 (*cf->cardbus_space_free)(cc, cbsc->sc_rbus_memt, sc->sc_prh,
292 csc->sc_prsize);
293 csc->sc_prsize = 0;
295 cardbus_free_tag(cc, cf, ctag);
296 return 0;
299 static bool
300 siisata_cardbus_resume(device_t dv, pmf_qual_t qual)
302 struct siisata_cardbus_softc *csc = device_private(dv);
303 struct siisata_softc *sc = &csc->si_sc;
304 int s;
306 s = splbio();
307 siisata_resume(sc);
308 splx(s);
310 return true;