sys/dev/pci/n8/QMgr/QMQueue.h

   1 /*-
   2  * Copyright (C) 2001-2003 by NBMK Encryption Technologies.
   3  * All rights reserved.
   4  *
   5  * NBMK Encryption Technologies provides no support of any kind for
   6  * this software.  Questions or concerns about it may be addressed to
   7  * the members of the relevant open-source community at
   8  * <tech-crypto@netbsd.org>.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions are
  12  * met:
  13  *
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  *
  17  * 2. Redistributions in binary form must reproduce the above
  18  *    copyright notice, this list of conditions and the following
  19  *    disclaimer in the documentation and/or other materials provided
  20  *    with the distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  23  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  24  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  25  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  26  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  27  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  28  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  29  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  32  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /*****************************************************************************
  36  * @(#) QMQueue.h 1.55@(#)
  37  *****************************************************************************/
  38
  39 /*****************************************************************************/
  40 /** @file QMQueue.h
  41  *  @brief Header for Encryption/Authentication and Public Key Handler Queues
  42  *
  43  *
  44  *  Header file for the Encryption/Authentication and Public Key Handler
  45  *  Queues, and their interface definitions.
  46  *
  47  *****************************************************************************/
  48
  49 /*****************************************************************************
  50  * Revision history:
  51  *
  52  * 05/13/03 brr   Correctly compute number of elements in RN Queue to determine
  53  *                when to update the RN write index. (Bug 914)
  54  * 04/21/03 brr   Added API_REQ_MASK.
  55  * 03/26/03 brr   Modified RNG not to perform PCI accesses with each reqeust
  56  *                for random bytes.
  57  * 03/19/03 brr   Added prototype for QMgrCount.
  58  * 02/20/03 brr   Elimated all references to shared memory.
  59  * 11/25/02 brr   Removed the updateAllSem.
  60  * 10/25/02 brr   Clean up function prototypes & include files.
  61  * 09/18/02 brr   Have QMgrCheckQueue return the number of requests completed.
  62  * 07/08/02 brr   Added support for polling NSP2000 device.
  63  * 06/06/02 brr   Moved waitQueue into the queue structure.
  64  * 05/30/02 brr   Use common struct for statistics & removed obsolete fields.
  65  * 05/02/02 brr   Moved all SKS fields to device struture.
  66  * 05/01/02 brr   Removed obsolete fields and added haltingMask & sizeMask.
  67  * 03/27/02 hml   Replaced N8_QueueReturnCodes_t with N8_Status_t.
  68  * 03/27/02 brr   Removed QMGR* macros and driverHandle from QueueControl_t.
  69  * 03/20/02 mmd   Added requestsCompleted stat counter to QueueControl_t.
  70  * 03/19/02 msz   Shared memory is now part of the queue control structure.
  71  * 03/18/02 msz   Don't loop forever on hardware error - Added hardwareFailed
  72  * 03/01/02 brr   Moved definition of QueueControl_t to this file since its
  73  *                internal to QMgr.
  74  * 02/26/02 brr   Modified read/write macros to update shared memory instead
  75  *                of accessing the hardware.
  76  * 02/14/02 brr   Resolve 2.0 merge problems.
  77  * 01/17/02 msz   Changes to support mirror registers - BUG  413
  78  * 12/15/01 msz   Added QMGR_CMD_Q_GET_READ_WRITE_PTR.
  79  * 12/04/01 mel   Fixed bug #395 : Added BM_includes.h to avoid crash for build
  80  *                when SUPPORTING_BM is not defined
  81  * 11/19/01 spm   Added proto for n8_SKS_Prom2Cache which is used
  82  *                QMgr setup to copy from SKS PROM to cache
  83  * 09/06/01 bac   Fixed the return type of QMgrCheckRequest.
  84  * 08/24/01 msz   Simplified macros a bit.
  85  * 08/16/01 mmd   Now including n8_driver_api.h instead of simon.h.
  86  * 08/16/01 msz   Code review changes
  87  * 08/15/01 brr   Fixed complier error when SUPPORTING_BM is not defined.
  88  * 08/01/01 msz   Created from merging EA_EnQueue.h and PK_EnQueue.h
  89  *                To see older revision history please see those files.
  90  *
  91  ****************************************************************************/
  92 /** @defgroup QMgr
  93  */
  94
  95 #ifndef QMQUEUE_H
  96 #define QMQUEUE_H
  97
  98 #include "n8_pub_types.h"
  99 #include "n8_pub_common.h"
 100 #include "n8_enqueue_common.h"
 101 #include "n8_rn_common.h"
 102 #include "nsp2000_regs.h"
 103 #include "n8_device_info.h"
 104 #include "n8_driver_parms.h"
 105 #include "helper.h"
 106
 107
 108 /*****************************************************************************
 109  * #defines
 110  *****************************************************************************/
 111
 112 #define API_REQ_MASK    (MAX_API_REQS-1)
 113
 114 /*****************************************************************************
 115  * Macros
 116  *****************************************************************************/
 117 /*
 118  * @brief Macros for queue manager operations.
 119  *
 120  * In general the macros take _queue_p as a pointer to the queue control
 121  * structure (QueueControl_t *).
 122  *
 123  * @par Assumptions:
 124  *    If the queue type is not EA (Encryption/Authentication) then it
 125  *    is PK (Public Key).  This can be done because there are separate
 126  *    macros for the RNG (random number generator) hardware.
 127  *****************************************************************************/
 128
 129
 130 /********** QMGR_IS_QUEUE_EA **********/
 131 #define QMGR_IS_EA(_queue_p)                                        \
 132    ( (_queue_p)->type == N8_EA )
 133
 134
 135 /*****************************************************************************
 136  * external data
 137  *****************************************************************************/
 138
 139 /* The one and only queue table! */
 140 extern struct QueueControlTable_s  queueTable_g;
 141
 142 /*****************************************************************************
 143  * QueueControl_t
 144  *****************************************************************************/
 145 /** @ingroup QMgr
 146  *  @struct QueueControl_t
 147  *  @brief This structure contains everything we need to know about a single
 148  *         queue.
 149  *
 150  *  The QueueControl_t structure contains all of the data needed for the use
 151  *  of a single queue. There is one queue for each execution unit on each
 152  *  chip.
 153  *
 154  *  Locks:
 155  *    The queueControlSem lock is used by the QMgr code. It ensures exclusive
 156  *    access to the QueueControl_t structure.
 157  *
 158  *    The process level concurrency semaphore queueControlSem will protect:
 159  *    · Data fields within the QueueControl_t structure, as these are on a
 160  *      per process basis.
 161  *
 162  *****************************************************************************/
 163
 164 typedef struct QueueControl_s
 165 {
 166    N8CommonRegs_t   *n8reg_p;           /**< The hardware pointer.  This
 167                                              value is set by the driver, so
 168                                              it may be common across different
 169                                              queue control structures. */
 170
 171    /* These are used in management of the queue. */
 172    QMgrRequest_t    *requestQueue[MAX_API_REQS];  /* Circular queue of API Requests */
 173    n8_WaitQueue_t    waitQueue[MAX_API_REQS];     /* Wait queue for the API Requests */
 174    int               apiWriteIdx;
 175    int               apiReadIdx;
 176
 177
 178    /* This section is for statistics on the queue */
 179    QueueStats_t      stats;
 180
 181    /* This section is for entries in the structure which are invariant across
 182       every process in the system.  In theory these variables could be moved to
 183       a shared memory segment, initialized once and attached to by all
 184       subsequent processes */
 185    int               chip;              /**< Chip number for this queue.
 186                                              Begins at 0. */
 187    N8_Component_t    type;              /**< Type of the execution unit this
 188                                              queue manages. */
 189    N8_Hardware_t     hardwareType;      /**< Type of hardware for this execution
 190                                              unit.  Note the hardware type
 191                                              may be "Behavioral Model". */
 192    int               sizeOfQueue;       /**< number of elements (not bytes) */
 193    uint32_t          sizeMask;          /**< Mask to apply to queue indexes */
 194
 195    unsigned long     cmdQueVirtPtr;     /**< Virtual Ptr to the command queue.  */
 196    unsigned long     cmdEntrySize;      /**< Length of command entry in bytes.  */
 197
 198    /* QMgr Locks */
 199    ATOMICLOCK_t      queueControlSem;   /**< Process sem for queue control */
 200
 201    /* EA_PK_data: */
 202
 203    EA_CMD_BLOCK_t   *EAq_head_p;        /**< head of the current linked list
 204                                              of EA requests.  Points into
 205                                              data allocated by the
 206                                              commandBlock structure above.
 207                                              This is set to a non zero
 208                                              value on a EA queue only. */
 209    PK_CMD_BLOCK_t   *PKq_head_p;        /**< head of the current linked list
 210                                              of PK requests.  Points into
 211                                              data allocated by the
 212                                              commandBlock structure above.
 213                                              This is set to a non zero
 214                                              value on a PK queue only. */
 215    uint16_t          writeIndex;        /* Current write index          */
 216    uint16_t         *readIndex_p;       /* Pointer to the read index    */
 217    uint32_t          remainingCmds;     /* Number of commands unable to */
 218                                         /* be processed because they do */
 219                                         /* not complete a request.      */
 220
 221    /* RNG_data: */
 222    uint16_t          readIndex;         /* Current read index            */
 223    N8RNGRegs_t      *rngReg_p;          /* Pointer to the RNG registers  */
 224    int               rngInitialized;    /* Flag indicating state of RNG  */
 225
 226    unsigned char     hardwareFailed;    /* Boolean set to non 0 if the   */
 227                                         /* hardware has a serious error. */
 228                                         /* Currently only needed in RNG. */
 229 } QueueControl_t;
 230
 231
 232
 233 /*****************************************************************************
 234  * QueueControlSet_t
 235  *****************************************************************************/
 236 /** @ingroup QMgr
 237  *  @typedef QueueControlSet_t
 238  *  @brief This type represents the queue information for a complete nsp2000
 239  *         implementation.
 240  *
 241  *  The QueueControlSet_t type contains all of the data needed for the use
 242  *  of a single nsp2000 chip.
 243  *
 244  *****************************************************************************/
 245 typedef QueueControl_t  QueueControlSet_t[N8_NUM_COMPONENTS];
 246
 247
 248 /*****************************************************************************
 249  * QueueControlTable_t
 250  *****************************************************************************/
 251 /** @ingroup QMgr
 252  *  @struct QueueControlTable_t
 253  *  @brief This structure contains the data needed for the use of all of the
 254  *  nsp2000 based queues on the machine.
 255  *
 256  *  This data structure contains an array of control sets and the number of
 257  *  control sets.
 258  *
 259  *****************************************************************************/
 260
 261 typedef struct QueueControlTable_s
 262 {
 263    QueueControlSet_t *controlSets_p;  /**< The control sets */
 264    uint32_t           nControlSets;   /**< The number of control sets */
 265    uint32_t           currentSet;     /**< The current control set to assign */
 266 } QueueControlTable_t;
 267
 268
 269
 270 /* prototypes */
 271 int  QMgrCheckQueue(N8_Component_t unit, int chip, uint16_t cmdsComplete);
 272 void QMgrCmdError(N8_Component_t    unit,
 273                   int               chip,
 274                   int               readQueueIndex,
 275                   int               configStatus);
 276
 277 int QMgrPoll(void);
 278 int QMgrCount(N8_Component_t unit);
 279
 280 #endif