sys/dev/sbus/dbrivar.h

   1 /*      $NetBSD: dbrivar.h,v 1.10 2008/05/16 15:38:20 macallan Exp $    */
   2
   3 /*
   4  * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
   5  * Copyright (c) 1998, 1999 Brent Baccala (baccala@freesoft.org)
   6  * Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill@netbsd.org>
   7  * Copyright (c) 2005 Michael Lorenz <macallan@netbsd.org>
   8  * All rights reserved.
   9  *
  10  * This driver is losely based on a Linux driver written by Rudolf Koenig and
  11  * Brent Baccala who kindly gave their permission to use their code in a
  12  * BSD-licensed driver.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions
  16  * are met:
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in the
  21  *    documentation and/or other materials provided with the distribution.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
  24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  26  * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  28  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  29  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  */
  35
  36 #ifndef DBRI_VAR_H
  37 #define DBRI_VAR_H
  38
  39 #define DBRI_NUM_COMMANDS       64
  40 #define DBRI_NUM_DESCRIPTORS    32
  41 #define DBRI_INT_BLOCKS         64
  42
  43 #define DBRI_PIPE_MAX           32
  44
  45 enum direction {
  46         in,
  47         out
  48 };
  49
  50 /* DBRI DMA transmit descriptor */
  51 struct dbri_xmit {
  52         volatile uint32_t       flags;
  53                 #define TX_EOF  0x80000000      /* End of frame marker */
  54                 #define TX_BCNT(x)      ((x&0x3fff)<<16)
  55                 #define TX_BINT 0x00008000      /* interrupt when EOF */
  56                 #define TX_MINT 0x00004000      /* marker interrupt */
  57                 #define TX_IDLE 0x00002000      /* send idles after data */
  58                 #define TX_FCNT(x)      (x&0x1fff)
  59
  60         volatile uint32_t       ba;             /* tx/rx buffer address */
  61         volatile uint32_t       nda;            /* next descriptor address */
  62         volatile uint32_t       status;
  63                 #define TS_OK           0x0001  /* transmission completed */
  64                 #define TS_ABORT        0x0004  /* transmission aborted */
  65                 #define TS_UNDERRUN     0x0008  /* DMA underrun */
  66 };
  67
  68 struct dbri_recv {
  69         volatile uint32_t       status;
  70                 #define RX_EOF          0x80000000
  71                 #define RX_COMPLETED    0x40000000
  72                 #define RX_BCNT(x)      ((x & 0x3fff) << 16)
  73                 #define RX_CRCERROR     0x00000080
  74                 #define RX_BBC          0x00000040      /* bad byte count */
  75                 #define RX_ABORT        0x00000020
  76                 #define RX_OVERRUN      0x00000008
  77         volatile uint32_t       ba;
  78         volatile uint32_t       nda;
  79         volatile uint32_t       flags;
  80                 #define RX_BSIZE(x)     (x & 0x3fff)
  81                 #define RX_FINAL        0x00008000
  82                 #define RX_MARKER       0x00004000
  83 };
  84
  85 struct dbri_pipe {
  86         uint32_t        sdp;            /* SDP command word */
  87         enum direction  direction;
  88         int             next;           /* next pipe in linked list */
  89         int             prev;           /* previous pipe in linked list */
  90         int             cycle;          /* offset of timeslot (bits) */
  91         int             length;         /* length of timeslot (bits) */
  92         int             desc;           /* index of active descriptor */
  93         volatile uint32_t       *prec;  /* pointer to received fixed data */
  94 };
  95
  96 struct dbri_desc {
  97         int             busy;
  98         void *          buf;            /* cpu view of buffer */
  99         void *          buf_dvma;       /* device view */
 100         bus_addr_t      dmabase;
 101         bus_dma_segment_t dmaseg;
 102         bus_dmamap_t    dmamap;
 103         size_t          len;
 104         void            (*callback)(void *);
 105         void            *callback_args;
 106         void            *softint;
 107 };
 108
 109 struct dbri_dma {
 110         volatile uint32_t       command[DBRI_NUM_COMMANDS];
 111         volatile int32_t        intr[DBRI_INT_BLOCKS];
 112         struct dbri_xmit        xmit[DBRI_NUM_DESCRIPTORS];
 113         struct dbri_recv        recv[DBRI_NUM_DESCRIPTORS];
 114 };
 115
 116 struct dbri_softc {
 117         device_t        sc_dev;         /* base device */
 118
 119         bus_space_handle_t sc_ioh;
 120         bus_space_tag_t sc_iot;
 121         /* DMA buffer for sending commands to the chip */
 122         bus_dma_tag_t   sc_dmat;
 123         bus_dmamap_t    sc_dmamap;
 124         bus_dma_segment_t sc_dmaseg;
 125
 126         int             sc_have_powerctl;
 127         int             sc_powerstate;  /* DBRI's powered up or not */
 128         int             sc_pmgrstate;   /* PWR_RESUME etc. */
 129         int             sc_burst;       /* DVMA burst size in effect */
 130
 131         bus_addr_t      sc_dmabase;     /* VA of buffer we provide */
 132         void *          sc_membase;
 133         int             sc_bufsiz;      /* size of the buffer */
 134         int             sc_locked;
 135         int             sc_irqp;
 136
 137         int             sc_waitseen;
 138
 139         int             sc_refcount;
 140         int             sc_playing;
 141         int             sc_recording;
 142
 143         int             sc_liu_state;
 144         void            (*sc_liu)(void *);
 145         void            *sc_liu_args;
 146
 147         struct dbri_pipe sc_pipe[DBRI_PIPE_MAX];
 148         struct dbri_desc sc_desc[DBRI_NUM_DESCRIPTORS];
 149
 150         struct cs4215_state     sc_mm;
 151         int             sc_latt, sc_ratt;       /* output attenuation */
 152         int             sc_linp, sc_rinp;       /* input volume */
 153         int             sc_monitor;             /* monitor volume */
 154         int             sc_input;               /* 0 - line, 1 - mic */
 155
 156         int             sc_ctl_mode;
 157
 158         uint32_t        sc_version;
 159         int             sc_chi_pipe_in;
 160         int             sc_chi_pipe_out;
 161         int             sc_chi_bpf;
 162
 163         int             sc_desc_used;
 164
 165         struct audio_params sc_params;
 166
 167         struct dbri_dma *sc_dma;
 168 };
 169
 170 #define dbri_dma_off(member, elem)      \
 171         ((uint32_t)(unsigned long)      \
 172          (&(((struct dbri_dma *)0)->member[elem])))
 173
 174 #if 1
 175 #define DBRI_CMD(cmd, intr, value)      ((cmd << 28) | (intr << 27) | value)
 176 #else
 177 #define DBRI_CMD(cmd, intr, value)      ((cmd << 28) | (1 << 27) | value)
 178 #endif
 179 #define DBRI_INTR_GETCHAN(v)            (((v) >> 24) & 0x3f)
 180 #define DBRI_INTR_GETCODE(v)            (((v) >> 20) & 0xf)
 181 #define DBRI_INTR_GETCMD(v)             (((v) >> 16) & 0xf)
 182 #define DBRI_INTR_GETVAL(v)             ((v) & 0xffff)
 183 #define DBRI_INTR_GETRVAL(v)            ((v) & 0xfffff)
 184
 185 #define DBRI_SDP_MODE(v)                ((v) & (7 << 13))
 186 #define DBRI_PIPE(v)                    ((v) << 0)
 187
 188 #endif /* DBRI_VAR_H */