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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / sbus / magma.c
blobbbb00527b81b0c9151273e28a4ed0194777438be
1 /* $NetBSD: magma.c,v 1.53 2009/09/17 16:28:12 tsutsui Exp $ */
2
3 /*-
4 * Copyright (c) 1998 Iain Hibbert
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 /*
29 * Driver for Magma SBus Serial/Parallel cards using the Cirrus Logic
30 * CD1400 & CD1190 chips
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: magma.c,v 1.53 2009/09/17 16:28:12 tsutsui Exp $");
35
36 #if 0
37 #define MAGMA_DEBUG
38 #endif
39
40 #include "magma.h"
41 #if NMAGMA > 0
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/proc.h>
46 #include <sys/device.h>
47 #include <sys/file.h>
48 #include <sys/ioctl.h>
49 #include <sys/malloc.h>
50 #include <sys/tty.h>
51 #include <sys/time.h>
52 #include <sys/kernel.h>
53 #include <sys/syslog.h>
54 #include <sys/conf.h>
55 #include <sys/errno.h>
56 #include <sys/kauth.h>
57 #include <sys/intr.h>
58
59 #include <sys/bus.h>
60 #include <machine/autoconf.h>
61
62 #include <dev/sbus/sbusvar.h>
63
64 #include <dev/ic/cd1400reg.h>
65 #include <dev/ic/cd1190reg.h>
66
67 #include <dev/sbus/mbppio.h>
68 #include <dev/sbus/magmareg.h>
69
70 #include "ioconf.h"
71
72 /* supported cards
73 *
74 * The table below lists the cards that this driver is likely to
75 * be able to support.
76 *
77 * Cards with parallel ports: except for the LC2+1Sp, they all use
78 * the CD1190 chip which I know nothing about. I've tried to leave
79 * hooks for it so it shouldn't be too hard to add support later.
80 * (I think somebody is working on this separately)
81 *
82 * Thanks to Bruce at Magma for telling me the hardware offsets.
83 */
84 static struct magma_board_info supported_cards[] = {
85 {
86 "MAGMA_Sp", "MAGMA,4_Sp", "Magma 4 Sp", 4, 0,
87 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 },
88 0, { 0, 0 }
89 },
90 {
91 "MAGMA_Sp", "MAGMA,8_Sp", "Magma 8 Sp", 8, 0,
92 2, 0xa000, 0xc000, 0xe000, { 0x4000, 0x6000, 0, 0 },
93 0, { 0, 0 }
94 },
95 {
96 "MAGMA_Sp", "MAGMA,_8HS_Sp", "Magma Fast 8 Sp", 8, 0,
97 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 },
98 0, { 0, 0 }
99 },
100 {
101 "MAGMA_Sp", "MAGMA,_8SP_422", "Magma 8 Sp - 422", 8, 0,
102 2, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0, 0 },
103 0, { 0, 0 }
104 },
105 {
106 "MAGMA_Sp", "MAGMA,12_Sp", "Magma 12 Sp", 12, 0,
107 3, 0xa000, 0xc000, 0xe000, { 0x2000, 0x4000, 0x6000, 0 },
108 0, { 0, 0 }
109 },
110 {
111 "MAGMA_Sp", "MAGMA,16_Sp", "Magma 16 Sp", 16, 0,
112 4, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0xa000, 0xb000 },
113 0, { 0, 0 }
114 },
115 {
116 "MAGMA_Sp", "MAGMA,16_Sp_2", "Magma 16 Sp", 16, 0,
117 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 },
118 0, { 0, 0 }
119 },
120 {
121 "MAGMA_Sp", "MAGMA,16HS_Sp", "Magma Fast 16 Sp", 16, 0,
122 4, 0x2000, 0x4000, 0x6000, { 0x8000, 0xa000, 0xc000, 0xe000 },
123 0, { 0, 0 }
124 },
125 {
126 "MAGMA_Sp", "MAGMA,21_Sp", "Magma LC 2+1 Sp", 2, 1,
127 1, 0xa000, 0xc000, 0xe000, { 0x8000, 0, 0, 0 },
128 0, { 0, 0 }
129 },
130 {
131 "MAGMA_Sp", "MAGMA,21HS_Sp", "Magma 2+1 Sp", 2, 1,
132 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 },
133 1, { 0x6000, 0 }
134 },
135 {
136 "MAGMA_Sp", "MAGMA,41_Sp", "Magma 4+1 Sp", 4, 1,
137 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 },
138 1, { 0x6000, 0 }
139 },
140 {
141 "MAGMA_Sp", "MAGMA,82_Sp", "Magma 8+2 Sp", 8, 2,
142 2, 0xd000, 0xe000, 0xf000, { 0x8000, 0x9000, 0, 0 },
143 2, { 0xa000, 0xb000 }
144 },
145 {
146 "MAGMA_Sp", "MAGMA,P1_Sp", "Magma P1 Sp", 0, 1,
147 0, 0, 0, 0, { 0, 0, 0, 0 },
148 1, { 0x8000, 0 }
149 },
150 {
151 "MAGMA_Sp", "MAGMA,P2_Sp", "Magma P2 Sp", 0, 2,
152 0, 0, 0, 0, { 0, 0, 0, 0 },
153 2, { 0x4000, 0x8000 }
154 },
155 {
156 "MAGMA 2+1HS Sp", "", "Magma 2+1HS Sp", 2, 0,
157 1, 0xa000, 0xc000, 0xe000, { 0x4000, 0, 0, 0 },
158 1, { 0x8000, 0 }
159 },
160 {
161 NULL, NULL, NULL, 0, 0,
162 0, 0, 0, 0, { 0, 0, 0, 0 },
163 0, { 0, 0 }
164 }
165 };
166
167 /************************************************************************
168 *
169 * Autoconfig Stuff
170 */
171
172 CFATTACH_DECL(magma, sizeof(struct magma_softc),
173 magma_match, magma_attach, NULL, NULL);
174
175 CFATTACH_DECL(mtty, sizeof(struct mtty_softc),
176 mtty_match, mtty_attach, NULL, NULL);
177
178 CFATTACH_DECL(mbpp, sizeof(struct mbpp_softc),
179 mbpp_match, mbpp_attach, NULL, NULL);
180
181 dev_type_open(mttyopen);
182 dev_type_close(mttyclose);
183 dev_type_read(mttyread);
184 dev_type_write(mttywrite);
185 dev_type_ioctl(mttyioctl);
186 dev_type_stop(mttystop);
187 dev_type_tty(mttytty);
188 dev_type_poll(mttypoll);
189
190 const struct cdevsw mtty_cdevsw = {
191 mttyopen, mttyclose, mttyread, mttywrite, mttyioctl,
192 mttystop, mttytty, mttypoll, nommap, ttykqfilter, D_TTY
193 };
194
195 dev_type_open(mbppopen);
196 dev_type_close(mbppclose);
197 dev_type_read(mbpp_rw);
198 dev_type_ioctl(mbppioctl);
199
200 const struct cdevsw mbpp_cdevsw = {
201 mbppopen, mbppclose, mbpp_rw, mbpp_rw, mbppioctl,
202 nostop, notty, nopoll, nommap, nokqfilter, D_OTHER
203 };
204
205 /************************************************************************
206 *
207 * CD1400 Routines
208 *
209 * cd1400_compute_baud calculate COR/BPR register values
210 * cd1400_write_ccr write a value to CD1400 ccr
211 * cd1400_read_reg read from a CD1400 register
212 * cd1400_write_reg write to a CD1400 register
213 * cd1400_enable_transmitter enable transmitting on CD1400 channel
214 */
215
216 /*
217 * compute the bpr/cor pair for any baud rate
218 * returns 0 for success, 1 for failure
219 */
220 int
221 cd1400_compute_baud(speed_t speed, int clock, int *cor, int *bpr)
222 {
223 int c, co, br;
224
225 if( speed < 50 || speed > 150000 )
226 return(1);
227
228 for( c = 0, co = 8 ; co <= 2048 ; co <<= 2, c++ ) {
229 br = ((clock * 1000000) + (co * speed) / 2) / (co * speed);
230 if( br < 0x100 ) {
231 *bpr = br;
232 *cor = c;
233 return(0);
234 }
235 }
236
237 return(1);
238 }
239
240 /*
241 * Write a CD1400 channel command, should have a timeout?
242 */
243 inline void
244 cd1400_write_ccr(struct cd1400 *cd, u_char cmd)
245 {
246 while( cd1400_read_reg(cd, CD1400_CCR) )
247 ;
248
249 cd1400_write_reg(cd, CD1400_CCR, cmd);
250 }
251
252 /*
253 * read a value from a cd1400 register
254 */
255 inline u_char
256 cd1400_read_reg(struct cd1400 *cd, int reg)
257 {
258 return(cd->cd_reg[reg]);
259 }
260
261 /*
262 * write a value to a cd1400 register
263 */
264 inline void
265 cd1400_write_reg(struct cd1400 *cd, int reg, u_char value)
266 {
267 cd->cd_reg[reg] = value;
268 }
269
270 /*
271 * enable transmit service requests for cd1400 channel
272 */
273 void
274 cd1400_enable_transmitter(struct cd1400 *cd, int channel)
275 {
276 int s, srer;
277
278 s = spltty();
279 cd1400_write_reg(cd, CD1400_CAR, channel);
280 srer = cd1400_read_reg(cd, CD1400_SRER);
281 SET(srer, CD1400_SRER_TXRDY);
282 cd1400_write_reg(cd, CD1400_SRER, srer);
283 splx(s);
284 }
285
286 /************************************************************************
287 *
288 * CD1190 Routines
289 */
290
291 /* well, there are none yet */
292
293 /************************************************************************
294 *
295 * Magma Routines
296 *
297 * magma_match reports if we have a magma board available
298 * magma_attach attaches magma boards to the sbus
299 * magma_hard hardware level interrupt routine
300 * magma_soft software level interrupt routine
301 */
302
303 int
304 magma_match(device_t parent, cfdata_t cf, void *aux)
305 {
306 struct sbus_attach_args *sa = aux;
307 struct magma_board_info *card;
308
309 /* See if we support this device */
310 for (card = supported_cards; ; card++) {
311 if (card->mb_sbusname == NULL)
312 /* End of table: no match */
313 return (0);
314 if (strcmp(sa->sa_name, card->mb_sbusname) == 0)
315 break;
316 }
317
318 dprintf(("magma: matched `%s'\n", sa->sa_name));
319 dprintf(("magma: magma_prom `%s'\n",
320 prom_getpropstring(sa->sa_node, "magma_prom")));
321 dprintf(("magma: intlevels `%s'\n",
322 prom_getpropstring(sa->sa_node, "intlevels")));
323 dprintf(("magma: chiprev `%s'\n",
324 prom_getpropstring(sa->sa_node, "chiprev")));
325 dprintf(("magma: clock `%s'\n",
326 prom_getpropstring(sa->sa_node, "clock")));
327
328 return (1);
329 }
330
331 void
332 magma_attach(device_t parent, device_t self, void *aux)
333 {
334 struct sbus_attach_args *sa = aux;
335 struct magma_softc *sc = device_private(self);
336 struct magma_board_info *card;
337 bus_space_handle_t bh;
338 char *magma_prom, *clockstr;
339 int cd_clock;
340 int node, chip;
341
342 node = sa->sa_node;
343
344 /*
345 * Find the card model.
346 * Older models all have sbus node name `MAGMA_Sp' (see
347 * `supported_cards[]' above), and must be distinguished
348 * by the `magma_prom' property.
349 */
350 magma_prom = prom_getpropstring(node, "magma_prom");
351
352 for (card = supported_cards; card->mb_name != NULL; card++) {
353 if (strcmp(sa->sa_name, card->mb_sbusname) != 0)
354 /* Sbus node name doesn't match */
355 continue;
356 if (strcmp(magma_prom, card->mb_name) == 0)
357 /* Model name match */
358 break;
359 }
360
361 if( card->mb_name == NULL ) {
362 printf(": %s (unsupported)\n", magma_prom);
363 return;
364 }
365
366 dprintf((" addr %p", sc));
367 printf(": %s\n", card->mb_realname);
368
369 sc->ms_board = card;
370 sc->ms_ncd1400 = card->mb_ncd1400;
371 sc->ms_ncd1190 = card->mb_ncd1190;
372
373 if (sbus_bus_map(sa->sa_bustag,
374 sa->sa_slot, sa->sa_offset, sa->sa_size,
375 BUS_SPACE_MAP_LINEAR, &bh) != 0) {
376 aprint_error("%s @ sbus: cannot map registers\n",
377 device_xname(self));
378 return;
379 }
380
381 /* the SVCACK* lines are daisychained */
382 sc->ms_svcackr = (char *)bus_space_vaddr(sa->sa_bustag, bh)
383 + card->mb_svcackr;
384 sc->ms_svcackt = (char *)bus_space_vaddr(sa->sa_bustag, bh)
385 + card->mb_svcackt;
386 sc->ms_svcackm = (char *)bus_space_vaddr(sa->sa_bustag, bh)
387 + card->mb_svcackm;
388
389 /*
390 * Find the clock speed; it's the same for all CD1400 chips
391 * on the board.
392 */
393 clockstr = prom_getpropstring(node, "clock");
394 if (*clockstr == '\0')
395 /* Default to 25MHz */
396 cd_clock = 25;
397 else {
398 cd_clock = 0;
399 while (*clockstr != '\0')
400 cd_clock = (cd_clock * 10) + (*clockstr++ - '0');
401 }
402
403 /* init the cd1400 chips */
404 for( chip = 0 ; chip < card->mb_ncd1400 ; chip++ ) {
405 struct cd1400 *cd = &sc->ms_cd1400[chip];
406
407 cd->cd_clock = cd_clock;
408 cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) +
409 card->mb_cd1400[chip];
410
411 /* prom_getpropstring(node, "chiprev"); */
412 /* seemingly the Magma drivers just ignore the propstring */
413 cd->cd_chiprev = cd1400_read_reg(cd, CD1400_GFRCR);
414
415 dprintf(("%s attach CD1400 %d addr %p rev %x clock %dMHz\n",
416 device_xname(&sc->ms_dev), chip,
417 cd->cd_reg, cd->cd_chiprev, cd->cd_clock));
418
419 /* clear GFRCR */
420 cd1400_write_reg(cd, CD1400_GFRCR, 0x00);
421
422 /* reset whole chip */
423 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FULLRESET);
424
425 /* wait for revision code to be restored */
426 while( cd1400_read_reg(cd, CD1400_GFRCR) != cd->cd_chiprev )
427 ;
428
429 /* set the Prescaler Period Register to tick at 1ms */
430 cd1400_write_reg(cd, CD1400_PPR,
431 ((cd->cd_clock * 1000000 / CD1400_PPR_PRESCALER + 500) / 1000));
432
433 /* The LC2+1Sp card is the only card that doesn't have
434 * a CD1190 for the parallel port, but uses channel 0 of
435 * the CD1400, so we make a note of it for later and set up
436 * the CD1400 for parallel mode operation.
437 */
438 if( card->mb_npar && card->mb_ncd1190 == 0 ) {
439 cd1400_write_reg(cd, CD1400_GCR, CD1400_GCR_PARALLEL);
440 cd->cd_parmode = 1;
441 }
442 }
443
444 /* init the cd1190 chips */
445 for( chip = 0 ; chip < card->mb_ncd1190 ; chip++ ) {
446 struct cd1190 *cd = &sc->ms_cd1190[chip];
447
448 cd->cd_reg = (char *)bus_space_vaddr(sa->sa_bustag, bh) +
449 card->mb_cd1190[chip];
450
451 /* XXX don't know anything about these chips yet */
452 printf("%s: CD1190 %d addr %p (unsupported)\n",
453 device_xname(self), chip, cd->cd_reg);
454 }
455
456 /* configure the children */
457 (void)config_found(self, mtty_match, NULL);
458 (void)config_found(self, mbpp_match, NULL);
459
460 /*
461 * Establish the interrupt handlers.
462 */
463 if (sa->sa_nintr == 0)
464 return; /* No interrupts to service!? */
465
466 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_SERIAL,
467 magma_hard, sc);
468 sc->ms_sicookie = softint_establish(SOFTINT_SERIAL, magma_soft, sc);
469 if (sc->ms_sicookie == NULL) {
470 aprint_normal("\n");
471 aprint_error_dev(&sc->ms_dev, "cannot establish soft int handler\n");
472 return;
473 }
474 evcnt_attach_dynamic(&sc->ms_intrcnt, EVCNT_TYPE_INTR, NULL,
475 device_xname(&sc->ms_dev), "intr");
476 }
477
478 /*
479 * hard interrupt routine
480 *
481 * returns 1 if it handled it, otherwise 0
482 *
483 * runs at IPL_SERIAL
484 */
485 int
486 magma_hard(void *arg)
487 {
488 struct magma_softc *sc = arg;
489 struct cd1400 *cd;
490 int chip, status = 0;
491 int serviced = 0;
492 int needsoftint = 0;
493
494 /*
495 * check status of all the CD1400 chips
496 */
497 for( chip = 0 ; chip < sc->ms_ncd1400 ; chip++ )
498 status |= cd1400_read_reg(&sc->ms_cd1400[chip], CD1400_SVRR);
499
500 if( ISSET(status, CD1400_SVRR_RXRDY) ) {
501 u_char rivr = *sc->ms_svcackr; /* enter rx service context */
502 int port = rivr >> 4;
503
504 if( rivr & (1<<3) ) { /* parallel port */
505 struct mbpp_port *mbpp;
506 int n_chars;
507
508 mbpp = &sc->ms_mbpp->ms_port[port];
509 cd = mbpp->mp_cd1400;
510
511 /* don't think we have to handle exceptions */
512 n_chars = cd1400_read_reg(cd, CD1400_RDCR);
513 while (n_chars--) {
514 if( mbpp->mp_cnt == 0 ) {
515 SET(mbpp->mp_flags, MBPPF_WAKEUP);
516 needsoftint = 1;
517 break;
518 }
519 *mbpp->mp_ptr = cd1400_read_reg(cd,CD1400_RDSR);
520 mbpp->mp_ptr++;
521 mbpp->mp_cnt--;
522 }
523 } else { /* serial port */
524 struct mtty_port *mtty;
525 u_char *ptr, n_chars, line_stat;
526
527 mtty = &sc->ms_mtty->ms_port[port];
528 cd = mtty->mp_cd1400;
529
530 if( ISSET(rivr, CD1400_RIVR_EXCEPTION) ) {
531 line_stat = cd1400_read_reg(cd, CD1400_RDSR);
532 n_chars = 1;
533 } else { /* no exception, received data OK */
534 line_stat = 0;
535 n_chars = cd1400_read_reg(cd, CD1400_RDCR);
536 }
537
538 ptr = mtty->mp_rput;
539 while( n_chars-- ) {
540 *ptr++ = line_stat;
541 *ptr++ = cd1400_read_reg(cd, CD1400_RDSR);
542 if( ptr == mtty->mp_rend ) ptr = mtty->mp_rbuf;
543 if( ptr == mtty->mp_rget ) {
544 if( ptr == mtty->mp_rbuf )
545 ptr = mtty->mp_rend;
546 ptr -= 2;
547 SET(mtty->mp_flags, MTTYF_RING_OVERFLOW);
548 break;
549 }
550 }
551 mtty->mp_rput = ptr;
552
553 needsoftint = 1;
554 }
555
556 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */
557 serviced = 1;
558 } /* if(rx_service...) */
559
560 if( ISSET(status, CD1400_SVRR_MDMCH) ) {
561 u_char mivr = *sc->ms_svcackm; /* enter mdm service context */
562 int port = mivr >> 4;
563 struct mtty_port *mtty;
564 int carrier;
565 u_char msvr;
566
567 /*
568 * Handle CD (LC2+1Sp = DSR) changes.
569 */
570 mtty = &sc->ms_mtty->ms_port[port];
571 cd = mtty->mp_cd1400;
572 msvr = cd1400_read_reg(cd, CD1400_MSVR2);
573 carrier = ISSET(msvr, cd->cd_parmode ? CD1400_MSVR2_DSR : CD1400_MSVR2_CD);
574
575 if( mtty->mp_carrier != carrier ) {
576 SET(mtty->mp_flags, MTTYF_CARRIER_CHANGED);
577 mtty->mp_carrier = carrier;
578 needsoftint = 1;
579 }
580
581 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */
582 serviced = 1;
583 } /* if(mdm_service...) */
584
585 if( ISSET(status, CD1400_SVRR_TXRDY) ) {
586 u_char tivr = *sc->ms_svcackt; /* enter tx service context */
587 int port = tivr >> 4;
588
589 if( tivr & (1<<3) ) { /* parallel port */
590 struct mbpp_port *mbpp;
591
592 mbpp = &sc->ms_mbpp->ms_port[port];
593 cd = mbpp->mp_cd1400;
594
595 if( mbpp->mp_cnt ) {
596 int count = 0;
597
598 /* fill the fifo */
599 while (mbpp->mp_cnt &&
600 count++ < CD1400_PAR_FIFO_SIZE) {
601 cd1400_write_reg(cd, CD1400_TDR,
602 *mbpp->mp_ptr);
603 mbpp->mp_ptr++;
604 mbpp->mp_cnt--;
605 }
606 } else {
607 /*
608 * fifo is empty and we got no more data
609 * to send, so shut off interrupts and
610 * signal for a wakeup, which can't be
611 * done here in case we beat mbpp_send to
612 * the tsleep call (we are running at >spltty)
613 */
614 cd1400_write_reg(cd, CD1400_SRER, 0);
615 SET(mbpp->mp_flags, MBPPF_WAKEUP);
616 needsoftint = 1;
617 }
618 } else { /* serial port */
619 struct mtty_port *mtty;
620 struct tty *tp;
621
622 mtty = &sc->ms_mtty->ms_port[port];
623 cd = mtty->mp_cd1400;
624 tp = mtty->mp_tty;
625
626 if( !ISSET(mtty->mp_flags, MTTYF_STOP) ) {
627 int count = 0;
628
629 /* check if we should start/stop a break */
630 if( ISSET(mtty->mp_flags, MTTYF_SET_BREAK) ) {
631 cd1400_write_reg(cd, CD1400_TDR, 0);
632 cd1400_write_reg(cd, CD1400_TDR, 0x81);
633 /* should we delay too? */
634 CLR(mtty->mp_flags, MTTYF_SET_BREAK);
635 count += 2;
636 }
637
638 if( ISSET(mtty->mp_flags, MTTYF_CLR_BREAK) ) {
639 cd1400_write_reg(cd, CD1400_TDR, 0);
640 cd1400_write_reg(cd, CD1400_TDR, 0x83);
641 CLR(mtty->mp_flags, MTTYF_CLR_BREAK);
642 count += 2;
643 }
644
645 /* I don't quite fill the fifo in case the last one is a
646 * NULL which I have to double up because its the escape
647 * code for embedded transmit characters.
648 */
649 while( mtty->mp_txc > 0 && count < CD1400_TX_FIFO_SIZE - 1 ) {
650 u_char ch;
651
652 ch = *mtty->mp_txp;
653
654 mtty->mp_txc--;
655 mtty->mp_txp++;
656
657 if( ch == 0 ) {
658 cd1400_write_reg(cd, CD1400_TDR, ch);
659 count++;
660 }
661
662 cd1400_write_reg(cd, CD1400_TDR, ch);
663 count++;
664 }
665 }
666
667 /* if we ran out of work or are requested to STOP then
668 * shut off the txrdy interrupts and signal DONE to flush
669 * out the chars we have sent.
670 */
671 if( mtty->mp_txc == 0 || ISSET(mtty->mp_flags, MTTYF_STOP) ) {
672 register int srer;
673
674 srer = cd1400_read_reg(cd, CD1400_SRER);
675 CLR(srer, CD1400_SRER_TXRDY);
676 cd1400_write_reg(cd, CD1400_SRER, srer);
677 CLR(mtty->mp_flags, MTTYF_STOP);
678
679 SET(mtty->mp_flags, MTTYF_DONE);
680 needsoftint = 1;
681 }
682 }
683
684 cd1400_write_reg(cd, CD1400_EOSRR, 0); /* end service context */
685 serviced = 1;
686 } /* if(tx_service...) */
687
688 /* XXX service CD1190 interrupts too
689 for( chip = 0 ; chip < sc->ms_ncd1190 ; chip++ ) {
690 }
691 */
692
693 if (needsoftint)
694 /* trigger the soft interrupt */
695 softint_schedule(sc->ms_sicookie);
696
697 return(serviced);
698 }
699
700 /*
701 * magma soft interrupt handler
702 *
703 * runs at IPL_SOFTSERIAL
704 */
705 void
706 magma_soft(void *arg)
707 {
708 struct magma_softc *sc = arg;
709 struct mtty_softc *mtty = sc->ms_mtty;
710 struct mbpp_softc *mbpp = sc->ms_mbpp;
711 int port;
712 int s, flags;
713
714 if (mtty == NULL)
715 goto chkbpp;
716
717 /*
718 * check the tty ports to see what needs doing
719 */
720 for( port = 0 ; port < mtty->ms_nports ; port++ ) {
721 struct mtty_port *mp = &mtty->ms_port[port];
722 struct tty *tp = mp->mp_tty;
723
724 if( !ISSET(tp->t_state, TS_ISOPEN) )
725 continue;
726
727 /*
728 * handle any received data
729 */
730 while( mp->mp_rget != mp->mp_rput ) {
731 u_char stat;
732 int data;
733
734 stat = mp->mp_rget[0];
735 data = mp->mp_rget[1];
736 mp->mp_rget = ((mp->mp_rget + 2) == mp->mp_rend)
737 ? mp->mp_rbuf : (mp->mp_rget + 2);
738
739 if( stat & (CD1400_RDSR_BREAK | CD1400_RDSR_FE) )
740 data |= TTY_FE;
741 if( stat & CD1400_RDSR_PE )
742 data |= TTY_PE;
743
744 if( stat & CD1400_RDSR_OE )
745 log(LOG_WARNING, "%s%x: fifo overflow\n",
746 device_xname(&mtty->ms_dev), port);
747
748 (*tp->t_linesw->l_rint)(data, tp);
749 }
750
751 s = splserial(); /* block out hard interrupt routine */
752 flags = mp->mp_flags;
753 CLR(mp->mp_flags, MTTYF_DONE | MTTYF_CARRIER_CHANGED | MTTYF_RING_OVERFLOW);
754 splx(s); /* ok */
755
756 if( ISSET(flags, MTTYF_CARRIER_CHANGED) ) {
757 dprintf(("%s%x: cd %s\n", device_xname(&mtty->ms_dev),
758 port, mp->mp_carrier ? "on" : "off"));
759 (*tp->t_linesw->l_modem)(tp, mp->mp_carrier);
760 }
761
762 if( ISSET(flags, MTTYF_RING_OVERFLOW) ) {
763 log(LOG_WARNING, "%s%x: ring buffer overflow\n",
764 device_xname(&mtty->ms_dev), port);
765 }
766
767 if( ISSET(flags, MTTYF_DONE) ) {
768 ndflush(&tp->t_outq, mp->mp_txp - tp->t_outq.c_cf);
769 CLR(tp->t_state, TS_BUSY);
770 (*tp->t_linesw->l_start)(tp); /* might be some more */
771 }
772 } /* for(each mtty...) */
773
774
775 chkbpp:
776 /*
777 * Check the bpp ports (if any) to see what needs doing
778 */
779 if (mbpp == NULL)
780 return;
781
782 for( port = 0 ; port < mbpp->ms_nports ; port++ ) {
783 struct mbpp_port *mp = &mbpp->ms_port[port];
784
785 if( !ISSET(mp->mp_flags, MBPPF_OPEN) )
786 continue;
787
788 s = splserial();
789 flags = mp->mp_flags;
790 CLR(mp->mp_flags, MBPPF_WAKEUP);
791 splx(s);
792
793 if( ISSET(flags, MBPPF_WAKEUP) ) {
794 wakeup(mp);
795 }
796
797 } /* for(each mbpp...) */
798 }
799
800 /************************************************************************
801 *
802 * MTTY Routines
803 *
804 * mtty_match match one mtty device
805 * mtty_attach attach mtty devices
806 * mttyopen open mtty device
807 * mttyclose close mtty device
808 * mttyread read from mtty
809 * mttywrite write to mtty
810 * mttyioctl do ioctl on mtty
811 * mttytty return tty pointer for mtty
812 * mttystop stop mtty device
813 * mtty_start start mtty device
814 * mtty_param set mtty parameters
815 * mtty_modem_control set modem control lines
816 */
817
818 int
819 mtty_match(device_t parent, cfdata_t cf, void *args)
820 {
821 struct magma_softc *sc = device_private(parent);
822
823 return( args == mtty_match && sc->ms_board->mb_nser && sc->ms_mtty == NULL );
824 }
825
826 void
827 mtty_attach(device_t parent, device_t dev, void *args)
828 {
829 struct magma_softc *sc = device_private(parent);
830 struct mtty_softc *ms = device_private(dev);
831 int port, chip, chan;
832
833 sc->ms_mtty = ms;
834 dprintf((" addr %p", ms));
835
836 for( port = 0, chip = 0, chan = 0 ; port < sc->ms_board->mb_nser ; port++ ) {
837 struct mtty_port *mp = &ms->ms_port[port];
838 struct tty *tp;
839
840 mp->mp_cd1400 = &sc->ms_cd1400[chip];
841 if (mp->mp_cd1400->cd_parmode && chan == 0)
842 chan = 1; /* skip channel 0 if parmode */
843 mp->mp_channel = chan;
844
845 tp = ttymalloc();
846 if (tp == NULL) break;
847 tty_attach(tp);
848 tp->t_oproc = mtty_start;
849 tp->t_param = mtty_param;
850
851 mp->mp_tty = tp;
852
853 mp->mp_rbuf = malloc(MTTY_RBUF_SIZE, M_DEVBUF, M_NOWAIT);
854 if (mp->mp_rbuf == NULL) break;
855
856 mp->mp_rend = mp->mp_rbuf + MTTY_RBUF_SIZE;
857
858 chan = (chan + 1) % CD1400_NO_OF_CHANNELS;
859 if (chan == 0)
860 chip++;
861 }
862
863 ms->ms_nports = port;
864 printf(": %d tty%s\n", port, port == 1 ? "" : "s");
865 }
866
867 /*
868 * open routine. returns zero if successful, else error code
869 */
870 int
871 mttyopen(dev_t dev, int flags, int mode, struct lwp *l)
872 {
873 int card = MAGMA_CARD(dev);
874 int port = MAGMA_PORT(dev);
875 struct mtty_softc *ms;
876 struct mtty_port *mp;
877 struct tty *tp;
878 struct cd1400 *cd;
879 int error, s;
880
881 if ((ms = device_lookup_private(&mtty_cd, card)) == NULL
882 || port >= ms->ms_nports )
883 return(ENXIO); /* device not configured */
884
885 mp = &ms->ms_port[port];
886 tp = mp->mp_tty;
887 tp->t_dev = dev;
888
889 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
890 return (EBUSY);
891
892 s = spltty();
893
894 if( !ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
895
896 /* set defaults */
897 ttychars(tp);
898 tp->t_iflag = TTYDEF_IFLAG;
899 tp->t_oflag = TTYDEF_OFLAG;
900 tp->t_cflag = TTYDEF_CFLAG;
901 if( ISSET(mp->mp_openflags, TIOCFLAG_CLOCAL) )
902 SET(tp->t_cflag, CLOCAL);
903 if( ISSET(mp->mp_openflags, TIOCFLAG_CRTSCTS) )
904 SET(tp->t_cflag, CRTSCTS);
905 if( ISSET(mp->mp_openflags, TIOCFLAG_MDMBUF) )
906 SET(tp->t_cflag, MDMBUF);
907 tp->t_lflag = TTYDEF_LFLAG;
908 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
909
910 /* init ring buffer */
911 mp->mp_rput = mp->mp_rget = mp->mp_rbuf;
912
913 /* reset CD1400 channel */
914 cd = mp->mp_cd1400;
915 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel);
916 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET);
917
918 /* encode the port number in top half of LIVR */
919 cd1400_write_reg(cd, CD1400_LIVR, port << 4 );
920
921 /* sets parameters and raises DTR */
922 (void)mtty_param(tp, &tp->t_termios);
923
924 /* set tty watermarks */
925 ttsetwater(tp);
926
927 /* enable service requests */
928 cd1400_write_reg(cd, CD1400_SRER,
929 CD1400_SRER_RXDATA | CD1400_SRER_MDMCH);
930
931 /* tell the tty about the carrier status */
932 if( ISSET(mp->mp_openflags, TIOCFLAG_SOFTCAR) ||
933 mp->mp_carrier )
934 SET(tp->t_state, TS_CARR_ON);
935 else
936 CLR(tp->t_state, TS_CARR_ON);
937 }
938 splx(s);
939
940 error = ttyopen(tp, MTTY_DIALOUT(dev), ISSET(flags, O_NONBLOCK));
941 if (error != 0)
942 goto bad;
943
944 error = (*tp->t_linesw->l_open)(dev, tp);
945 if (error != 0)
946 goto bad;
947
948 bad:
949 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
950 /*
951 * We failed to open the device, and nobody else had it opened.
952 * Clean up the state as appropriate.
953 */
954 /* XXX - do that here */
955 }
956
957 return (error);
958 }
959
960 /*
961 * close routine. returns zero if successful, else error code
962 */
963 int
964 mttyclose(dev_t dev, int flag, int mode, struct lwp *l)
965 {
966 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
967 MAGMA_CARD(dev));
968 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
969 struct tty *tp = mp->mp_tty;
970 int s;
971
972 (*tp->t_linesw->l_close)(tp, flag);
973 ttyclose(tp);
974
975 s = spltty();
976
977 /* if HUPCL is set, and the tty is no longer open
978 * shut down the port
979 */
980 if( ISSET(tp->t_cflag, HUPCL) || !ISSET(tp->t_state, TS_ISOPEN) ) {
981 /* XXX wait until FIFO is empty before turning off the channel
982 struct cd1400 *cd = mp->mp_cd1400;
983 */
984
985 /* drop DTR and RTS */
986 (void)mtty_modem_control(mp, 0, DMSET);
987
988 /* turn off the channel
989 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel);
990 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET);
991 */
992 }
993
994 splx(s);
995
996 return(0);
997 }
998
999 /*
1000 * Read routine
1001 */
1002 int
1003 mttyread(dev_t dev, struct uio *uio, int flags)
1004 {
1005 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1006 MAGMA_CARD(dev));
1007 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1008 struct tty *tp = mp->mp_tty;
1009
1010 return( (*tp->t_linesw->l_read)(tp, uio, flags) );
1011 }
1012
1013 /*
1014 * Write routine
1015 */
1016 int
1017 mttywrite(dev_t dev, struct uio *uio, int flags)
1018 {
1019 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1020 MAGMA_CARD(dev));
1021 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1022 struct tty *tp = mp->mp_tty;
1023
1024 return( (*tp->t_linesw->l_write)(tp, uio, flags) );
1025 }
1026
1027 /*
1028 * Poll routine
1029 */
1030 int
1031 mttypoll(dev_t dev, int events, struct lwp *l)
1032 {
1033 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1034 MAGMA_CARD(dev));
1035 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1036 struct tty *tp = mp->mp_tty;
1037
1038 return ((*tp->t_linesw->l_poll)(tp, events, l));
1039 }
1040
1041 /*
1042 * return tty pointer
1043 */
1044 struct tty *
1045 mttytty(dev_t dev)
1046 {
1047 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1048 MAGMA_CARD(dev));
1049 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1050
1051 return(mp->mp_tty);
1052 }
1053
1054 /*
1055 * ioctl routine
1056 */
1057 int
1058 mttyioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l)
1059 {
1060 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1061 MAGMA_CARD(dev));
1062 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1063 struct tty *tp = mp->mp_tty;
1064 int error;
1065
1066 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flags, l);
1067 if( error != EPASSTHROUGH ) return(error);
1068
1069 error = ttioctl(tp, cmd, data, flags, l);
1070 if( error != EPASSTHROUGH ) return(error);
1071
1072 error = 0;
1073
1074 switch(cmd) {
1075 case TIOCSBRK: /* set break */
1076 SET(mp->mp_flags, MTTYF_SET_BREAK);
1077 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel);
1078 break;
1079
1080 case TIOCCBRK: /* clear break */
1081 SET(mp->mp_flags, MTTYF_CLR_BREAK);
1082 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel);
1083 break;
1084
1085 case TIOCSDTR: /* set DTR */
1086 mtty_modem_control(mp, TIOCM_DTR, DMBIS);
1087 break;
1088
1089 case TIOCCDTR: /* clear DTR */
1090 mtty_modem_control(mp, TIOCM_DTR, DMBIC);
1091 break;
1092
1093 case TIOCMSET: /* set modem lines */
1094 mtty_modem_control(mp, *((int *)data), DMSET);
1095 break;
1096
1097 case TIOCMBIS: /* bit set modem lines */
1098 mtty_modem_control(mp, *((int *)data), DMBIS);
1099 break;
1100
1101 case TIOCMBIC: /* bit clear modem lines */
1102 mtty_modem_control(mp, *((int *)data), DMBIC);
1103 break;
1104
1105 case TIOCMGET: /* get modem lines */
1106 *((int *)data) = mtty_modem_control(mp, 0, DMGET);
1107 break;
1108
1109 case TIOCGFLAGS:
1110 *((int *)data) = mp->mp_openflags;
1111 break;
1112
1113 case TIOCSFLAGS:
1114 if (kauth_authorize_device_tty(l->l_cred,
1115 KAUTH_DEVICE_TTY_PRIVSET, tp))
1116 error = EPERM;
1117 else
1118 mp->mp_openflags = *((int *)data) &
1119 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL |
1120 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF);
1121 break;
1122
1123 default:
1124 error = EPASSTHROUGH;
1125 }
1126
1127 return(error);
1128 }
1129
1130 /*
1131 * Stop output, e.g., for ^S or output flush.
1132 */
1133 void
1134 mttystop(struct tty *tp, int flags)
1135 {
1136 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1137 MAGMA_CARD(tp->t_dev));
1138 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)];
1139 int s;
1140
1141 s = spltty();
1142
1143 if( ISSET(tp->t_state, TS_BUSY) ) {
1144 if( !ISSET(tp->t_state, TS_TTSTOP) )
1145 SET(tp->t_state, TS_FLUSH);
1146
1147 /*
1148 * the transmit interrupt routine will disable transmit when it
1149 * notices that MTTYF_STOP has been set.
1150 */
1151 SET(mp->mp_flags, MTTYF_STOP);
1152 }
1153
1154 splx(s);
1155 }
1156
1157 /*
1158 * Start output, after a stop.
1159 */
1160 void
1161 mtty_start(struct tty *tp)
1162 {
1163 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1164 MAGMA_CARD(tp->t_dev));
1165 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)];
1166 int s;
1167
1168 s = spltty();
1169
1170 /* we only need to do something if we are not already busy
1171 * or delaying or stopped
1172 */
1173 if( !ISSET(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) {
1174 if (ttypull(tp)) {
1175 mp->mp_txc = ndqb(&tp->t_outq, 0);
1176 mp->mp_txp = tp->t_outq.c_cf;
1177 SET(tp->t_state, TS_BUSY);
1178 cd1400_enable_transmitter(mp->mp_cd1400, mp->mp_channel);
1179 }
1180 }
1181
1182 splx(s);
1183 }
1184
1185 /*
1186 * set/get modem line status
1187 *
1188 * bits can be: TIOCM_DTR, TIOCM_RTS, TIOCM_CTS, TIOCM_CD, TIOCM_RI, TIOCM_DSR
1189 *
1190 * note that DTR and RTS lines are exchanged, and that DSR is
1191 * not available on the LC2+1Sp card (used as CD)
1192 *
1193 * only let them fiddle with RTS if CRTSCTS is not enabled
1194 */
1195 int
1196 mtty_modem_control(struct mtty_port *mp, int bits, int howto)
1197 {
1198 struct cd1400 *cd = mp->mp_cd1400;
1199 struct tty *tp = mp->mp_tty;
1200 int s, msvr;
1201
1202 s = spltty();
1203
1204 cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel);
1205
1206 switch(howto) {
1207 case DMGET: /* get bits */
1208 bits = 0;
1209
1210 bits |= TIOCM_LE;
1211
1212 msvr = cd1400_read_reg(cd, CD1400_MSVR1);
1213 if( msvr & CD1400_MSVR1_RTS ) bits |= TIOCM_DTR;
1214
1215 msvr = cd1400_read_reg(cd, CD1400_MSVR2);
1216 if( msvr & CD1400_MSVR2_DTR ) bits |= TIOCM_RTS;
1217 if( msvr & CD1400_MSVR2_CTS ) bits |= TIOCM_CTS;
1218 if( msvr & CD1400_MSVR2_RI ) bits |= TIOCM_RI;
1219 if( msvr & CD1400_MSVR2_DSR ) bits |= (cd->cd_parmode ? TIOCM_CD : TIOCM_DSR);
1220 if( msvr & CD1400_MSVR2_CD ) bits |= (cd->cd_parmode ? 0 : TIOCM_CD);
1221
1222 break;
1223
1224 case DMSET: /* reset bits */
1225 if( !ISSET(tp->t_cflag, CRTSCTS) )
1226 cd1400_write_reg(cd, CD1400_MSVR2, ((bits & TIOCM_RTS) ? CD1400_MSVR2_DTR : 0));
1227
1228 cd1400_write_reg(cd, CD1400_MSVR1, ((bits & TIOCM_DTR) ? CD1400_MSVR1_RTS : 0));
1229
1230 break;
1231
1232 case DMBIS: /* set bits */
1233 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) )
1234 cd1400_write_reg(cd, CD1400_MSVR2, CD1400_MSVR2_DTR);
1235
1236 if( bits & TIOCM_DTR )
1237 cd1400_write_reg(cd, CD1400_MSVR1, CD1400_MSVR1_RTS);
1238
1239 break;
1240
1241 case DMBIC: /* clear bits */
1242 if( (bits & TIOCM_RTS) && !ISSET(tp->t_cflag, CRTSCTS) )
1243 cd1400_write_reg(cd, CD1400_MSVR2, 0);
1244
1245 if( bits & TIOCM_DTR )
1246 cd1400_write_reg(cd, CD1400_MSVR1, 0);
1247
1248 break;
1249 }
1250
1251 splx(s);
1252 return(bits);
1253 }
1254
1255 /*
1256 * Set tty parameters, returns error or 0 on success
1257 */
1258 int
1259 mtty_param(struct tty *tp, struct termios *t)
1260 {
1261 struct mtty_softc *ms = device_lookup_private(&mtty_cd,
1262 MAGMA_CARD(tp->t_dev));
1263 struct mtty_port *mp = &ms->ms_port[MAGMA_PORT(tp->t_dev)];
1264 struct cd1400 *cd = mp->mp_cd1400;
1265 int rbpr, tbpr, rcor, tcor;
1266 u_char mcor1 = 0, mcor2 = 0;
1267 int s, opt;
1268
1269 if( t->c_ospeed && cd1400_compute_baud(t->c_ospeed, cd->cd_clock, &tcor, &tbpr) )
1270 return(EINVAL);
1271
1272 if( t->c_ispeed && cd1400_compute_baud(t->c_ispeed, cd->cd_clock, &rcor, &rbpr) )
1273 return(EINVAL);
1274
1275 s = spltty();
1276
1277 /* hang up the line if ospeed is zero, else raise DTR */
1278 (void)mtty_modem_control(mp, TIOCM_DTR, (t->c_ospeed == 0 ? DMBIC : DMBIS));
1279
1280 /* select channel, done in mtty_modem_control() */
1281 /* cd1400_write_reg(cd, CD1400_CAR, mp->mp_channel); */
1282
1283 /* set transmit speed */
1284 if( t->c_ospeed ) {
1285 cd1400_write_reg(cd, CD1400_TCOR, tcor);
1286 cd1400_write_reg(cd, CD1400_TBPR, tbpr);
1287 }
1288
1289 /* set receive speed */
1290 if( t->c_ispeed ) {
1291 cd1400_write_reg(cd, CD1400_RCOR, rcor);
1292 cd1400_write_reg(cd, CD1400_RBPR, rbpr);
1293 }
1294
1295 /* enable transmitting and receiving on this channel */
1296 opt = CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN | CD1400_CCR_RCVEN;
1297 cd1400_write_ccr(cd, opt);
1298
1299 /* set parity, data and stop bits */
1300 opt = 0;
1301 if( ISSET(t->c_cflag, PARENB) )
1302 opt |= (ISSET(t->c_cflag, PARODD) ? CD1400_COR1_PARODD : CD1400_COR1_PARNORMAL);
1303
1304 if( !ISSET(t->c_iflag, INPCK) )
1305 opt |= CD1400_COR1_NOINPCK; /* no parity checking */
1306
1307 if( ISSET(t->c_cflag, CSTOPB) )
1308 opt |= CD1400_COR1_STOP2;
1309
1310 switch( t->c_cflag & CSIZE ) {
1311 case CS5:
1312 opt |= CD1400_COR1_CS5;
1313 break;
1314
1315 case CS6:
1316 opt |= CD1400_COR1_CS6;
1317 break;
1318
1319 case CS7:
1320 opt |= CD1400_COR1_CS7;
1321 break;
1322
1323 default:
1324 opt |= CD1400_COR1_CS8;
1325 break;
1326 }
1327
1328 cd1400_write_reg(cd, CD1400_COR1, opt);
1329
1330 /*
1331 * enable Embedded Transmit Commands (for breaks)
1332 * use the CD1400 automatic CTS flow control if CRTSCTS is set
1333 */
1334 opt = CD1400_COR2_ETC;
1335 if( ISSET(t->c_cflag, CRTSCTS) ) opt |= CD1400_COR2_CCTS_OFLOW;
1336 cd1400_write_reg(cd, CD1400_COR2, opt);
1337
1338 cd1400_write_reg(cd, CD1400_COR3, MTTY_RX_FIFO_THRESHOLD);
1339
1340 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR1 | CD1400_CCR_COR2 | CD1400_CCR_COR3);
1341
1342 cd1400_write_reg(cd, CD1400_COR4, CD1400_COR4_PFO_EXCEPTION);
1343 cd1400_write_reg(cd, CD1400_COR5, 0);
1344
1345 /*
1346 * if automatic RTS handshaking enabled, set DTR threshold
1347 * (RTS and DTR lines are switched, CD1400 thinks its DTR)
1348 */
1349 if( ISSET(t->c_cflag, CRTSCTS) )
1350 mcor1 = MTTY_RX_DTR_THRESHOLD;
1351
1352 /* set up `carrier detect' interrupts */
1353 if( cd->cd_parmode ) {
1354 SET(mcor1, CD1400_MCOR1_DSRzd);
1355 SET(mcor2, CD1400_MCOR2_DSRod);
1356 } else {
1357 SET(mcor1, CD1400_MCOR1_CDzd);
1358 SET(mcor2, CD1400_MCOR2_CDod);
1359 }
1360
1361 cd1400_write_reg(cd, CD1400_MCOR1, mcor1);
1362 cd1400_write_reg(cd, CD1400_MCOR2, mcor2);
1363
1364 /* receive timeout 2ms */
1365 cd1400_write_reg(cd, CD1400_RTPR, 2);
1366
1367 splx(s);
1368 return(0);
1369 }
1370
1371 /************************************************************************
1372 *
1373 * MBPP Routines
1374 *
1375 * mbpp_match match one mbpp device
1376 * mbpp_attach attach mbpp devices
1377 * mbppopen open mbpp device
1378 * mbppclose close mbpp device
1379 * mbppioctl do ioctl on mbpp
1380 * mbpp_rw general rw routine
1381 * mbpp_timeout rw timeout
1382 * mbpp_start rw start after delay
1383 * mbpp_send send data
1384 * mbpp_recv recv data
1385 */
1386
1387 int
1388 mbpp_match(device_t parent, cfdata_t cf, void *args)
1389 {
1390 struct magma_softc *sc = device_private(parent);
1391
1392 return( args == mbpp_match && sc->ms_board->mb_npar && sc->ms_mbpp == NULL );
1393 }
1394
1395 void
1396 mbpp_attach(device_t parent, device_t dev, void *args)
1397 {
1398 struct magma_softc *sc = device_private(parent);
1399 struct mbpp_softc *ms = device_private(dev);
1400 struct mbpp_port *mp;
1401 int port;
1402
1403 sc->ms_mbpp = ms;
1404 dprintf((" addr %p", ms));
1405
1406 for( port = 0 ; port < sc->ms_board->mb_npar ; port++ ) {
1407 mp = &ms->ms_port[port];
1408
1409 callout_init(&mp->mp_timeout_ch, 0);
1410 callout_init(&mp->mp_start_ch, 0);
1411
1412 if( sc->ms_ncd1190 )
1413 mp->mp_cd1190 = &sc->ms_cd1190[port];
1414 else
1415 mp->mp_cd1400 = &sc->ms_cd1400[0];
1416 }
1417
1418 ms->ms_nports = port;
1419 printf(": %d port%s\n", port, port == 1 ? "" : "s");
1420 }
1421
1422 /*
1423 * open routine. returns zero if successful, else error code
1424 */
1425 int
1426 mbppopen(dev_t dev, int flags, int mode, struct lwp *l)
1427 {
1428 int card = MAGMA_CARD(dev);
1429 int port = MAGMA_PORT(dev);
1430 struct mbpp_softc *ms;
1431 struct mbpp_port *mp;
1432 int s;
1433
1434 if ((ms = device_lookup_private(&mbpp_cd, card)) == NULL
1435 || port >= ms->ms_nports )
1436 return(ENXIO);
1437
1438 mp = &ms->ms_port[port];
1439
1440 s = spltty();
1441 if( ISSET(mp->mp_flags, MBPPF_OPEN) ) {
1442 splx(s);
1443 return(EBUSY);
1444 }
1445 SET(mp->mp_flags, MBPPF_OPEN);
1446 splx(s);
1447
1448 /* set defaults */
1449 mp->mp_burst = MBPP_BURST;
1450 mp->mp_timeout = mbpp_mstohz(MBPP_TIMEOUT);
1451 mp->mp_delay = mbpp_mstohz(MBPP_DELAY);
1452
1453 /* init chips */
1454 if( mp->mp_cd1400 ) { /* CD1400 */
1455 struct cd1400 *cd = mp->mp_cd1400;
1456
1457 /* set up CD1400 channel */
1458 s = spltty();
1459 cd1400_write_reg(cd, CD1400_CAR, 0);
1460 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET);
1461 cd1400_write_reg(cd, CD1400_LIVR, (1<<3));
1462 splx(s);
1463 } else { /* CD1190 */
1464 mp->mp_flags = 0;
1465 return (ENXIO);
1466 }
1467
1468 return (0);
1469 }
1470
1471 /*
1472 * close routine. returns zero if successful, else error code
1473 */
1474 int
1475 mbppclose(dev_t dev, int flag, int mode, struct lwp *l)
1476 {
1477 struct mbpp_softc *ms = device_lookup_private(&mbpp_cd,
1478 MAGMA_CARD(dev));
1479 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1480
1481 mp->mp_flags = 0;
1482 return(0);
1483 }
1484
1485 /*
1486 * ioctl routine
1487 */
1488 int
1489 mbppioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l)
1490 {
1491 struct mbpp_softc *ms = device_lookup_private(&mbpp_cd,
1492 MAGMA_CARD(dev));
1493 struct mbpp_port *mp = &ms->ms_port[MAGMA_PORT(dev)];
1494 struct mbpp_param *bp;
1495 int error = 0;
1496 int s;
1497
1498 switch(cmd) {
1499 case MBPPIOCSPARAM:
1500 bp = (struct mbpp_param *)data;
1501 if( bp->bp_burst < MBPP_BURST_MIN || bp->bp_burst > MBPP_BURST_MAX ||
1502 bp->bp_delay < MBPP_DELAY_MIN || bp->bp_delay > MBPP_DELAY_MIN ) {
1503 error = EINVAL;
1504 } else {
1505 mp->mp_burst = bp->bp_burst;
1506 mp->mp_timeout = mbpp_mstohz(bp->bp_timeout);
1507 mp->mp_delay = mbpp_mstohz(bp->bp_delay);
1508 }
1509 break;
1510 case MBPPIOCGPARAM:
1511 bp = (struct mbpp_param *)data;
1512 bp->bp_burst = mp->mp_burst;
1513 bp->bp_timeout = mbpp_hztoms(mp->mp_timeout);
1514 bp->bp_delay = mbpp_hztoms(mp->mp_delay);
1515 break;
1516 case MBPPIOCGSTAT:
1517 /* XXX make this more generic */
1518 s = spltty();
1519 cd1400_write_reg(mp->mp_cd1400, CD1400_CAR, 0);
1520 *(int *)data = cd1400_read_reg(mp->mp_cd1400, CD1400_PSVR);
1521 splx(s);
1522 break;
1523 default:
1524 error = ENOTTY;
1525 }
1526
1527 return(error);
1528 }
1529
1530 int
1531 mbpp_rw(dev_t dev, struct uio *uio, int flag)
1532 {
1533 int card = MAGMA_CARD(dev);
1534 int port = MAGMA_PORT(dev);
1535 struct mbpp_softc *ms = device_lookup_private(&mbpp_cd, card);
1536 struct mbpp_port *mp = &ms->ms_port[port];
1537 char *buffer, *ptr;
1538 int buflen, cnt, len;
1539 int s, error = 0;
1540 int gotdata = 0;
1541
1542 if( uio->uio_resid == 0 )
1543 return(0);
1544
1545 buflen = min(uio->uio_resid, mp->mp_burst);
1546 buffer = malloc(buflen, M_DEVBUF, M_WAITOK);
1547 if( buffer == NULL )
1548 return(ENOMEM);
1549
1550 SET(mp->mp_flags, MBPPF_UIO);
1551
1552 /*
1553 * start timeout, if needed
1554 */
1555 if( mp->mp_timeout > 0 ) {
1556 SET(mp->mp_flags, MBPPF_TIMEOUT);
1557 callout_reset(&mp->mp_timeout_ch, mp->mp_timeout,
1558 mbpp_timeout, mp);
1559 }
1560
1561 len = cnt = 0;
1562 while( uio->uio_resid > 0 ) {
1563 len = min(buflen, uio->uio_resid);
1564 ptr = buffer;
1565
1566 if( uio->uio_rw == UIO_WRITE ) {
1567 error = uiomove(ptr, len, uio);
1568 if( error ) break;
1569 }
1570 again: /* goto bad */
1571 /* timed out? */
1572 if( !ISSET(mp->mp_flags, MBPPF_UIO) )
1573 break;
1574
1575 /*
1576 * perform the operation
1577 */
1578 if( uio->uio_rw == UIO_WRITE ) {
1579 cnt = mbpp_send(mp, ptr, len);
1580 } else {
1581 cnt = mbpp_recv(mp, ptr, len);
1582 }
1583
1584 if( uio->uio_rw == UIO_READ ) {
1585 if( cnt ) {
1586 error = uiomove(ptr, cnt, uio);
1587 if( error ) break;
1588 gotdata++;
1589 }
1590 else if( gotdata ) /* consider us done */
1591 break;
1592 }
1593
1594 /* timed out? */
1595 if( !ISSET(mp->mp_flags, MBPPF_UIO) )
1596 break;
1597
1598 /*
1599 * poll delay?
1600 */
1601 if( mp->mp_delay > 0 ) {
1602 s = splsoftclock();
1603 SET(mp->mp_flags, MBPPF_DELAY);
1604 callout_reset(&mp->mp_start_ch, mp->mp_delay,
1605 mbpp_start, mp);
1606 error = tsleep(mp, PCATCH | PZERO, "mbppdelay", 0);
1607 splx(s);
1608 if( error ) break;
1609 }
1610
1611 /*
1612 * don't call uiomove again until we used all the data we grabbed
1613 */
1614 if( uio->uio_rw == UIO_WRITE && cnt != len ) {
1615 ptr += cnt;
1616 len -= cnt;
1617 cnt = 0;
1618 goto again;
1619 }
1620 }
1621
1622 /*
1623 * clear timeouts
1624 */
1625 s = splsoftclock();
1626 if( ISSET(mp->mp_flags, MBPPF_TIMEOUT) ) {
1627 callout_stop(&mp->mp_timeout_ch);
1628 CLR(mp->mp_flags, MBPPF_TIMEOUT);
1629 }
1630 if( ISSET(mp->mp_flags, MBPPF_DELAY) ) {
1631 callout_stop(&mp->mp_start_ch);
1632 CLR(mp->mp_flags, MBPPF_DELAY);
1633 }
1634 splx(s);
1635
1636 /*
1637 * adjust for those chars that we uiomoved but never actually wrote
1638 */
1639 if( uio->uio_rw == UIO_WRITE && cnt != len ) {
1640 uio->uio_resid += (len - cnt);
1641 }
1642
1643 free(buffer, M_DEVBUF);
1644 return(error);
1645 }
1646
1647 void
1648 mbpp_timeout(void *arg)
1649 {
1650 struct mbpp_port *mp = arg;
1651
1652 CLR(mp->mp_flags, MBPPF_UIO | MBPPF_TIMEOUT);
1653 wakeup(mp);
1654 }
1655
1656 void
1657 mbpp_start(void *arg)
1658 {
1659 struct mbpp_port *mp = arg;
1660
1661 CLR(mp->mp_flags, MBPPF_DELAY);
1662 wakeup(mp);
1663 }
1664
1665 int
1666 mbpp_send(struct mbpp_port *mp, void *ptr, int len)
1667 {
1668 int s;
1669 struct cd1400 *cd = mp->mp_cd1400;
1670
1671 /* set up io information */
1672 mp->mp_ptr = ptr;
1673 mp->mp_cnt = len;
1674
1675 /* start transmitting */
1676 s = spltty();
1677 if( cd ) {
1678 cd1400_write_reg(cd, CD1400_CAR, 0);
1679
1680 /* output strobe width ~1microsecond */
1681 cd1400_write_reg(cd, CD1400_TBPR, 10);
1682
1683 /* enable channel */
1684 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTEN);
1685 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_TXRDY);
1686 }
1687
1688 /* ZZzzz... */
1689 tsleep(mp, PCATCH | PZERO, "mbpp_send", 0);
1690
1691 /* stop transmitting */
1692 if( cd ) {
1693 cd1400_write_reg(cd, CD1400_CAR, 0);
1694
1695 /* disable transmitter */
1696 cd1400_write_reg(cd, CD1400_SRER, 0);
1697 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_XMTDIS);
1698
1699 /* flush fifo */
1700 cd1400_write_ccr(cd, CD1400_CCR_CMDRESET | CD1400_CCR_FTF);
1701 }
1702 splx(s);
1703
1704 /* return number of chars sent */
1705 return(len - mp->mp_cnt);
1706 }
1707
1708 int
1709 mbpp_recv(struct mbpp_port *mp, void *ptr, int len)
1710 {
1711 int s;
1712 struct cd1400 *cd = mp->mp_cd1400;
1713
1714 /* set up io information */
1715 mp->mp_ptr = ptr;
1716 mp->mp_cnt = len;
1717
1718 /* start receiving */
1719 s = spltty();
1720 if( cd ) {
1721 int rcor, rbpr;
1722
1723 cd1400_write_reg(cd, CD1400_CAR, 0);
1724
1725 /* input strobe at 100kbaud (10microseconds) */
1726 cd1400_compute_baud(100000, cd->cd_clock, &rcor, &rbpr);
1727 cd1400_write_reg(cd, CD1400_RCOR, rcor);
1728 cd1400_write_reg(cd, CD1400_RBPR, rbpr);
1729
1730 /* rx threshold */
1731 cd1400_write_reg(cd, CD1400_COR3, MBPP_RX_FIFO_THRESHOLD);
1732 cd1400_write_ccr(cd, CD1400_CCR_CMDCORCHG | CD1400_CCR_COR3);
1733
1734 /* enable channel */
1735 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVEN);
1736 cd1400_write_reg(cd, CD1400_SRER, CD1400_SRER_RXDATA);
1737 }
1738
1739 /* ZZzzz... */
1740 tsleep(mp, PCATCH | PZERO, "mbpp_recv", 0);
1741
1742 /* stop receiving */
1743 if( cd ) {
1744 cd1400_write_reg(cd, CD1400_CAR, 0);
1745
1746 /* disable receiving */
1747 cd1400_write_reg(cd, CD1400_SRER, 0);
1748 cd1400_write_ccr(cd, CD1400_CCR_CMDCHANCTL | CD1400_CCR_RCVDIS);
1749 }
1750 splx(s);
1751
1752 /* return number of chars received */
1753 return(len - mp->mp_cnt);
1754 }
1755
1756 int
1757 mbpp_hztoms(int h)
1758 {
1759 int m = h;
1760
1761 if( m > 0 )
1762 m = m * 1000 / hz;
1763 return(m);
1764 }
1765
1766 int
1767 mbpp_mstohz(int m)
1768 {
1769 int h = m;
1770
1771 if( h > 0 ) {
1772 h = h * hz / 1000;
1773 if( h == 0 )
1774 h = 1000 / hz;
1775 }
1776 return(h);
1777 }
1778
1779 #endif /* NMAGMA */
NetBSD on the FriendlyARM MINI2440