sys/dev/sbus/qereg.h

   1 /*      $NetBSD: qereg.h,v 1.6 2008/04/28 20:23:57 martin Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1999 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Paul Kranenburg.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * Copyright (c) 1998 Jason L. Wright.
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  * 1. Redistributions of source code must retain the above copyright
  40  *    notice, this list of conditions and the following disclaimer.
  41  * 2. Redistributions in binary form must reproduce the above copyright
  42  *    notice, this list of conditions and the following disclaimer in the
  43  *    documentation and/or other materials provided with the distribution.
  44  * 3. The name of the authors may not be used to endorse or promote products
  45  *    derived from this software without specific prior written permission.
  46  *
  47  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
  48  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  49  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  50  * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  51  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  52  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  53  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  54  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  55  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  56  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  57  */
  58
  59 /*
  60  * QE Channel registers
  61  */
  62 #if 0
  63 struct qe_cregs {
  64         uint32_t ctrl;          /* control */
  65         uint32_t stat;          /* status */
  66         uint32_t rxds;          /* rx descriptor ring ptr */
  67         uint32_t txds;          /* tx descriptor ring ptr */
  68         uint32_t rimask;        /* rx interrupt mask */
  69         uint32_t timask;        /* tx interrupt mask */
  70         uint32_t qmask;         /* qec error interrupt mask */
  71         uint32_t mmask;         /* mace error interrupt mask */
  72         uint32_t rxwbufptr;     /* local memory rx write ptr */
  73         uint32_t rxrbufptr;     /* local memory rx read ptr */
  74         uint32_t txwbufptr;     /* local memory tx write ptr */
  75         uint32_t txrbufptr;     /* local memory tx read ptr */
  76         uint32_t ccnt;          /* collision counter */
  77         uint32_t pipg;          /* inter-frame gap */
  78 };
  79 #endif
  80 /* register indices: */
  81 #define QE_CRI_CTRL     (0*4)
  82 #define QE_CRI_STAT     (1*4)
  83 #define QE_CRI_RXDS     (2*4)
  84 #define QE_CRI_TXDS     (3*4)
  85 #define QE_CRI_RIMASK   (4*4)
  86 #define QE_CRI_TIMASK   (5*4)
  87 #define QE_CRI_QMASK    (6*4)
  88 #define QE_CRI_MMASK    (7*4)
  89 #define QE_CRI_RXWBUF   (8*4)
  90 #define QE_CRI_RXRBUF   (9*4)
  91 #define QE_CRI_TXWBUF   (10*4)
  92 #define QE_CRI_TXRBUF   (11*4)
  93 #define QE_CRI_CCNT     (12*4)
  94 #define QE_CRI_PIPG     (13*4)
  95
  96 /* qe_cregs.ctrl: control. */
  97 #define QE_CR_CTRL_RXOFF        0x00000004      /* disable receiver */
  98 #define QE_CR_CTRL_RESET        0x00000002      /* reset this channel */
  99 #define QE_CR_CTRL_TWAKEUP      0x00000001      /* tx DMA wakeup */
 100
 101 /* qe_cregs.stat: status. */
 102 #define QE_CR_STAT_EDEFER       0x10000000      /* excessive defers */
 103 #define QE_CR_STAT_CLOSS        0x08000000      /* loss of carrier */
 104 #define QE_CR_STAT_ERETRIES     0x04000000      /* >16 retries */
 105 #define QE_CR_STAT_LCOLL        0x02000000      /* late tx collision */
 106 #define QE_CR_STAT_FUFLOW       0x01000000      /* fifo underflow */
 107 #define QE_CR_STAT_JERROR       0x00800000      /* jabber error */
 108 #define QE_CR_STAT_BERROR       0x00400000      /* babble error */
 109 #define QE_CR_STAT_TXIRQ        0x00200000      /* tx interrupt */
 110 #define QE_CR_STAT_TCCOFLOW     0x00100000      /* tx collision cntr expired */
 111 #define QE_CR_STAT_TXDERROR     0x00080000      /* tx descriptor is bad */
 112 #define QE_CR_STAT_TXLERR       0x00040000      /* tx late error */
 113 #define QE_CR_STAT_TXPERR       0x00020000      /* tx parity error */
 114 #define QE_CR_STAT_TXSERR       0x00010000      /* tx sbus error ack */
 115 #define QE_CR_STAT_RCCOFLOW     0x00001000      /* rx collision cntr expired */
 116 #define QE_CR_STAT_RUOFLOW      0x00000800      /* rx runt counter expired */
 117 #define QE_CR_STAT_MCOFLOW      0x00000400      /* rx missed counter expired */
 118 #define QE_CR_STAT_RXFOFLOW     0x00000200      /* rx fifo over flow */
 119 #define QE_CR_STAT_RLCOLL       0x00000100      /* rx late collision */
 120 #define QE_CR_STAT_FCOFLOW      0x00000080      /* rx frame counter expired */
 121 #define QE_CR_STAT_CECOFLOW     0x00000040      /* rx crc error cntr expired */
 122 #define QE_CR_STAT_RXIRQ        0x00000020      /* rx interrupt */
 123 #define QE_CR_STAT_RXDROP       0x00000010      /* rx dropped packet */
 124 #define QE_CR_STAT_RXSMALL      0x00000008      /* rx buffer too small */
 125 #define QE_CR_STAT_RXLERR       0x00000004      /* rx late error */
 126 #define QE_CR_STAT_RXPERR       0x00000002      /* rx parity error */
 127 #define QE_CR_STAT_RXSERR       0x00000001      /* rx sbus error ack */
 128 #define QE_CR_STAT_BITS         "\177\020"                              \
 129                         "b\0RXSERR\0b\1RXPERR\0b\2RXLERR\0"             \
 130                         "b\3RXSMALL\0b\4RXDROP\0b\5RXIRQ\0"             \
 131                         "b\6CECOFLOW\0b\7FCOFLOW\0b\10RLCOLL\0"         \
 132                         "b\11RXFOFLOW\0b\12MCOFLOW\0b\13RUOFLOW\0"      \
 133                         "b\14RCCOFLOW\0b\20TXSERR\0b\21TXPERR\0"        \
 134                         "b\22TXLERR\0b\23TXDERROR\0b\24TCCOFLOW\0"      \
 135                         "b\25TXIRQ\0b\26BERROR\0b\27JERROR\0"           \
 136                         "b\30FUFLOW\0b\31LCOLL\0b\32ERETRIES\0"         \
 137                         "b\33CLOSS\0b\34EDEFER\0\0"
 138
 139 /*
 140  * Errors: all status bits except for TX/RX IRQ
 141  */
 142 #define QE_CR_STAT_ALLERRORS    \
 143         ( QE_CR_STAT_EDEFER   | QE_CR_STAT_CLOSS    | QE_CR_STAT_ERETRIES \
 144         | QE_CR_STAT_LCOLL    | QE_CR_STAT_FUFLOW   | QE_CR_STAT_JERROR \
 145         | QE_CR_STAT_BERROR   | QE_CR_STAT_TCCOFLOW | QE_CR_STAT_TXDERROR \
 146         | QE_CR_STAT_TXLERR   | QE_CR_STAT_TXPERR   | QE_CR_STAT_TXSERR \
 147         | QE_CR_STAT_RCCOFLOW | QE_CR_STAT_RUOFLOW  | QE_CR_STAT_MCOFLOW \
 148         | QE_CR_STAT_RXFOFLOW | QE_CR_STAT_RLCOLL   | QE_CR_STAT_FCOFLOW \
 149         | QE_CR_STAT_CECOFLOW | QE_CR_STAT_RXDROP   | QE_CR_STAT_RXSMALL \
 150         | QE_CR_STAT_RXLERR   | QE_CR_STAT_RXPERR   | QE_CR_STAT_RXSERR)
 151
 152 /* qe_cregs.qmask: qec error interrupt mask. */
 153 #define QE_CR_QMASK_COFLOW      0x00100000      /* collision cntr overflow */
 154 #define QE_CR_QMASK_TXDERROR    0x00080000      /* tx descriptor error */
 155 #define QE_CR_QMASK_TXLERR      0x00040000      /* tx late error */
 156 #define QE_CR_QMASK_TXPERR      0x00020000      /* tx parity error */
 157 #define QE_CR_QMASK_TXSERR      0x00010000      /* tx sbus error ack */
 158 #define QE_CR_QMASK_RXDROP      0x00000010      /* rx packet dropped */
 159 #define QE_CR_QMASK_RXSMALL     0x00000008      /* rx buffer too small */
 160 #define QE_CR_QMASK_RXLERR      0x00000004      /* rx late error */
 161 #define QE_CR_QMASK_RXPERR      0x00000002      /* rx parity error */
 162 #define QE_CR_QMASK_RXSERR      0x00000001      /* rx sbus error ack */
 163
 164 /* qe_cregs.mmask: MACE error interrupt mask. */
 165 #define QE_CR_MMASK_EDEFER      0x10000000      /* excess defer */
 166 #define QE_CR_MMASK_CLOSS       0x08000000      /* carrier loss */
 167 #define QE_CR_MMASK_ERETRY      0x04000000      /* excess retry */
 168 #define QE_CR_MMASK_LCOLL       0x02000000      /* late collision error */
 169 #define QE_CR_MMASK_UFLOW       0x01000000      /* underflow */
 170 #define QE_CR_MMASK_JABBER      0x00800000      /* jabber error */
 171 #define QE_CR_MMASK_BABBLE      0x00400000      /* babble error */
 172 #define QE_CR_MMASK_OFLOW       0x00000800      /* overflow */
 173 #define QE_CR_MMASK_RXCOLL      0x00000400      /* rx coll-cntr overflow */
 174 #define QE_CR_MMASK_RPKT        0x00000200      /* runt pkt overflow */
 175 #define QE_CR_MMASK_MPKT        0x00000100      /* missed pkt overflow */
 176
 177 /* qe_cregs.pipg: inter-frame gap. */
 178 #define QE_CR_PIPG_TENAB        0x00000020      /* enable throttle */
 179 #define QE_CR_PIPG_MMODE        0x00000010      /* manual mode */
 180 #define QE_CR_PIPG_WMASK        0x0000000f      /* sbus wait mask */
 181
 182 /*
 183  * MACE registers
 184  */
 185 #if 0
 186 struct qe_mregs {
 187         uint8_t rcvfifo;        /* [0]  receive fifo */
 188         uint8_t xmtfifo;        /* [1]  transmit fifo */
 189         uint8_t xmtfc;          /* [2]  transmit frame control */
 190         uint8_t xmtfs;          /* [3]  transmit frame status */
 191         uint8_t xmtrc;          /* [4]  tx retry count */
 192         uint8_t rcvfc;          /* [5]  receive frame control */
 193         uint8_t rcvfs;          /* [6]  receive frame status */
 194         uint8_t fifofc;         /* [7]  fifo frame count */
 195         uint8_t ir;             /* [8]  interrupt register */
 196         uint8_t imr;            /* [9]  interrupt mask register */
 197         uint8_t pr;             /* [10] poll register */
 198         uint8_t biucc;          /* [11] biu config control */
 199         uint8_t fifocc;         /* [12] fifo config control */
 200         uint8_t maccc;          /* [13] mac config control */
 201         uint8_t plscc;          /* [14] pls config control */
 202         uint8_t phycc;          /* [15] phy config control */
 203         uint8_t chipid1;        /* [16] chipid, low byte */
 204         uint8_t chipid2;        /* [17] chipid, high byte */
 205         uint8_t iac;            /* [18] internal address config */
 206         uint8_t _reserved0;     /* [19] reserved */
 207         uint8_t ladrf;          /* [20] logical address filter */
 208         uint8_t padr;           /* [21] physical address */
 209         uint8_t _reserved1;     /* [22] reserved */
 210         uint8_t _reserved2;     /* [23] reserved */
 211         uint8_t mpc;            /* [24] missed packet count */
 212         uint8_t _reserved3;     /* [25] reserved */
 213         uint8_t rntpc;          /* [26] runt packet count */
 214         uint8_t rcvcc;          /* [27] receive collision count */
 215         uint8_t _reserved4;     /* [28] reserved */
 216         uint8_t utr;            /* [29] user test register */
 217         uint8_t rtr1;           /* [30] reserved test register 1 */
 218         uint8_t rtr2;           /* [31] reserved test register 2 */
 219 };
 220 #endif
 221 /* register indices: */
 222 #define QE_MRI_RCVFIFO  0       /* receive fifo */
 223 #define QE_MRI_XMTFIFO  1       /* transmit fifo */
 224 #define QE_MRI_XMTFC    2       /* transmit frame control */
 225 #define QE_MRI_XMTFS    3       /* transmit frame status */
 226 #define QE_MRI_XMTRC    4       /* tx retry count */
 227 #define QE_MRI_RCVFC    5       /* receive frame control */
 228 #define QE_MRI_RCVFS    6       /* receive frame status */
 229 #define QE_MRI_FIFOFC   7       /* fifo frame count */
 230 #define QE_MRI_IR       8       /* interrupt register */
 231 #define QE_MRI_IMR      9       /* interrupt mask register */
 232 #define QE_MRI_PR       10      /* poll register */
 233 #define QE_MRI_BIUCC    11      /* biu config control */
 234 #define QE_MRI_FIFOCC   12      /* fifo config control */
 235 #define QE_MRI_MACCC    13      /* mac config control */
 236 #define QE_MRI_PLSCC    14      /* pls config control */
 237 #define QE_MRI_PHYCC    15      /* phy config control */
 238 #define QE_MRI_CHIPID1  16      /* chipid, low byte */
 239 #define QE_MRI_CHIPID2  17      /* chipid, high byte */
 240 #define QE_MRI_IAC      18      /* internal address config */
 241 #define QE_MRI_LADRF    20      /* logical address filter */
 242 #define QE_MRI_PADR     21      /* physical address */
 243 #define QE_MRI_MPC      24      /* missed packet count */
 244 #define QE_MRI_RNTPC    26      /* runt packet count */
 245 #define QE_MRI_RCVCC    27      /* receive collision count */
 246 #define QE_MRI_UTR      29      /* user test register */
 247 #define QE_MRI_RTR1     30      /* reserved test register 1 */
 248 #define QE_MRI_RTR2     31      /* reserved test register 2 */
 249
 250 /* qe_mregs.xmtfc: transmit frame control. */
 251 #define QE_MR_XMTFC_DRETRY      0x80            /* disable retries */
 252 #define QE_MR_XMTFC_DXMTFCS     0x08            /* disable tx fcs */
 253 #define QE_MR_XMTFC_APADXMT     0x01            /* enable auto padding */
 254
 255 /* qe_mregs.xmtfs: transmit frame status. */
 256 #define QE_MR_XMTFS_XMTSV       0x80            /* tx valid */
 257 #define QE_MR_XMTFS_UFLO        0x40            /* tx underflow */
 258 #define QE_MR_XMTFS_LCOL        0x20            /* tx late collision */
 259 #define QE_MR_XMTFS_MORE        0x10            /* tx > 1 retries */
 260 #define QE_MR_XMTFS_ONE         0x08            /* tx 1 retry */
 261 #define QE_MR_XMTFS_DEFER       0x04            /* tx pkt deferred */
 262 #define QE_MR_XMTFS_LCAR        0x02            /* tx carrier lost */
 263 #define QE_MR_XMTFS_RTRY        0x01            /* tx retry error */
 264
 265 /* qe_mregs.xmtrc: transmit retry count. */
 266 #define QE_MR_XMTRC_EXDEF       0x80            /* tx excess defers */
 267 #define QE_MR_XMTRC_XMTRC       0x0f            /* tx retry count mask */
 268
 269 /* qe_mregs.rcvfc: receive frame control. */
 270 #define QE_MR_RCVFC_LLRCV       0x08            /* rx low latency */
 271 #define QE_MR_RCVFC_MR          0x04            /* rx addr match/reject */
 272 #define QE_MR_RCVFC_ASTRPRCV    0x01            /* rx auto strip */
 273
 274 /* qe_mregs.rcvfs: receive frame status. */
 275 #define QE_MR_RCVFS_OFLO        0x80            /* rx overflow */
 276 #define QE_MR_RCVFS_CLSN        0x40            /* rx late collision */
 277 #define QE_MR_RCVFS_FRAM        0x20            /* rx framing error */
 278 #define QE_MR_RCVFS_FCS         0x10            /* rx fcs error */
 279 #define QE_MR_RCVFS_RCVCNT      0x0f            /* rx msg byte count mask */
 280
 281 /* qe_mregs.fifofc: fifo frame count. */
 282 #define QE_MR_FIFOFC_RCVFC      0xf0            /* rx fifo frame count */
 283 #define QE_MR_FIFOFC_XMTFC      0x0f            /* tx fifo frame count */
 284
 285 /* qe_mregs.ir: interrupt register. */
 286 #define QE_MR_IR_JAB            0x80            /* jabber error */
 287 #define QE_MR_IR_BABL           0x40            /* babble error */
 288 #define QE_MR_IR_CERR           0x20            /* collision error */
 289 #define QE_MR_IR_RCVCCO         0x10            /* collision cnt overflow */
 290 #define QE_MR_IR_RNTPCO         0x08            /* runt pkt cnt overflow */
 291 #define QE_MR_IR_MPCO           0x04            /* miss pkt cnt overflow */
 292 #define QE_MR_IR_RCVINT         0x02            /* packet received */
 293 #define QE_MR_IR_XMTINT         0x01            /* packet transmitted */
 294
 295 /* qe_mregs.imr: interrupt mask register. */
 296 #define QE_MR_IMR_JABM          0x80            /* jabber errors */
 297 #define QE_MR_IMR_BABLM         0x40            /* babble errors */
 298 #define QE_MR_IMR_CERRM         0x20            /* collision errors */
 299 #define QE_MR_IMR_RCVCCOM       0x10            /* rx collision count oflow */
 300 #define QE_MR_IMR_RNTPCOM       0x08            /* runt pkt cnt ovrflw */
 301 #define QE_MR_IMR_MPCOM         0x04            /* miss pkt cnt ovrflw */
 302 #define QE_MR_IMR_RCVINTM       0x02            /* rx interrupts */
 303 #define QE_MR_IMR_XMTINTM       0x01            /* tx interrupts */
 304
 305 /* qe_mregs.pr: poll register. */
 306 #define QE_MR_PR_XMTSV          0x80            /* tx status is valid */
 307 #define QE_MR_PR_TDTREQ         0x40            /* tx data xfer request */
 308 #define QE_MR_PR_RDTREQ         0x20            /* rx data xfer request */
 309
 310 /* qe_mregs.biucc: biu config control. */
 311 #define QE_MR_BIUCC_BSWAP       0x40            /* byte swap */
 312 #define QE_MR_BIUCC_4TS         0x00            /* 4byte xmit start point */
 313 #define QE_MR_BIUCC_16TS        0x10            /* 16byte xmit start point */
 314 #define QE_MR_BIUCC_64TS        0x20            /* 64byte xmit start point */
 315 #define QE_MR_BIUCC_112TS       0x30            /* 112byte xmit start point */
 316 #define QE_MR_BIUCC_SWRST       0x01            /* sw-reset mace */
 317
 318 /* qe_mregs.fifocc: fifo config control. */
 319 #define QE_MR_FIFOCC_TXF8       0x00            /* tx fifo 8 write cycles */
 320 #define QE_MR_FIFOCC_TXF32      0x80            /* tx fifo 32 write cycles */
 321 #define QE_MR_FIFOCC_TXF16      0x40            /* tx fifo 16 write cycles */
 322 #define QE_MR_FIFOCC_RXF64      0x20            /* rx fifo 64 write cycles */
 323 #define QE_MR_FIFOCC_RXF32      0x10            /* rx fifo 32 write cycles */
 324 #define QE_MR_FIFOCC_RXF16      0x00            /* rx fifo 16 write cycles */
 325 #define QE_MR_FIFOCC_TFWU       0x08            /* tx fifo watermark update */
 326 #define QE_MR_FIFOCC_RFWU       0x04            /* rx fifo watermark update */
 327 #define QE_MR_FIFOCC_XMTBRST    0x02            /* tx burst enable */
 328 #define QE_MR_FIFOCC_RCVBRST    0x01            /* rx burst enable */
 329
 330 /* qe_mregs.maccc: mac config control. */
 331 #define QE_MR_MACCC_PROM        0x80            /* promiscuous mode enable */
 332 #define QE_MR_MACCC_DXMT2PD     0x40            /* tx 2part deferral enable */
 333 #define QE_MR_MACCC_EMBA        0x20            /* modified backoff enable */
 334 #define QE_MR_MACCC_DRCVPA      0x08            /* rx physical addr disable */
 335 #define QE_MR_MACCC_DRCVBC      0x04            /* rx broadcast disable */
 336 #define QE_MR_MACCC_ENXMT       0x02            /* enable transmitter */
 337 #define QE_MR_MACCC_ENRCV       0x01            /* enable receiver */
 338
 339 /* qe_mregs.plscc: pls config control. */
 340 #define QE_MR_PLSCC_XMTSEL      0x08            /* tx mode select */
 341 #define QE_MR_PLSCC_PORTMASK    0x06            /* port selection bits */
 342 #define  QE_MR_PLSCC_GPSI       0x06            /* use gpsi connector */
 343 #define  QE_MR_PLSCC_DAI        0x04            /* use dai connector */
 344 #define  QE_MR_PLSCC_TP         0x02            /* use twistedpair connector */
 345 #define  QE_MR_PLSCC_AUI        0x00            /* use aui connector */
 346 #define QE_MR_PLSCC_ENPLSIO     0x01            /* pls i/o enable */
 347
 348 /* qe_mregs.phycc: phy config control. */
 349 #define QE_MR_PHYCC_LNKFL       0x80            /* link fail */
 350 #define QE_MR_PHYCC_DLNKTST     0x40            /* disable link test logic */
 351 #define QE_MR_PHYCC_REVPOL      0x20            /* rx polarity */
 352 #define QE_MR_PHYCC_DAPC        0x10            /* autopolaritycorrect disab */
 353 #define QE_MR_PHYCC_LRT         0x08            /* select low threshold */
 354 #define QE_MR_PHYCC_ASEL        0x04            /* connector port auto-sel */
 355 #define QE_MR_PHYCC_RWAKE       0x02            /* remote wakeup */
 356 #define QE_MR_PHYCC_AWAKE       0x01            /* auto wakeup */
 357
 358 /* qe_mregs.iac: internal address config. */
 359 #define QE_MR_IAC_ADDRCHG       0x80            /* start address change */
 360 #define QE_MR_IAC_PHYADDR       0x04            /* physical address reset */
 361 #define QE_MR_IAC_LOGADDR       0x02            /* logical address reset */
 362
 363 /* qe_mregs.utr: user test register. */
 364 #define QE_MR_UTR_RTRE          0x80            /* enable resv test register */
 365 #define QE_MR_UTR_RTRD          0x40            /* disab resv test register */
 366 #define QE_MR_UTR_RPA           0x20            /* accept runt packets */
 367 #define QE_MR_UTR_FCOLL         0x10            /* force collision status */
 368 #define QE_MR_UTR_RCVSFCSE      0x08            /* enable fcs on rx */
 369 #define QE_MR_UTR_INTLOOPM      0x06            /* Internal loopback w/mandec */
 370 #define QE_MR_UTR_INTLOOP       0x04            /* Internal loopback */
 371 #define QE_MR_UTR_EXTLOOP       0x02            /* external loopback */
 372 #define QE_MR_UTR_NOLOOP        0x00            /* no loopback */
 373
 374 /* Buffer and Ring sizes: fixed ring size */
 375 #define QE_TX_RING_MAXSIZE      256             /* maximum tx ring size */
 376 #define QE_RX_RING_MAXSIZE      256             /* maximum rx ring size */
 377 #define QE_TX_RING_SIZE         16
 378 #define QE_RX_RING_SIZE         16
 379 #define QE_PKT_BUF_SZ           2048
 380
 381 #define MC_POLY_LE              0xedb88320      /* mcast crc, little endian */