?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / external / bsd / drm / dist / shared-core / r600_cp.c
blob2e4f607b15e23bce6df6b1bc978ad106dcaf518f
1 /* r600_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3 * Copyright 2008 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Dave Airlie <airlied@redhat.com>
27 * Alex Deucher <alexander.deucher@amd.com>
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "radeon_drm.h"
33 #include "radeon_drv.h"
34 #include "r300_reg.h"
35
36 #include "r600_microcode.h"
37
38 # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
39 # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
40
41 #define R600_PTE_VALID (1 << 0)
42 #define R600_PTE_SYSTEM (1 << 1)
43 #define R600_PTE_SNOOPED (1 << 2)
44 #define R600_PTE_READABLE (1 << 5)
45 #define R600_PTE_WRITEABLE (1 << 6)
46
47 /* MAX values used for gfx init */
48 #define R6XX_MAX_SH_GPRS 256
49 #define R6XX_MAX_TEMP_GPRS 16
50 #define R6XX_MAX_SH_THREADS 256
51 #define R6XX_MAX_SH_STACK_ENTRIES 4096
52 #define R6XX_MAX_BACKENDS 8
53 #define R6XX_MAX_BACKENDS_MASK 0xff
54 #define R6XX_MAX_SIMDS 8
55 #define R6XX_MAX_SIMDS_MASK 0xff
56 #define R6XX_MAX_PIPES 8
57 #define R6XX_MAX_PIPES_MASK 0xff
58
59 #define R7XX_MAX_SH_GPRS 256
60 #define R7XX_MAX_TEMP_GPRS 16
61 #define R7XX_MAX_SH_THREADS 256
62 #define R7XX_MAX_SH_STACK_ENTRIES 4096
63 #define R7XX_MAX_BACKENDS 8
64 #define R7XX_MAX_BACKENDS_MASK 0xff
65 #define R7XX_MAX_SIMDS 16
66 #define R7XX_MAX_SIMDS_MASK 0xffff
67 #define R7XX_MAX_PIPES 8
68 #define R7XX_MAX_PIPES_MASK 0xff
69
70 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
71 {
72 int i;
73
74 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
75
76 for (i = 0; i < dev_priv->usec_timeout; i++) {
77 int slots;
78 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
79 slots = (RADEON_READ(R600_GRBM_STATUS)
80 & R700_CMDFIFO_AVAIL_MASK);
81 else
82 slots = (RADEON_READ(R600_GRBM_STATUS)
83 & R600_CMDFIFO_AVAIL_MASK);
84 if (slots >= entries)
85 return 0;
86 DRM_UDELAY(1);
87 }
88 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
89 RADEON_READ(R600_GRBM_STATUS),
90 RADEON_READ(R600_GRBM_STATUS2));
91
92 return -EBUSY;
93 }
94
95 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
96 {
97 int i, ret;
98
99 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
100
101 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
102 ret = r600_do_wait_for_fifo(dev_priv, 8);
103 else
104 ret = r600_do_wait_for_fifo(dev_priv, 16);
105 if (ret)
106 return ret;
107 for (i = 0; i < dev_priv->usec_timeout; i++) {
108 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
109 return 0;
110 DRM_UDELAY(1);
111 }
112 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
113 RADEON_READ(R600_GRBM_STATUS),
114 RADEON_READ(R600_GRBM_STATUS2));
115
116 return -EBUSY;
117 }
118
119 void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
120 {
121 #ifdef __linux__
122 struct drm_sg_mem *entry = dev->sg;
123 int max_pages;
124 int pages;
125 int i;
126
127 if (!entry)
128 return;
129
130 #endif
131 if (gart_info->bus_addr) {
132 #ifdef __linux__
133 max_pages = (gart_info->table_size / sizeof(u64));
134 pages = (entry->pages <= max_pages)
135 ? entry->pages : max_pages;
136
137 for (i = 0; i < pages; i++) {
138 if (!entry->busaddr[i])
139 break;
140 pci_unmap_page(dev->pdev, entry->busaddr[i],
141 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
142 }
143 #endif
144 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
145 gart_info->bus_addr = 0;
146 }
147 }
148
149 /* R600 has page table setup */
150 int r600_page_table_init(struct drm_device *dev)
151 {
152 drm_radeon_private_t *dev_priv = dev->dev_private;
153 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
154 struct drm_sg_mem *entry = dev->sg;
155 int ret = 0;
156 int i, j;
157 int max_pages, pages;
158 u64 *pci_gart, page_base;
159 dma_addr_t entry_addr;
160
161 /* okay page table is available - lets rock */
162
163 /* PTEs are 64-bits */
164 pci_gart = (u64 *)gart_info->addr;
165
166 max_pages = (gart_info->table_size / sizeof(u64));
167 pages = (entry->pages <= max_pages) ? entry->pages : max_pages;
168
169 memset(pci_gart, 0, max_pages * sizeof(u64));
170
171 for (i = 0; i < pages; i++) {
172 #ifdef __linux__
173 entry->busaddr[i] = pci_map_page(dev->pdev,
174 entry->pagelist[i], 0,
175 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
176 if (entry->busaddr[i] == 0) {
177 DRM_ERROR("unable to map PCIGART pages!\n");
178 r600_page_table_cleanup(dev, gart_info);
179 goto done;
180 }
181 #endif
182 entry_addr = entry->busaddr[i];
183 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
184 page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
185 page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
186 page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
187
188 *pci_gart = page_base;
189
190 if ((i % 128) == 0)
191 DRM_DEBUG("page entry %d: 0x%016llx\n",
192 i, (unsigned long long)page_base);
193 pci_gart++;
194 entry_addr += ATI_PCIGART_PAGE_SIZE;
195 }
196 }
197 ret = 1;
198 #ifdef __linux__
199 done:
200 #endif
201 return ret;
202 }
203
204 static void r600_vm_flush_gart_range(struct drm_device *dev)
205 {
206 drm_radeon_private_t *dev_priv = dev->dev_private;
207 u32 resp, countdown = 1000;
208 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
209 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
210 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
211
212 do {
213 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
214 countdown--;
215 DRM_UDELAY(1);
216 } while (((resp & 0xf0) == 0) && countdown );
217 }
218
219 static void r600_vm_init(struct drm_device *dev)
220 {
221 drm_radeon_private_t *dev_priv = dev->dev_private;
222 /* initialise the VM to use the page table we constructed up there */
223 u32 vm_c0, i;
224 u32 mc_rd_a;
225 u32 vm_l2_cntl, vm_l2_cntl3;
226 /* okay set up the PCIE aperture type thingo */
227 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
228 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
229 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
230
231 /* setup MC RD a */
232 mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
233 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
234 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
235
236 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
237 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
238
239 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
240 RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
241
242 RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
243 RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
244
245 RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
246 RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
247
248 RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
249 RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
250
251 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
252 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
253
254 RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
255 RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
256
257 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
258 vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
259 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
260
261 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
262 vm_l2_cntl3 = R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
263 R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
264 R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
265 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
266
267 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
268
269 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
270
271 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
272
273 /* disable all other contexts */
274 for (i = 1; i < 8; i++)
275 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
276
277 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
278 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
279 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
280
281 r600_vm_flush_gart_range(dev);
282 }
283
284 /* load r600 microcode */
285 static void r600_cp_load_microcode(drm_radeon_private_t * dev_priv)
286 {
287 const u32 (*cp)[3];
288 const u32 *pfp;
289 int i;
290
291 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
292 case CHIP_R600:
293 DRM_INFO("Loading R600 Microcode\n");
294 cp = R600_cp_microcode;
295 pfp = R600_pfp_microcode;
296 break;
297 case CHIP_RV610:
298 DRM_INFO("Loading RV610 Microcode\n");
299 cp = RV610_cp_microcode;
300 pfp = RV610_pfp_microcode;
301 break;
302 case CHIP_RV630:
303 DRM_INFO("Loading RV630 Microcode\n");
304 cp = RV630_cp_microcode;
305 pfp = RV630_pfp_microcode;
306 break;
307 case CHIP_RV620:
308 DRM_INFO("Loading RV620 Microcode\n");
309 cp = RV620_cp_microcode;
310 pfp = RV620_pfp_microcode;
311 break;
312 case CHIP_RV635:
313 DRM_INFO("Loading RV635 Microcode\n");
314 cp = RV635_cp_microcode;
315 pfp = RV635_pfp_microcode;
316 break;
317 case CHIP_RV670:
318 DRM_INFO("Loading RV670 Microcode\n");
319 cp = RV670_cp_microcode;
320 pfp = RV670_pfp_microcode;
321 break;
322 case CHIP_RS780:
323 DRM_INFO("Loading RS780 Microcode\n");
324 cp = RS780_cp_microcode;
325 pfp = RS780_pfp_microcode;
326 break;
327 default:
328 return;
329 }
330
331 r600_do_cp_stop(dev_priv);
332
333 RADEON_WRITE(R600_CP_RB_CNTL,
334 R600_RB_NO_UPDATE |
335 R600_RB_BLKSZ(15) |
336 R600_RB_BUFSZ(3));
337
338 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
339 RADEON_READ(R600_GRBM_SOFT_RESET);
340 DRM_UDELAY(15000);
341 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
342
343 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
344
345 for (i = 0; i < PM4_UCODE_SIZE; i++) {
346 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][0]);
347 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][1]);
348 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][2]);
349 }
350
351 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
352 for (i = 0; i < PFP_UCODE_SIZE; i++)
353 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
354
355 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
356 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
357 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
358
359 }
360
361 static void r700_vm_init(struct drm_device *dev)
362 {
363 drm_radeon_private_t *dev_priv = dev->dev_private;
364 /* initialise the VM to use the page table we constructed up there */
365 u32 vm_c0, i;
366 u32 mc_vm_md_l1;
367 u32 vm_l2_cntl, vm_l2_cntl3;
368 /* okay set up the PCIE aperture type thingo */
369 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
370 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
371 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
372
373 mc_vm_md_l1 = R700_ENABLE_L1_TLB |
374 R700_ENABLE_L1_FRAGMENT_PROCESSING |
375 R700_SYSTEM_ACCESS_MODE_IN_SYS |
376 R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
377 R700_EFFECTIVE_L1_TLB_SIZE(5) |
378 R700_EFFECTIVE_L1_QUEUE_SIZE(5);
379
380 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
381 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
382 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
383 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
384 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
385 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
386 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
387
388 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
389 vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
390 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
391
392 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
393 vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) |
394 R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
395 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
396
397 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
398
399 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
400
401 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
402
403 /* disable all other contexts */
404 for (i = 1; i < 8; i++)
405 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
406
407 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
408 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
409 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
410
411 r600_vm_flush_gart_range(dev);
412 }
413
414 /* load r600 microcode */
415 static void r700_cp_load_microcode(drm_radeon_private_t * dev_priv)
416 {
417 const u32 *pfp;
418 const u32 *cp;
419 int i;
420
421 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
422 case CHIP_RV770:
423 DRM_INFO("Loading RV770/RV790 Microcode\n");
424 pfp = RV770_pfp_microcode;
425 cp = RV770_cp_microcode;
426 break;
427 case CHIP_RV730:
428 DRM_INFO("Loading RV730 Microcode\n");
429 pfp = RV730_pfp_microcode;
430 cp = RV730_cp_microcode;
431 break;
432 case CHIP_RV710:
433 DRM_INFO("Loading RV710 Microcode\n");
434 pfp = RV710_pfp_microcode;
435 cp = RV710_cp_microcode;
436 break;
437 default:
438 return;
439 }
440
441 r600_do_cp_stop(dev_priv);
442
443 RADEON_WRITE(R600_CP_RB_CNTL,
444 R600_RB_NO_UPDATE |
445 R600_RB_BLKSZ(15) |
446 R600_RB_BUFSZ(3));
447
448 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
449 RADEON_READ(R600_GRBM_SOFT_RESET);
450 DRM_UDELAY(15000);
451 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
452
453 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
454 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
455 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
456 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
457
458 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
459 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
460 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i]);
461 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
462
463 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
464 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
465 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
466
467 }
468
469 static void r600_test_writeback(drm_radeon_private_t * dev_priv)
470 {
471 u32 tmp;
472
473 /* Writeback doesn't seem to work everywhere, test it here and possibly
474 * enable it if it appears to work
475 */
476 DRM_WRITE32(dev_priv->ring_rptr, R600_SCRATCHOFF(1), 0);
477 RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
478
479 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
480 if (DRM_READ32(dev_priv->ring_rptr, R600_SCRATCHOFF(1)) ==
481 0xdeadbeef)
482 break;
483 DRM_UDELAY(1);
484 }
485
486 if (tmp < dev_priv->usec_timeout) {
487 dev_priv->writeback_works = 1;
488 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
489 } else {
490 dev_priv->writeback_works = 0;
491
492 for (tmp = 0; tmp < 512; tmp+=16 )
493 DRM_DEBUG("%d %x %x %x %x\n", tmp, DRM_READ32(dev_priv->ring_rptr, tmp),
494 DRM_READ32(dev_priv->ring_rptr, tmp + 4),
495 DRM_READ32(dev_priv->ring_rptr, tmp + 8),
496 DRM_READ32(dev_priv->ring_rptr, tmp + 16));
497
498 DRM_INFO("writeback test failed %x %x\n", DRM_READ32(dev_priv->ring_rptr, R600_SCRATCHOFF(1)), RADEON_READ(R600_SCRATCH_REG1));
499 }
500 if (radeon_no_wb == 1) {
501 dev_priv->writeback_works = 0;
502 DRM_INFO("writeback forced off\n");
503 }
504
505 if (!dev_priv->writeback_works) {
506 /* Disable writeback to avoid unnecessary bus master transfers */
507 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
508 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
509 }
510 }
511
512 int r600_do_engine_reset(struct drm_device * dev)
513 {
514 drm_radeon_private_t *dev_priv = dev->dev_private;
515 u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
516
517 DRM_INFO("Resetting GPU\n");
518
519 cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
520 cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
521 RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
522
523 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
524 RADEON_READ(R600_GRBM_SOFT_RESET);
525 DRM_UDELAY(50);
526 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
527 RADEON_READ(R600_GRBM_SOFT_RESET);
528
529 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
530 cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
531 RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA);
532
533 RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
534 RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
535 RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
536 RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
537
538 /* Reset the CP ring */
539 r600_do_cp_reset(dev_priv);
540
541 /* The CP is no longer running after an engine reset */
542 dev_priv->cp_running = 0;
543
544 /* Reset any pending vertex, indirect buffers */
545 radeon_freelist_reset(dev);
546
547 return 0;
548
549 }
550
551 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
552 u32 num_backends,
553 u32 backend_disable_mask)
554 {
555 u32 backend_map = 0;
556 u32 enabled_backends_mask;
557 u32 enabled_backends_count;
558 u32 cur_pipe;
559 u32 swizzle_pipe[R6XX_MAX_PIPES];
560 u32 cur_backend;
561 u32 i;
562
563 if (num_tile_pipes > R6XX_MAX_PIPES)
564 num_tile_pipes = R6XX_MAX_PIPES;
565 if (num_tile_pipes < 1)
566 num_tile_pipes = 1;
567 if (num_backends > R6XX_MAX_BACKENDS)
568 num_backends = R6XX_MAX_BACKENDS;
569 if (num_backends < 1)
570 num_backends = 1;
571
572 enabled_backends_mask = 0;
573 enabled_backends_count = 0;
574 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
575 if (((backend_disable_mask >> i) & 1) == 0) {
576 enabled_backends_mask |= (1 << i);
577 ++enabled_backends_count;
578 }
579 if (enabled_backends_count == num_backends)
580 break;
581 }
582
583 if (enabled_backends_count == 0) {
584 enabled_backends_mask = 1;
585 enabled_backends_count = 1;
586 }
587
588 if (enabled_backends_count != num_backends)
589 num_backends = enabled_backends_count;
590
591 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
592 switch (num_tile_pipes) {
593 case 1:
594 swizzle_pipe[0] = 0;
595 break;
596 case 2:
597 swizzle_pipe[0] = 0;
598 swizzle_pipe[1] = 1;
599 break;
600 case 3:
601 swizzle_pipe[0] = 0;
602 swizzle_pipe[1] = 1;
603 swizzle_pipe[2] = 2;
604 break;
605 case 4:
606 swizzle_pipe[0] = 0;
607 swizzle_pipe[1] = 1;
608 swizzle_pipe[2] = 2;
609 swizzle_pipe[3] = 3;
610 break;
611 case 5:
612 swizzle_pipe[0] = 0;
613 swizzle_pipe[1] = 1;
614 swizzle_pipe[2] = 2;
615 swizzle_pipe[3] = 3;
616 swizzle_pipe[4] = 4;
617 break;
618 case 6:
619 swizzle_pipe[0] = 0;
620 swizzle_pipe[1] = 2;
621 swizzle_pipe[2] = 4;
622 swizzle_pipe[3] = 5;
623 swizzle_pipe[4] = 1;
624 swizzle_pipe[5] = 3;
625 break;
626 case 7:
627 swizzle_pipe[0] = 0;
628 swizzle_pipe[1] = 2;
629 swizzle_pipe[2] = 4;
630 swizzle_pipe[3] = 6;
631 swizzle_pipe[4] = 1;
632 swizzle_pipe[5] = 3;
633 swizzle_pipe[6] = 5;
634 break;
635 case 8:
636 swizzle_pipe[0] = 0;
637 swizzle_pipe[1] = 2;
638 swizzle_pipe[2] = 4;
639 swizzle_pipe[3] = 6;
640 swizzle_pipe[4] = 1;
641 swizzle_pipe[5] = 3;
642 swizzle_pipe[6] = 5;
643 swizzle_pipe[7] = 7;
644 break;
645 }
646
647 cur_backend = 0;
648 for (cur_pipe=0; cur_pipe<num_tile_pipes; ++cur_pipe) {
649 while (((1 << cur_backend) & enabled_backends_mask) == 0)
650 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
651
652 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
653
654 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
655 }
656
657 return backend_map;
658 }
659
660 static int r600_count_pipe_bits (uint32_t val)
661 {
662 int i, ret = 0;
663 for (i = 0; i < 32; i++) {
664 ret += val & 1;
665 val >>= 1;
666 }
667 return ret;
668 }
669
670 static void r600_gfx_init(struct drm_device * dev,
671 drm_radeon_private_t * dev_priv)
672 {
673 int i, j, num_qd_pipes;
674 u32 sx_debug_1;
675 u32 tc_cntl;
676 u32 arb_pop;
677 u32 num_gs_verts_per_thread;
678 u32 vgt_gs_per_es;
679 u32 gs_prim_buffer_depth = 0;
680 u32 sq_ms_fifo_sizes;
681 u32 sq_config;
682 u32 sq_gpr_resource_mgmt_1 = 0;
683 u32 sq_gpr_resource_mgmt_2 = 0;
684 u32 sq_thread_resource_mgmt = 0;
685 u32 sq_stack_resource_mgmt_1 = 0;
686 u32 sq_stack_resource_mgmt_2 = 0;
687 u32 hdp_host_path_cntl;
688 u32 backend_map;
689 u32 gb_tiling_config = 0;
690 u32 cc_rb_backend_disable = 0;
691 u32 cc_gc_shader_pipe_config = 0;
692 u32 ramcfg;
693
694 /* setup chip specs */
695 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
696 case CHIP_R600:
697 dev_priv->r600_max_pipes = 4;
698 dev_priv->r600_max_tile_pipes = 8;
699 dev_priv->r600_max_simds = 4;
700 dev_priv->r600_max_backends = 4;
701 dev_priv->r600_max_gprs = 256;
702 dev_priv->r600_max_threads = 192;
703 dev_priv->r600_max_stack_entries = 256;
704 dev_priv->r600_max_hw_contexts = 8;
705 dev_priv->r600_max_gs_threads = 16;
706 dev_priv->r600_sx_max_export_size = 128;
707 dev_priv->r600_sx_max_export_pos_size = 16;
708 dev_priv->r600_sx_max_export_smx_size = 128;
709 dev_priv->r600_sq_num_cf_insts = 2;
710 break;
711 case CHIP_RV630:
712 case CHIP_RV635:
713 dev_priv->r600_max_pipes = 2;
714 dev_priv->r600_max_tile_pipes = 2;
715 dev_priv->r600_max_simds = 3;
716 dev_priv->r600_max_backends = 1;
717 dev_priv->r600_max_gprs = 128;
718 dev_priv->r600_max_threads = 192;
719 dev_priv->r600_max_stack_entries = 128;
720 dev_priv->r600_max_hw_contexts = 8;
721 dev_priv->r600_max_gs_threads = 4;
722 dev_priv->r600_sx_max_export_size = 128;
723 dev_priv->r600_sx_max_export_pos_size = 16;
724 dev_priv->r600_sx_max_export_smx_size = 128;
725 dev_priv->r600_sq_num_cf_insts = 2;
726 break;
727 case CHIP_RV610:
728 case CHIP_RS780:
729 case CHIP_RV620:
730 dev_priv->r600_max_pipes = 1;
731 dev_priv->r600_max_tile_pipes = 1;
732 dev_priv->r600_max_simds = 2;
733 dev_priv->r600_max_backends = 1;
734 dev_priv->r600_max_gprs = 128;
735 dev_priv->r600_max_threads = 192;
736 dev_priv->r600_max_stack_entries = 128;
737 dev_priv->r600_max_hw_contexts = 4;
738 dev_priv->r600_max_gs_threads = 4;
739 dev_priv->r600_sx_max_export_size = 128;
740 dev_priv->r600_sx_max_export_pos_size = 16;
741 dev_priv->r600_sx_max_export_smx_size = 128;
742 dev_priv->r600_sq_num_cf_insts = 1;
743 break;
744 case CHIP_RV670:
745 dev_priv->r600_max_pipes = 4;
746 dev_priv->r600_max_tile_pipes = 4;
747 dev_priv->r600_max_simds = 4;
748 dev_priv->r600_max_backends = 4;
749 dev_priv->r600_max_gprs = 192;
750 dev_priv->r600_max_threads = 192;
751 dev_priv->r600_max_stack_entries = 256;
752 dev_priv->r600_max_hw_contexts = 8;
753 dev_priv->r600_max_gs_threads = 16;
754 dev_priv->r600_sx_max_export_size = 128;
755 dev_priv->r600_sx_max_export_pos_size = 16;
756 dev_priv->r600_sx_max_export_smx_size = 128;
757 dev_priv->r600_sq_num_cf_insts = 2;
758 break;
759 default:
760 break;
761 }
762
763 /* Initialize HDP */
764 j = 0;
765 for (i = 0; i < 32; i++) {
766 RADEON_WRITE((0x2c14 + j), 0x00000000);
767 RADEON_WRITE((0x2c18 + j), 0x00000000);
768 RADEON_WRITE((0x2c1c + j), 0x00000000);
769 RADEON_WRITE((0x2c20 + j), 0x00000000);
770 RADEON_WRITE((0x2c24 + j), 0x00000000);
771 j += 0x18;
772 }
773
774 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
775
776 /* setup tiling, simd, pipe config */
777 ramcfg = RADEON_READ(R600_RAMCFG);
778
779 switch (dev_priv->r600_max_tile_pipes) {
780 case 1:
781 gb_tiling_config |= R600_PIPE_TILING(0);
782 break;
783 case 2:
784 gb_tiling_config |= R600_PIPE_TILING(1);
785 break;
786 case 4:
787 gb_tiling_config |= R600_PIPE_TILING(2);
788 break;
789 case 8:
790 gb_tiling_config |= R600_PIPE_TILING(3);
791 break;
792 default:
793 break;
794 }
795
796 gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
797
798 gb_tiling_config |= R600_GROUP_SIZE(0);
799
800 if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
801 gb_tiling_config |= R600_ROW_TILING(3);
802 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
803 } else {
804 gb_tiling_config |=
805 R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
806 gb_tiling_config |=
807 R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
808 }
809
810 gb_tiling_config |= R600_BANK_SWAPS(1);
811
812 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
813 dev_priv->r600_max_backends,
814 (0xff << dev_priv->r600_max_backends) & 0xff);
815 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
816
817 cc_gc_shader_pipe_config =
818 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
819 cc_gc_shader_pipe_config |=
820 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
821
822 cc_rb_backend_disable =
823 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
824
825 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
826 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
827 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
828
829 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
830 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
831 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
832
833 num_qd_pipes =
834 R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
835 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
836 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
837
838 /* set HW defaults for 3D engine */
839 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
840 R600_ROQ_IB2_START(0x2b)));
841
842 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
843 R600_ROQ_END(0x40)));
844
845 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
846 R600_SYNC_GRADIENT |
847 R600_SYNC_WALKER |
848 R600_SYNC_ALIGNER));
849
850 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
851 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
852
853 sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
854 sx_debug_1 |= R600_SMX_EVENT_RELEASE;
855 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
856 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
857 RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
858
859 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
860 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
861 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
862 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
863 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))
864 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
865 else
866 RADEON_WRITE(R600_DB_DEBUG, 0);
867
868 RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
869 R600_DEPTH_FLUSH(16) |
870 R600_DEPTH_PENDING_FREE(4) |
871 R600_DEPTH_CACHELINE_FREE(16)));
872 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
873 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
874
875 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
876 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
877
878 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
879 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
880 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
881 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
882 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
883 R600_FETCH_FIFO_HIWATER(0xa) |
884 R600_DONE_FIFO_HIWATER(0xe0) |
885 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
886 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
887 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
888 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
889 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
890 }
891 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
892
893 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
894 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
895 */
896 sq_config = RADEON_READ(R600_SQ_CONFIG);
897 sq_config &= ~(R600_PS_PRIO(3) |
898 R600_VS_PRIO(3) |
899 R600_GS_PRIO(3) |
900 R600_ES_PRIO(3));
901 sq_config |= (R600_DX9_CONSTS |
902 R600_VC_ENABLE |
903 R600_PS_PRIO(0) |
904 R600_VS_PRIO(1) |
905 R600_GS_PRIO(2) |
906 R600_ES_PRIO(3));
907
908 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
909 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
910 R600_NUM_VS_GPRS(124) |
911 R600_NUM_CLAUSE_TEMP_GPRS(4));
912 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
913 R600_NUM_ES_GPRS(0));
914 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
915 R600_NUM_VS_THREADS(48) |
916 R600_NUM_GS_THREADS(4) |
917 R600_NUM_ES_THREADS(4));
918 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
919 R600_NUM_VS_STACK_ENTRIES(128));
920 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
921 R600_NUM_ES_STACK_ENTRIES(0));
922 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
923 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
924 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
925 /* no vertex cache */
926 sq_config &= ~R600_VC_ENABLE;
927
928 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
929 R600_NUM_VS_GPRS(44) |
930 R600_NUM_CLAUSE_TEMP_GPRS(2));
931 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
932 R600_NUM_ES_GPRS(17));
933 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
934 R600_NUM_VS_THREADS(78) |
935 R600_NUM_GS_THREADS(4) |
936 R600_NUM_ES_THREADS(31));
937 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
938 R600_NUM_VS_STACK_ENTRIES(40));
939 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
940 R600_NUM_ES_STACK_ENTRIES(16));
941 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
942 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)){
943 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
944 R600_NUM_VS_GPRS(44) |
945 R600_NUM_CLAUSE_TEMP_GPRS(2));
946 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
947 R600_NUM_ES_GPRS(18));
948 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
949 R600_NUM_VS_THREADS(78) |
950 R600_NUM_GS_THREADS(4) |
951 R600_NUM_ES_THREADS(31));
952 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
953 R600_NUM_VS_STACK_ENTRIES(40));
954 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
955 R600_NUM_ES_STACK_ENTRIES(16));
956 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
957 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
958 R600_NUM_VS_GPRS(44) |
959 R600_NUM_CLAUSE_TEMP_GPRS(2));
960 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
961 R600_NUM_ES_GPRS(17));
962 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
963 R600_NUM_VS_THREADS(78) |
964 R600_NUM_GS_THREADS(4) |
965 R600_NUM_ES_THREADS(31));
966 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
967 R600_NUM_VS_STACK_ENTRIES(64));
968 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
969 R600_NUM_ES_STACK_ENTRIES(64));
970 }
971
972 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
973 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
974 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
975 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
976 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
977 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
978
979 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
980 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
981 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))
982 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
983 else
984 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
985
986 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
987 R600_S0_Y(0x4) |
988 R600_S1_X(0x4) |
989 R600_S1_Y(0xc)));
990 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
991 R600_S0_Y(0xe) |
992 R600_S1_X(0x2) |
993 R600_S1_Y(0x2) |
994 R600_S2_X(0xa) |
995 R600_S2_Y(0x6) |
996 R600_S3_X(0x6) |
997 R600_S3_Y(0xa)));
998 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
999 R600_S0_Y(0xb) |
1000 R600_S1_X(0x4) |
1001 R600_S1_Y(0xc) |
1002 R600_S2_X(0x1) |
1003 R600_S2_Y(0x6) |
1004 R600_S3_X(0xa) |
1005 R600_S3_Y(0xe)));
1006 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1007 R600_S4_Y(0x1) |
1008 R600_S5_X(0x0) |
1009 R600_S5_Y(0x0) |
1010 R600_S6_X(0xb) |
1011 R600_S6_Y(0x4) |
1012 R600_S7_X(0x7) |
1013 R600_S7_Y(0x8)));
1014
1015 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1016 case CHIP_R600:
1017 case CHIP_RV630:
1018 case CHIP_RV635:
1019 gs_prim_buffer_depth = 0;
1020 break;
1021 case CHIP_RV610:
1022 case CHIP_RS780:
1023 case CHIP_RV620:
1024 gs_prim_buffer_depth = 32;
1025 break;
1026 case CHIP_RV670:
1027 gs_prim_buffer_depth = 128;
1028 break;
1029 default:
1030 break;
1031 }
1032
1033 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1034 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1035 /* Max value for this is 256 */
1036 if (vgt_gs_per_es > 256)
1037 vgt_gs_per_es = 256;
1038
1039 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1040 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1041 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1042 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1043
1044 /* more default values. 2D/3D driver should adjust as needed */
1045 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1046 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1047 RADEON_WRITE(R600_SX_MISC, 0);
1048 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1049 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1050 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1051 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1052 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1053 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1054
1055 /* clear render buffer base addresses */
1056 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1057 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1058 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1059 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1060 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1061 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1062 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1063 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1064
1065 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1066 case CHIP_RV610:
1067 case CHIP_RS780:
1068 case CHIP_RV620:
1069 tc_cntl = R600_TC_L2_SIZE(8);
1070 break;
1071 case CHIP_RV630:
1072 case CHIP_RV635:
1073 tc_cntl = R600_TC_L2_SIZE(4);
1074 break;
1075 case CHIP_R600:
1076 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1077 break;
1078 default:
1079 tc_cntl = R600_TC_L2_SIZE(0);
1080 break;
1081 }
1082
1083 RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1084
1085 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1086 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1087
1088 arb_pop = RADEON_READ(R600_ARB_POP);
1089 arb_pop |= R600_ENABLE_TC128;
1090 RADEON_WRITE(R600_ARB_POP, arb_pop);
1091
1092 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1093 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1094 R600_NUM_CLIP_SEQ(3)));
1095 RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1096
1097 }
1098
1099 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1100 u32 num_backends,
1101 u32 backend_disable_mask)
1102 {
1103 u32 backend_map = 0;
1104 u32 enabled_backends_mask;
1105 u32 enabled_backends_count;
1106 u32 cur_pipe;
1107 u32 swizzle_pipe[R7XX_MAX_PIPES];
1108 u32 cur_backend;
1109 u32 i;
1110
1111 if (num_tile_pipes > R7XX_MAX_PIPES)
1112 num_tile_pipes = R7XX_MAX_PIPES;
1113 if (num_tile_pipes < 1)
1114 num_tile_pipes = 1;
1115 if (num_backends > R7XX_MAX_BACKENDS)
1116 num_backends = R7XX_MAX_BACKENDS;
1117 if (num_backends < 1)
1118 num_backends = 1;
1119
1120 enabled_backends_mask = 0;
1121 enabled_backends_count = 0;
1122 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1123 if (((backend_disable_mask >> i) & 1) == 0) {
1124 enabled_backends_mask |= (1 << i);
1125 ++enabled_backends_count;
1126 }
1127 if (enabled_backends_count == num_backends)
1128 break;
1129 }
1130
1131 if (enabled_backends_count == 0) {
1132 enabled_backends_mask = 1;
1133 enabled_backends_count = 1;
1134 }
1135
1136 if (enabled_backends_count != num_backends)
1137 num_backends = enabled_backends_count;
1138
1139 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1140 switch (num_tile_pipes) {
1141 case 1:
1142 swizzle_pipe[0] = 0;
1143 break;
1144 case 2:
1145 swizzle_pipe[0] = 0;
1146 swizzle_pipe[1] = 1;
1147 break;
1148 case 3:
1149 swizzle_pipe[0] = 0;
1150 swizzle_pipe[1] = 2;
1151 swizzle_pipe[2] = 1;
1152 break;
1153 case 4:
1154 swizzle_pipe[0] = 0;
1155 swizzle_pipe[1] = 2;
1156 swizzle_pipe[2] = 3;
1157 swizzle_pipe[3] = 1;
1158 break;
1159 case 5:
1160 swizzle_pipe[0] = 0;
1161 swizzle_pipe[1] = 2;
1162 swizzle_pipe[2] = 4;
1163 swizzle_pipe[3] = 1;
1164 swizzle_pipe[4] = 3;
1165 break;
1166 case 6:
1167 swizzle_pipe[0] = 0;
1168 swizzle_pipe[1] = 2;
1169 swizzle_pipe[2] = 4;
1170 swizzle_pipe[3] = 5;
1171 swizzle_pipe[4] = 3;
1172 swizzle_pipe[5] = 1;
1173 break;
1174 case 7:
1175 swizzle_pipe[0] = 0;
1176 swizzle_pipe[1] = 2;
1177 swizzle_pipe[2] = 4;
1178 swizzle_pipe[3] = 6;
1179 swizzle_pipe[4] = 3;
1180 swizzle_pipe[5] = 1;
1181 swizzle_pipe[6] = 5;
1182 break;
1183 case 8:
1184 swizzle_pipe[0] = 0;
1185 swizzle_pipe[1] = 2;
1186 swizzle_pipe[2] = 4;
1187 swizzle_pipe[3] = 6;
1188 swizzle_pipe[4] = 3;
1189 swizzle_pipe[5] = 1;
1190 swizzle_pipe[6] = 7;
1191 swizzle_pipe[7] = 5;
1192 break;
1193 }
1194
1195 cur_backend = 0;
1196 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1197 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1198 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1199
1200 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1201
1202 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1203 }
1204
1205 return backend_map;
1206 }
1207
1208 static void r700_gfx_init(struct drm_device * dev,
1209 drm_radeon_private_t * dev_priv)
1210 {
1211 int i, j, num_qd_pipes;
1212 u32 sx_debug_1;
1213 u32 smx_dc_ctl0;
1214 u32 num_gs_verts_per_thread;
1215 u32 vgt_gs_per_es;
1216 u32 gs_prim_buffer_depth = 0;
1217 u32 sq_ms_fifo_sizes;
1218 u32 sq_config;
1219 u32 sq_thread_resource_mgmt;
1220 u32 hdp_host_path_cntl;
1221 u32 sq_dyn_gpr_size_simd_ab_0;
1222 u32 backend_map;
1223 u32 gb_tiling_config = 0;
1224 u32 cc_rb_backend_disable = 0;
1225 u32 cc_gc_shader_pipe_config = 0;
1226 u32 mc_arb_ramcfg;
1227 u32 db_debug4;
1228
1229 /* setup chip specs */
1230 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1231 case CHIP_RV770:
1232 dev_priv->r600_max_pipes = 4;
1233 dev_priv->r600_max_tile_pipes = 8;
1234 dev_priv->r600_max_simds = 10;
1235 dev_priv->r600_max_backends = 4;
1236 dev_priv->r600_max_gprs = 256;
1237 dev_priv->r600_max_threads = 248;
1238 dev_priv->r600_max_stack_entries = 512;
1239 dev_priv->r600_max_hw_contexts = 8;
1240 dev_priv->r600_max_gs_threads = 16 * 2;
1241 dev_priv->r600_sx_max_export_size = 128;
1242 dev_priv->r600_sx_max_export_pos_size = 16;
1243 dev_priv->r600_sx_max_export_smx_size = 112;
1244 dev_priv->r600_sq_num_cf_insts = 2;
1245
1246 dev_priv->r700_sx_num_of_sets = 7;
1247 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1248 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1249 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1250 break;
1251 case CHIP_RV730:
1252 dev_priv->r600_max_pipes = 2;
1253 dev_priv->r600_max_tile_pipes = 4;
1254 dev_priv->r600_max_simds = 8;
1255 dev_priv->r600_max_backends = 2;
1256 dev_priv->r600_max_gprs = 128;
1257 dev_priv->r600_max_threads = 248;
1258 dev_priv->r600_max_stack_entries = 256;
1259 dev_priv->r600_max_hw_contexts = 8;
1260 dev_priv->r600_max_gs_threads = 16 * 2;
1261 dev_priv->r600_sx_max_export_size = 256;
1262 dev_priv->r600_sx_max_export_pos_size = 32;
1263 dev_priv->r600_sx_max_export_smx_size = 224;
1264 dev_priv->r600_sq_num_cf_insts = 2;
1265
1266 dev_priv->r700_sx_num_of_sets = 7;
1267 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1268 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1269 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1270 break;
1271 case CHIP_RV710:
1272 dev_priv->r600_max_pipes = 2;
1273 dev_priv->r600_max_tile_pipes = 2;
1274 dev_priv->r600_max_simds = 2;
1275 dev_priv->r600_max_backends = 1;
1276 dev_priv->r600_max_gprs = 256;
1277 dev_priv->r600_max_threads = 192;
1278 dev_priv->r600_max_stack_entries = 256;
1279 dev_priv->r600_max_hw_contexts = 4;
1280 dev_priv->r600_max_gs_threads = 8 * 2;
1281 dev_priv->r600_sx_max_export_size = 128;
1282 dev_priv->r600_sx_max_export_pos_size = 16;
1283 dev_priv->r600_sx_max_export_smx_size = 112;
1284 dev_priv->r600_sq_num_cf_insts = 1;
1285
1286 dev_priv->r700_sx_num_of_sets = 7;
1287 dev_priv->r700_sc_prim_fifo_size = 0x40;
1288 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1289 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1290 break;
1291 default:
1292 break;
1293 }
1294
1295 /* Initialize HDP */
1296 j = 0;
1297 for (i = 0; i < 32; i++) {
1298 RADEON_WRITE((0x2c14 + j), 0x00000000);
1299 RADEON_WRITE((0x2c18 + j), 0x00000000);
1300 RADEON_WRITE((0x2c1c + j), 0x00000000);
1301 RADEON_WRITE((0x2c20 + j), 0x00000000);
1302 RADEON_WRITE((0x2c24 + j), 0x00000000);
1303 j += 0x18;
1304 }
1305
1306 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1307
1308 /* setup tiling, simd, pipe config */
1309 mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1310
1311 switch (dev_priv->r600_max_tile_pipes) {
1312 case 1:
1313 gb_tiling_config |= R600_PIPE_TILING(0);
1314 break;
1315 case 2:
1316 gb_tiling_config |= R600_PIPE_TILING(1);
1317 break;
1318 case 4:
1319 gb_tiling_config |= R600_PIPE_TILING(2);
1320 break;
1321 case 8:
1322 gb_tiling_config |= R600_PIPE_TILING(3);
1323 break;
1324 default:
1325 break;
1326 }
1327
1328 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1329 gb_tiling_config |= R600_BANK_TILING(1);
1330 else
1331 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1332
1333 gb_tiling_config |= R600_GROUP_SIZE(0);
1334
1335 if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1336 gb_tiling_config |= R600_ROW_TILING(3);
1337 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1338 } else {
1339 gb_tiling_config |=
1340 R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1341 gb_tiling_config |=
1342 R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1343 }
1344
1345 gb_tiling_config |= R600_BANK_SWAPS(1);
1346
1347 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
1348 dev_priv->r600_max_backends,
1349 (0xff << dev_priv->r600_max_backends) & 0xff);
1350 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1351
1352 cc_gc_shader_pipe_config =
1353 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1354 cc_gc_shader_pipe_config |=
1355 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1356
1357 cc_rb_backend_disable =
1358 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1359
1360 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
1361 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1362 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1363
1364 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1365 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1366 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1367
1368 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1369 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1370 RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1371 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1372 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1373
1374 num_qd_pipes =
1375 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
1376 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1377 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1378
1379 /* set HW defaults for 3D engine */
1380 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1381 R600_ROQ_IB2_START(0x2b)));
1382
1383 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1384
1385 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
1386 R600_SYNC_GRADIENT |
1387 R600_SYNC_WALKER |
1388 R600_SYNC_ALIGNER));
1389
1390 sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1391 sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1392 RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1393
1394 smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1395 smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1396 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1397 RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1398
1399 RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1400 R700_GS_FLUSH_CTL(4) |
1401 R700_ACK_FLUSH_CTL(3) |
1402 R700_SYNC_FLUSH_CTL));
1403
1404 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1405 RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f));
1406 else {
1407 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1408 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1409 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1410 }
1411
1412 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1413 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1414 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1415
1416 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1417 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1418 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1419
1420 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1421
1422 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1423
1424 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1425
1426 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1427
1428 RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1429
1430 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1431 R600_DONE_FIFO_HIWATER(0xe0) |
1432 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1433 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1434 case CHIP_RV770:
1435 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1436 break;
1437 case CHIP_RV730:
1438 case CHIP_RV710:
1439 default:
1440 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1441 break;
1442 }
1443 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1444
1445 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1446 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1447 */
1448 sq_config = RADEON_READ(R600_SQ_CONFIG);
1449 sq_config &= ~(R600_PS_PRIO(3) |
1450 R600_VS_PRIO(3) |
1451 R600_GS_PRIO(3) |
1452 R600_ES_PRIO(3));
1453 sq_config |= (R600_DX9_CONSTS |
1454 R600_VC_ENABLE |
1455 R600_EXPORT_SRC_C |
1456 R600_PS_PRIO(0) |
1457 R600_VS_PRIO(1) |
1458 R600_GS_PRIO(2) |
1459 R600_ES_PRIO(3));
1460 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1461 /* no vertex cache */
1462 sq_config &= ~R600_VC_ENABLE;
1463
1464 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1465
1466 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1467 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1468 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1469
1470 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1471 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1472
1473 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1474 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1475 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1476 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1477 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1478 else
1479 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1480 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1481
1482 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1483 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1484
1485 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1486 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1487
1488 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1489 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1490 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1491 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1492
1493 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1494 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1495 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1496 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1497 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1498 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1499 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1500 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1501
1502 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1503 R700_FORCE_EOV_MAX_REZ_CNT(255)));
1504
1505 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1506 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1507 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1508 else
1509 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1510 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1511
1512 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1513 case CHIP_RV770:
1514 case CHIP_RV730:
1515 gs_prim_buffer_depth = 384;
1516 break;
1517 case CHIP_RV710:
1518 gs_prim_buffer_depth = 128;
1519 break;
1520 default:
1521 break;
1522 }
1523
1524 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1525 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1526 /* Max value for this is 256 */
1527 if (vgt_gs_per_es > 256)
1528 vgt_gs_per_es = 256;
1529
1530 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1531 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1532 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1533
1534 /* more default values. 2D/3D driver should adjust as needed */
1535 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1536 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1537 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1538 RADEON_WRITE(R600_SX_MISC, 0);
1539 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1540 RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1541 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1542 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1543 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1544 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1545 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1546 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1547
1548 /* clear render buffer base addresses */
1549 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1550 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1551 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1552 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1553 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1554 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1555 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1556 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1557
1558 RADEON_WRITE(R700_TCP_CNTL, 0);
1559
1560 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1561 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1562
1563 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1564
1565 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1566 R600_NUM_CLIP_SEQ(3)));
1567
1568 }
1569
1570 static void r600_cp_init_ring_buffer(struct drm_device * dev,
1571 drm_radeon_private_t * dev_priv)
1572 {
1573 u32 ring_start;
1574 u64 rptr_addr;
1575 /*u32 cur_read_ptr;*/
1576 /*u32 tmp;*/
1577
1578 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1579 r700_gfx_init(dev, dev_priv);
1580 else
1581 r600_gfx_init(dev, dev_priv);
1582
1583 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1584 RADEON_READ(R600_GRBM_SOFT_RESET);
1585 DRM_UDELAY(15000);
1586 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1587
1588
1589 /* Set ring buffer size */
1590 #ifdef __BIG_ENDIAN
1591 RADEON_WRITE(R600_CP_RB_CNTL,
1592 RADEON_BUF_SWAP_32BIT |
1593 RADEON_RB_NO_UPDATE |
1594 (dev_priv->ring.rptr_update_l2qw << 8) |
1595 dev_priv->ring.size_l2qw);
1596 #else
1597 RADEON_WRITE(R600_CP_RB_CNTL,
1598 RADEON_RB_NO_UPDATE |
1599 (dev_priv->ring.rptr_update_l2qw << 8) |
1600 dev_priv->ring.size_l2qw);
1601 #endif
1602
1603 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4);
1604
1605 /* Set the write pointer delay */
1606 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1607
1608 #ifdef __BIG_ENDIAN
1609 RADEON_WRITE(R600_CP_RB_CNTL,
1610 RADEON_BUF_SWAP_32BIT |
1611 RADEON_RB_NO_UPDATE |
1612 RADEON_RB_RPTR_WR_ENA |
1613 (dev_priv->ring.rptr_update_l2qw << 8) |
1614 dev_priv->ring.size_l2qw);
1615 #else
1616 RADEON_WRITE(R600_CP_RB_CNTL,
1617 RADEON_RB_NO_UPDATE |
1618 RADEON_RB_RPTR_WR_ENA |
1619 (dev_priv->ring.rptr_update_l2qw << 8) |
1620 dev_priv->ring.size_l2qw);
1621 #endif
1622
1623 /* Initialize the ring buffer's read and write pointers */
1624 #if 0
1625 cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
1626 RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
1627 SET_RING_HEAD(dev_priv, cur_read_ptr);
1628 dev_priv->ring.tail = cur_read_ptr;
1629
1630 #endif
1631
1632 RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1633 RADEON_WRITE(R600_CP_RB_WPTR, 0);
1634 SET_RING_HEAD(dev_priv, 0);
1635 dev_priv->ring.tail = 0;
1636
1637 #if __OS_HAS_AGP
1638 if (dev_priv->flags & RADEON_IS_AGP) {
1639 rptr_addr = dev_priv->ring_rptr->offset
1640 - dev->agp->base +
1641 dev_priv->gart_vm_start;
1642 } else
1643 #endif
1644 {
1645 rptr_addr = dev_priv->ring_rptr->offset
1646 - ((unsigned long) dev->sg->virtual)
1647 + dev_priv->gart_vm_start;
1648 }
1649
1650 RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
1651 rptr_addr & 0xffffffff);
1652 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
1653 upper_32_bits(rptr_addr));
1654
1655 #ifdef __BIG_ENDIAN
1656 RADEON_WRITE(R600_CP_RB_CNTL,
1657 RADEON_BUF_SWAP_32BIT |
1658 (dev_priv->ring.rptr_update_l2qw << 8) |
1659 dev_priv->ring.size_l2qw);
1660 #else
1661 RADEON_WRITE(R600_CP_RB_CNTL,
1662 (dev_priv->ring.rptr_update_l2qw << 8) |
1663 dev_priv->ring.size_l2qw);
1664 #endif
1665
1666 #if __OS_HAS_AGP
1667 if (dev_priv->flags & RADEON_IS_AGP) {
1668 // XXX
1669 radeon_write_agp_base(dev_priv, dev->agp->base);
1670
1671 // XXX
1672 radeon_write_agp_location(dev_priv,
1673 (((dev_priv->gart_vm_start - 1 +
1674 dev_priv->gart_size) & 0xffff0000) |
1675 (dev_priv->gart_vm_start >> 16)));
1676
1677 ring_start = (dev_priv->cp_ring->offset
1678 - dev->agp->base
1679 + dev_priv->gart_vm_start);
1680 } else
1681 #endif
1682 ring_start = (dev_priv->cp_ring->offset
1683 - (unsigned long)dev->sg->virtual
1684 + dev_priv->gart_vm_start);
1685
1686 RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1687
1688 RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1689
1690 RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1691
1692 /* Initialize the scratch register pointer. This will cause
1693 * the scratch register values to be written out to memory
1694 * whenever they are updated.
1695 *
1696 * We simply put this behind the ring read pointer, this works
1697 * with PCI GART as well as (whatever kind of) AGP GART
1698 */
1699
1700 {
1701 u64 scratch_addr;
1702
1703 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR);
1704 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1705 scratch_addr += R600_SCRATCH_REG_OFFSET;
1706 scratch_addr >>= 8;
1707 scratch_addr &= 0xffffffff;
1708
1709 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1710 }
1711
1712 dev_priv->scratch = ((__volatile__ u32 *)
1713 dev_priv->ring_rptr->handle +
1714 (R600_SCRATCH_REG_OFFSET / sizeof(u32)));
1715
1716 RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1717
1718 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1719 RADEON_WRITE(R600_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1720
1721 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1722 RADEON_WRITE(R600_LAST_DISPATCH_REG,
1723 dev_priv->sarea_priv->last_dispatch);
1724
1725 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1726 RADEON_WRITE(R600_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1727
1728 r600_do_wait_for_idle(dev_priv);
1729
1730 }
1731
1732 int r600_do_cleanup_cp(struct drm_device * dev)
1733 {
1734 drm_radeon_private_t *dev_priv = dev->dev_private;
1735 DRM_DEBUG("\n");
1736
1737 /* Make sure interrupts are disabled here because the uninstall ioctl
1738 * may not have been called from userspace and after dev_private
1739 * is freed, it's too late.
1740 */
1741 if (dev->irq_enabled)
1742 drm_irq_uninstall(dev);
1743
1744 #if __OS_HAS_AGP
1745 if (dev_priv->flags & RADEON_IS_AGP) {
1746 if (dev_priv->cp_ring != NULL) {
1747 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1748 dev_priv->cp_ring = NULL;
1749 }
1750 if (dev_priv->ring_rptr != NULL) {
1751 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1752 dev_priv->ring_rptr = NULL;
1753 }
1754 if (dev->agp_buffer_map != NULL) {
1755 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1756 dev->agp_buffer_map = NULL;
1757 }
1758 } else
1759 #endif
1760 {
1761
1762 if (dev_priv->gart_info.mapping.handle) {
1763 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1764 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1765 dev_priv->gart_info.addr = 0;
1766 dev_priv->gart_info.mapping.handle = 0;
1767 }
1768 }
1769 /* only clear to the start of flags */
1770 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1771
1772 return 0;
1773 }
1774
1775 int r600_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
1776 {
1777 drm_radeon_private_t *dev_priv = dev->dev_private;
1778
1779 DRM_DEBUG("\n");
1780
1781 /* if we require new memory map but we don't have it fail */
1782 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1783 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1784 r600_do_cleanup_cp(dev);
1785 return -EINVAL;
1786 }
1787
1788 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP))
1789 {
1790 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1791 dev_priv->flags &= ~RADEON_IS_AGP;
1792 /* The writeback test succeeds, but when writeback is enabled,
1793 * the ring buffer read ptr update fails after first 128 bytes.
1794 */
1795 radeon_no_wb = 1;
1796 }
1797 else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1798 && !init->is_pci)
1799 {
1800 DRM_DEBUG("Restoring AGP flag\n");
1801 dev_priv->flags |= RADEON_IS_AGP;
1802 }
1803
1804 dev_priv->usec_timeout = init->usec_timeout;
1805 if (dev_priv->usec_timeout < 1 ||
1806 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1807 DRM_DEBUG("TIMEOUT problem!\n");
1808 r600_do_cleanup_cp(dev);
1809 return -EINVAL;
1810 }
1811
1812 /* Enable vblank on CRTC1 for older X servers
1813 */
1814 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1815
1816 dev_priv->cp_mode = init->cp_mode;
1817
1818 /* We don't support anything other than bus-mastering ring mode,
1819 * but the ring can be in either AGP or PCI space for the ring
1820 * read pointer.
1821 */
1822 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1823 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1824 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1825 r600_do_cleanup_cp(dev);
1826 return -EINVAL;
1827 }
1828
1829 switch (init->fb_bpp) {
1830 case 16:
1831 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1832 break;
1833 case 32:
1834 default:
1835 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1836 break;
1837 }
1838 dev_priv->front_offset = init->front_offset;
1839 dev_priv->front_pitch = init->front_pitch;
1840 dev_priv->back_offset = init->back_offset;
1841 dev_priv->back_pitch = init->back_pitch;
1842
1843 dev_priv->ring_offset = init->ring_offset;
1844 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1845 dev_priv->buffers_offset = init->buffers_offset;
1846 dev_priv->gart_textures_offset = init->gart_textures_offset;
1847
1848 dev_priv->sarea = drm_getsarea(dev);
1849 if (!dev_priv->sarea) {
1850 DRM_ERROR("could not find sarea!\n");
1851 r600_do_cleanup_cp(dev);
1852 return -EINVAL;
1853 }
1854
1855 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1856 if (!dev_priv->cp_ring) {
1857 DRM_ERROR("could not find cp ring region!\n");
1858 r600_do_cleanup_cp(dev);
1859 return -EINVAL;
1860 }
1861 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1862 if (!dev_priv->ring_rptr) {
1863 DRM_ERROR("could not find ring read pointer!\n");
1864 r600_do_cleanup_cp(dev);
1865 return -EINVAL;
1866 }
1867 dev->agp_buffer_token = init->buffers_offset;
1868 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1869 if (!dev->agp_buffer_map) {
1870 DRM_ERROR("could not find dma buffer region!\n");
1871 r600_do_cleanup_cp(dev);
1872 return -EINVAL;
1873 }
1874
1875 if (init->gart_textures_offset) {
1876 dev_priv->gart_textures =
1877 drm_core_findmap(dev, init->gart_textures_offset);
1878 if (!dev_priv->gart_textures) {
1879 DRM_ERROR("could not find GART texture region!\n");
1880 r600_do_cleanup_cp(dev);
1881 return -EINVAL;
1882 }
1883 }
1884
1885 dev_priv->sarea_priv =
1886 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1887 init->sarea_priv_offset);
1888
1889 #if __OS_HAS_AGP
1890 // XXX
1891 if (dev_priv->flags & RADEON_IS_AGP) {
1892 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1893 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1894 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1895 if (!dev_priv->cp_ring->handle ||
1896 !dev_priv->ring_rptr->handle ||
1897 !dev->agp_buffer_map->handle) {
1898 DRM_ERROR("could not find ioremap agp regions!\n");
1899 r600_do_cleanup_cp(dev);
1900 return -EINVAL;
1901 }
1902 } else
1903 #endif
1904 {
1905 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1906 dev_priv->ring_rptr->handle =
1907 (void *)dev_priv->ring_rptr->offset;
1908 dev->agp_buffer_map->handle =
1909 (void *)dev->agp_buffer_map->offset;
1910
1911 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1912 dev_priv->cp_ring->handle);
1913 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1914 dev_priv->ring_rptr->handle);
1915 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1916 dev->agp_buffer_map->handle);
1917 }
1918
1919 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
1920 dev_priv->fb_size =
1921 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
1922 - dev_priv->fb_location;
1923
1924 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1925 ((dev_priv->front_offset
1926 + dev_priv->fb_location) >> 10));
1927
1928 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1929 ((dev_priv->back_offset
1930 + dev_priv->fb_location) >> 10));
1931
1932 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1933 ((dev_priv->depth_offset
1934 + dev_priv->fb_location) >> 10));
1935
1936 dev_priv->gart_size = init->gart_size;
1937
1938 /* New let's set the memory map ... */
1939 if (dev_priv->new_memmap) {
1940 u32 base = 0;
1941
1942 DRM_INFO("Setting GART location based on new memory map\n");
1943
1944 /* If using AGP, try to locate the AGP aperture at the same
1945 * location in the card and on the bus, though we have to
1946 * align it down.
1947 */
1948 #if __OS_HAS_AGP
1949 // XXX
1950 if (dev_priv->flags & RADEON_IS_AGP) {
1951 base = dev->agp->base;
1952 /* Check if valid */
1953 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1954 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1955 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1956 dev->agp->base);
1957 base = 0;
1958 }
1959 }
1960 #endif
1961 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1962 if (base == 0) {
1963 base = dev_priv->fb_location + dev_priv->fb_size;
1964 if (base < dev_priv->fb_location ||
1965 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1966 base = dev_priv->fb_location
1967 - dev_priv->gart_size;
1968 }
1969 dev_priv->gart_vm_start = base & 0xffc00000u;
1970 if (dev_priv->gart_vm_start != base)
1971 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1972 base, dev_priv->gart_vm_start);
1973 }
1974
1975 #if __OS_HAS_AGP
1976 // XXX
1977 if (dev_priv->flags & RADEON_IS_AGP)
1978 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1979 - dev->agp->base
1980 + dev_priv->gart_vm_start);
1981 else
1982 #endif
1983 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1984 - (unsigned long)dev->sg->virtual
1985 + dev_priv->gart_vm_start);
1986
1987 DRM_DEBUG("fb 0x%08x size %d\n",
1988 (unsigned int) dev_priv->fb_location,
1989 (unsigned int) dev_priv->fb_size);
1990 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1991 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
1992 (unsigned int) dev_priv->gart_vm_start);
1993 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
1994 dev_priv->gart_buffers_offset);
1995
1996 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1997 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1998 + init->ring_size / sizeof(u32));
1999 dev_priv->ring.size = init->ring_size;
2000 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2001
2002 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2003 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
2004
2005 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2006 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
2007
2008 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2009
2010 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2011
2012 #if __OS_HAS_AGP
2013 if (dev_priv->flags & RADEON_IS_AGP) {
2014 // XXX turn off pcie gart
2015 } else
2016 #endif
2017 {
2018 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2019 /* if we have an offset set from userspace */
2020 if (!dev_priv->pcigart_offset_set) {
2021 DRM_ERROR("Need gart offset from userspace\n");
2022 r600_do_cleanup_cp(dev);
2023 return -EINVAL;
2024 }
2025
2026 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2027
2028 dev_priv->gart_info.bus_addr =
2029 dev_priv->pcigart_offset + dev_priv->fb_location;
2030 dev_priv->gart_info.mapping.offset =
2031 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2032 dev_priv->gart_info.mapping.size =
2033 dev_priv->gart_info.table_size;
2034
2035 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2036 if (!dev_priv->gart_info.mapping.handle) {
2037 DRM_ERROR("ioremap failed.\n");
2038 r600_do_cleanup_cp(dev);
2039 return -EINVAL;
2040 }
2041
2042 dev_priv->gart_info.addr =
2043 dev_priv->gart_info.mapping.handle;
2044
2045 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2046 dev_priv->gart_info.addr,
2047 dev_priv->pcigart_offset);
2048
2049 if (!r600_page_table_init(dev)) {
2050 DRM_ERROR("Failed to init GART table\n");
2051 r600_do_cleanup_cp(dev);
2052 return -EINVAL;
2053 }
2054
2055 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2056 r700_vm_init(dev);
2057 else
2058 r600_vm_init(dev);
2059 }
2060
2061 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2062 r700_cp_load_microcode(dev_priv);
2063 else
2064 r600_cp_load_microcode(dev_priv);
2065
2066 r600_cp_init_ring_buffer(dev, dev_priv);
2067
2068 dev_priv->last_buf = 0;
2069
2070 r600_do_engine_reset(dev);
2071 r600_test_writeback(dev_priv);
2072
2073 return 0;
2074 }
2075
2076 int r600_do_resume_cp(struct drm_device * dev)
2077 {
2078 drm_radeon_private_t *dev_priv = dev->dev_private;
2079
2080 DRM_DEBUG("\n");
2081 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2082 r700_vm_init(dev);
2083 r700_cp_load_microcode(dev_priv);
2084 } else {
2085 r600_vm_init(dev);
2086 r600_cp_load_microcode(dev_priv);
2087 }
2088 r600_cp_init_ring_buffer(dev, dev_priv);
2089 r600_do_engine_reset(dev);
2090
2091 return 0;
2092 }
2093
2094 /* Wait for the CP to go idle.
2095 */
2096 int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2097 {
2098 RING_LOCALS;
2099 DRM_DEBUG("\n");
2100
2101 BEGIN_RING(5);
2102 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2103 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2104 /* wait for 3D idle clean */
2105 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2106 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2107 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2108
2109 ADVANCE_RING();
2110 COMMIT_RING();
2111
2112 return r600_do_wait_for_idle(dev_priv);
2113 }
2114
2115 /* Start the Command Processor.
2116 */
2117 void r600_do_cp_start(drm_radeon_private_t * dev_priv)
2118 {
2119 u32 cp_me;
2120 RING_LOCALS;
2121 DRM_DEBUG("\n");
2122
2123 BEGIN_RING(7);
2124 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2125 OUT_RING(0x00000001);
2126 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2127 OUT_RING(0x00000003);
2128 else
2129 OUT_RING(0x00000000);
2130 OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2131 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2132 OUT_RING(0x00000000);
2133 OUT_RING(0x00000000);
2134 ADVANCE_RING();
2135 COMMIT_RING();
2136
2137 /* set the mux and reset the halt bit */
2138 cp_me = 0xff;
2139 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2140
2141 dev_priv->cp_running = 1;
2142
2143 }
2144
2145 void r600_do_cp_reset(drm_radeon_private_t * dev_priv)
2146 {
2147 u32 cur_read_ptr;
2148 DRM_DEBUG("\n");
2149
2150 cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2151 RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2152 SET_RING_HEAD(dev_priv, cur_read_ptr);
2153 dev_priv->ring.tail = cur_read_ptr;
2154 }
2155
2156 void r600_do_cp_stop(drm_radeon_private_t * dev_priv)
2157 {
2158 uint32_t cp_me;
2159
2160 DRM_DEBUG("\n");
2161
2162 cp_me = 0xff | R600_CP_ME_HALT;
2163
2164 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2165
2166 dev_priv->cp_running = 0;
2167 }
2168
2169 int r600_cp_dispatch_indirect(struct drm_device *dev,
2170 struct drm_buf *buf, int start, int end)
2171 {
2172 drm_radeon_private_t *dev_priv = dev->dev_private;
2173 RING_LOCALS;
2174
2175 if (start != end) {
2176 unsigned long offset = (dev_priv->gart_buffers_offset
2177 + buf->offset + start);
2178 int dwords = (end - start + 3) / sizeof(u32);
2179
2180 DRM_DEBUG("dwords:%d\n", dwords);
2181 DRM_DEBUG("offset 0x%lx\n", offset);
2182
2183
2184 /* Indirect buffer data must be a multiple of 16 dwords.
2185 * pad the data with a Type-2 CP packet.
2186 */
2187 while (dwords & 0xf) {
2188 u32 *data = (u32 *)
2189 ((char *)dev->agp_buffer_map->handle
2190 + buf->offset + start);
2191 data[dwords++] = RADEON_CP_PACKET2;
2192 }
2193
2194 /* Fire off the indirect buffer */
2195 BEGIN_RING(4);
2196 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2197 OUT_RING((offset & 0xfffffffc));
2198 OUT_RING((upper_32_bits(offset) & 0xff));
2199 OUT_RING(dwords);
2200 ADVANCE_RING();
2201 }
2202
2203 return 0;
2204 }
NetBSD on the FriendlyARM MINI2440