1 /* $NetBSD: omap2_intr.h,v 1.3 2008/08/27 11:03:10 matt Exp $ */
4 * Define the SDP2430 specific information and then include the generic OMAP
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10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain this list of conditions
13 * and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce this list of conditions
15 * and the following disclaimer in the documentation and/or other materials
16 * provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
19 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
20 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANY
21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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30 #ifndef _ARM_OMAP_OMAP2_INTR_H_
31 #define _ARM_OMAP_OMAP2_INTR_H_
33 #define ARM_IRQ_HANDLER _C_LABEL(omap_irq_handler)
38 #include <arm/armreg.h>
39 #include <arm/cpufunc.h>
41 uint32_t omap_microtimer_read(void);
42 uint32_t omap_microtimer_interval(uint32_t start
, uint32_t end
);
44 #define IRQ_EMUINT 0 /* MPU emulation (1) */
45 #define IRQ_COMMRX 1 /* MPU emulation (1) */
46 #define IRQ_COMMTX 2 /* MPU emulation (1) */
47 #define IRQ_BENCH 3 /* MPU emulation (1) */
48 #define IRQ_XTI 4 /* (2430) XTI module (2) (3) */
49 #define IRQ_MCBSP2_ST 4 /* (3530) Sidetone MCBSP2 overflow */
50 #define IRQ_XTI_WKUP 5 /* (2430) XTI module (3) */
51 #define IRQ_MCBSP3_ST 5 /* (3530) Sidetone MCBSP3 overflow */
52 #define IRQ_SSM_ABORT 6 /* (2430) MPU subsystem secure state-machine abort */
53 #define IRQ_SYS_nIRQ0 7 /* External interrupt (active low) */
54 #define IRQ_D2D_FW_STACKED 8 /* (2430) Occurs when modem does a security violation and has been automatically put DEVICE_SECURITY [0] under reset. */
55 #define IRQ_RSVD8 8 /* (3530) */
56 #define IRQ_SMX_DBG 9 /* (3530) SMX error for debug */
57 #define IRQ_RSVD9 9 /* Reserved */
58 #define IRQ_SMX_APP 10 /* (3530) SMX error for application */
59 #define IRQ_L3 10 /* (2420) L2 interconnect (transaction error) */
60 #define IRQ_SMX_APE_IA_ARM1136 10 /* (2430) Error flag for reporting application and unknown errors from SMX-APE (4) rd_wrSError_o */
61 #define IRQ_PRCM_MPU 11 /* PRCM */
62 #define IRQ_SDMA0 12 /* System DMA interrupt request 0 (5) */
63 #define IRQ_SDMA1 13 /* System DMA interrupt request 1 (5) */
64 #define IRQ_SDMA2 14 /* System DMA interrupt request 2 */
65 #define IRQ_SDMA3 15 /* System DMA interrupt request 3 */
66 #define IRQ_McBSP2_COMMON 16 /* (2430) McBSP2 common IRQ. This IRQ regroups all interrupt sources of the McBSPLP. Not backward-compatible with the previous McBSP. */
67 #define IRQ_McBSP3_COMMON 17 /* (2430) McBSP3 common IRQ. This IRQ regroups all interrupt sources of the McBSPLP. Not backward-compatible with the previous McBSP. */
68 #define IRQ_McBSP4_COMMON 18 /* (2430) McBSP4 common IRQ. This IRQ regroups all interrupt sources of the McBSPLP. Not backward-compatible with the previous McBSP. */
69 #define IRQ_SR1 18 /* (3530) SmartReflex 1 */
70 #define IRQ_McBSP5_COMMON 19 /* (2430) McBSP5 common IRQ. This IRQ regroups all interrupt sources of the McBSPLP. Not backward-compatible with the previous McBSP. */
71 #define IRQ_SR2 19 /* (3530) SmartReflex 2 */
72 #define IRQ_GPMC 20 /* General-purpose memory controller module */
73 #define IRQ_GFX 21 /* (2430) 2D/3D graphics module */
74 #define IRQ_RSVD22 22 /* Reserved */
75 #define IRQ_MCBSP3 22 /* McBSP module 3 */
76 #define IRQ_EAC 23 /* Audio Controller (2420) */
77 #define IRQ_MCBSP4 22 /* McBSP module 4 */
78 #define IRQ_CAM0 24 /* Camera interface interrupt request 0 */
79 #define IRQ_DSS 25 /* Display subsystem module (5) */
80 #define IRQ_MAIL_U0_MPU 26 /* Mailbox user 0 interrupt request */
81 #define IRQ_DSP_UMA 27 /* (2420) DSP UMA core s/w interrupt */
82 #define IRQ_MCBSP5 27 /* McBSP module 5 */
83 #define IRQ_DSP_MMU 28 /* (2420) DSP MMU interrupt */
84 #define IRQ_IVA2_MMU 28 /* (2430) IVA2 MMU interrupt */
85 #define IRQ_GPIO1_MPU 29 /* GPIO module 1 (5) (3) */
86 #define IRQ_GPIO2_MPU 30 /* GPIO module 2 (5) (3) */
87 #define IRQ_GPIO3_MPU 31 /* GPIO module 3 (5) (3) */
88 #define IRQ_GPIO4_MPU 32 /* GPIO module 4 (5) (3) */
89 #define IRQ_GPIO5_MPU 33 /* (2430/2530) GPIO module 5 */
90 #define IRQ_GPIO6_MPU 34 /* (3530) GPIO module 5 */
91 #define IRQ_MAIL_U2_MPU 34 /* (2420) Mailbox user 2 */
92 #define IRQ_WDT3 35 /* (2420) Watchdog timer module 3 overflow */
93 #define IRQ_USIM 35 /* (3530) USIM interrupt (HS devices only) */
94 #define IRQ_WDT4 36 /* (2420) Watchdog timer module 4 overflow */
95 #define IRQ_WDT3_3530 36 /* (3530) Watchdog timer module 3 overflow */
96 #define IRQ_IVA2WDT 36 /* (2430) IVA2 watchdog timer interrupt */
97 #define IRQ_GPT1 37 /* General-purpose timer module 1 */
98 #define IRQ_GPT2 38 /* General-purpose timer module 2 */
99 #define IRQ_GPT3 39 /* General-purpose timer module 3 */
100 #define IRQ_GPT4 40 /* General-purpose timer module 4 */
101 #define IRQ_GPT5 41 /* General-purpose timer module 5 (5) */
102 #define IRQ_GPT6 42 /* General-purpose timer module 6 (5) (3) */
103 #define IRQ_GPT7 43 /* General-purpose timer module 7 (5) (3) */
104 #define IRQ_GPT8 44 /* General-purpose timer module 8 (5) (3) */
105 #define IRQ_GPT9 45 /* General-purpose timer module 9 (3) */
106 #define IRQ_GPT10 46 /* General-purpose timer module 10 */
107 #define IRQ_GPT11 47 /* General-purpose timer module 11 (PWM) */
108 #define IRQ_GPT12 48 /* General-purpose timer module 12 (PWM) */
109 #define IRQ_SPI4_IRQ 48 /* (3530) McSPI module 4 */
110 #define IRQ_RSVD49 49 /* Reserved */
111 #define IRQ_SHA1MD5_2 49 /* (350) SHA-1/MD5 crypto-accelerator 2 */
112 #define IRQ_PKA 50 /* (2430) PKA crypto-accelerator */
113 #define IRQ_SHA1MD5 51 /* (2430) SHA-1/MD5 crypto-accelerator */
114 #define IRQ_RNG 52 /* (2430) RNG module */
115 #define IRQ_MG 53 /* (2430) MG function (5) */
116 #define IRQ_MCBSP4_TX 54 /* (2430) McBSP module 4 transmit (5) */
117 #define IRQ_MCBSP4_RX 55 /* (2430) McBSP module 4 receive (5) */
118 #define IRQ_I2C1 56 /* I2C module 1 */
119 #define IRQ_I2C2 57 /* I2C module 2 */
120 #define IRQ_HDQ 58 /* HDQ/1-wire */
121 #define IRQ_McBSP1_TX 59 /* McBSP module 1 transmit (5) */
122 #define IRQ_McBSP1_RX 60 /* McBSP module 1 receive (5) */
123 #define IRQ_MCBSP1_OVR 61 /* (2430) McBSP module 1 overflow interrupt (5) */
124 #define IRQ_I2C3 61 /* (3530) I2C module 3 */
125 #define IRQ_McBSP2_TX 62 /* McBSP module 2 transmit (5) */
126 #define IRQ_McBSP2_RX 63 /* McBSP module 2 receive (5) */
127 #define IRQ_McBSP1_COMMON 64 /* (2430) McBSP1 common IRQ. This IRQ regroups all the interrupt sources of the McBSPLP. Not backward compatible with previous McBSP. */
128 #define IRQ_FPKA_ERROR 64 /* (3530) PKA crypto-accelerator */
129 #define IRQ_SPI1 65 /* McSPI module 1 */
130 #define IRQ_SPI2 66 /* McSPI module 2 */
131 #define IRQ_SSI_P1_MPU0 67 /* (2430) Dual SSI port 1 interrupt request 0 (5) */
132 #define IRQ_SSI_P1_MPU1 68 /* (2430) Dual SSI port 1 interrupt request 1 (5) */
133 #define IRQ_SSI_P2_MPU0 69 /* (2430) Dual SSI port 2 interrupt request 0 (5) */
134 #define IRQ_SSI_P2_MPU1 70 /* (2430) Dual SSI port 2 interrupt request 1 (5) */
135 #define IRQ_SSI_GDD_MPU 71 /* (2430) Dual SSI GDD (5) */
136 #define IRQ_UART1 72 /* UART module 1 (3) */
137 #define IRQ_UART2 73 /* UART module 2 (3) */
138 #define IRQ_UART3 74 /* UART module 3 (also infrared) (5) (3) */
139 #define IRQ_PBIAS 75 /* (3530) Merged intr. for PBIASite 1 & 2 */
140 #define IRQ_USB_GEN 75 /* USB device general interrupt (3) */
141 #define IRQ_OCHI 76 /* (3530) OHCI controller HSUSB MP Host Interrupt */
142 #define IRQ_USB_NISO 76 /* USB device non-ISO (3) */
143 #define IRQ_EHCI 77 /* (3530) EHCI controller HSUSB MP Host Interrupt */
144 #define IRQ_USB_ISO 77 /* USB device ISO (3) */
145 #define IRQ_TLL 78 /* (3530) HSUSB MP TLL interrupt (3) */
146 #define IRQ_USB_HGEN 78 /* USB host general interrupt (3) */
147 #define IRQ_PARTHASH 79 /* (3530) SHA2/MD5 accel 1 */
148 #define IRQ_USB_HSOF 79 /* USB host start-of-frame (3) */
149 #define IRQ_USB_OTG 80 /* USB OTG */
150 #define IRQ_MCBSP5_TX 81 /* (2430/3530) McBSP module 5 transmit (5) */
151 #define IRQ_MCBSP5_RX 82 /* (2430/3530) McBSP module 5 receive (5) */
152 #define IRQ_MMC1 83 /* (2430/3530) MMC/SD module 1 (3) */
153 #define IRQ_MS 84 /* (2430/3530) MS-PRO module */
154 #define IRQ_FAC 85 /* (2430) FAC module */
155 #define IRQ_MMC2 86 /* (2430/3530) MMC/SD module 2 */
156 #define IRQ_ARM11_ICR 87 /* (2430) ARM11 ICR interrupt */
157 #define IRQ_MPU_ICR 87 /* (3530) MPU ICR interrupt */
158 #define IRQ_D2DFRINT 88 /* (2430) From 3G coprocessor hardware when used in chassis mode */
159 #define IRQ_MCBSP3_TX 89 /* (2430) McBSP module 3 transmit (5) */
160 #define IRQ_MCBSP3_RX 90 /* (2430) McBSP module 3 receive (5) */
161 #define IRQ_SPI3 91 /* (2430) Module McSPI 3 */
162 #define IRQ_HS_USB_MC 92 /* (2430) Module HS USB OTG controller (3) */
163 #define IRQ_HS_USB_MC 92 /* (2430) Module HS USB OTG controller (3) */
164 #define IRQ_Carkit 94 /* (2430) Carkit interrupt when the external HS USB transceiver is used in carkit mode (2) */
165 #define IRQ_MMC3 94 /* (3530) MMC/SD module 3 */
166 #define IRQ_GPT12_3530 95 /* (3530) GPT12 */
168 #define PIC_MAXSOURCES 96
169 #define PIC_MAXMAXSOURCES (96+160)
171 extern void omap_irq_handler(void *);
173 #include <arm/pic/picvar.h>
175 #endif /* ! _LOCORE */
177 #endif /* _ARM_OMAP_OMAP2_INTR_H_ */
