sys/arch/arm/omap/omap5912_intr.h

   1 /*      $NetBSD: $ */
   2
   3 /*
   4  * Define the OMAP5912 specific information and then include the generic OMAP
   5  * interrupt header.
   6  */
   7
   8 /*
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain this list of conditions
  13  *    and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce this list of conditions
  15  *    and the following disclaimer in the documentation and/or other materials
  16  *    provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  19  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
  20  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ANY
  21  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  22  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  23  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  24  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  25  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  26  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  27  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #ifndef _ARM_OMAP_OMAP5912_INTR_H_
  31 #define _ARM_OMAP_OMAP5912_INTR_H_
  32
  33 #ifndef _LOCORE
  34
  35 #define OMAP_INTC_DEVICE                "omap5912intc"
  36
  37 #define OMAP_INT_L1_NIRQ                32      /* Number of level 1 IRQs */
  38 #define OMAP_INT_L2_NIRQ                128     /* Number of level 2 IRQs */
  39 #define OMAP_INT_L2_IRQ                 0       /* L1 IRQ that L2 IRQs feed */
  40 #define OMAP_INT_L2_FIQ                 2       /* L1 IRQ that L2 FIQs feed */
  41 #define OMAP_FREE_IRQ_NUM               28      /* Number of free IRQs */
  42
  43 /*
  44  * The interrupt controller is used before we do the kernel configuration, so
  45  * we have to have the register addresses hard-coded in here, instead of being
  46  * able to get them from the config file.
  47  */
  48 #define OMAP_INT_L1_BASE        0xFFFECB00
  49 #define OMAP_INT_L2_BASE        0xFFFE0000
  50
  51 #endif /* ! _LOCORE */
  52
  53 #include <arm/omap/omap_intr.h>         /* Include the OMAP common header */
  54
  55 #endif /* _ARM_OMAP_OMAP5912_INTR_H_ */