sys/arch/evbarm/ixdp425/ixdp425_pci.c

   1 /*      $NetBSD: ixdp425_pci.c,v 1.5 2005/12/11 12:17:09 christos Exp $ */
   2 #define PCI_DEBUG
   3 /*
   4  * Copyright (c) 2003
   5  *      Ichiro FUKUHARA <ichiro@ichiro.org>.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
  21  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __KERNEL_RCSID(0, "$NetBSD: ixdp425_pci.c,v 1.5 2005/12/11 12:17:09 christos Exp $");
  32
  33 /*
  34  * IXDP425 PCI interrupt support.
  35  */
  36
  37 #include <sys/param.h>
  38 #include <sys/systm.h>
  39 #include <sys/device.h>
  40
  41 #include <machine/autoconf.h>
  42 #include <machine/bus.h>
  43
  44 #include <evbarm/ixdp425/ixdp425reg.h>
  45 #include <evbarm/ixdp425/ixdp425var.h>
  46
  47 #include <arm/xscale/ixp425reg.h>
  48 #include <arm/xscale/ixp425var.h>
  49
  50 #include <dev/pci/pcidevs.h>
  51 #include <dev/pci/ppbreg.h>
  52
  53 static int ixdp425_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
  54 static const char *ixdp425_pci_intr_string(void *, pci_intr_handle_t);
  55 static const struct evcnt *ixdp425_pci_intr_evcnt(void *, pci_intr_handle_t);
  56 static void *ixdp425_pci_intr_establish(void *, pci_intr_handle_t, int,
  57         int (*func)(void *), void *);
  58 static void ixdp425_pci_intr_disestablish(void *, void *);
  59
  60 void
  61 ixp425_md_pci_init(struct ixp425_softc *sc)
  62 {
  63         pci_chipset_tag_t pc = &sc->ia_pci_chipset;
  64         u_int32_t reg;
  65
  66         /*
  67          * PCI initialization
  68          */
  69         pc->pc_intr_v = sc;
  70         pc->pc_intr_map = ixdp425_pci_intr_map;
  71         pc->pc_intr_string = ixdp425_pci_intr_string;
  72         pc->pc_intr_evcnt = ixdp425_pci_intr_evcnt;
  73         pc->pc_intr_establish = ixdp425_pci_intr_establish;
  74         pc->pc_intr_disestablish = ixdp425_pci_intr_disestablish;
  75
  76         /* PCI Reset Assert */
  77         reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
  78         GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg & ~(1U << GPIO_PCI_RESET));
  79
  80         /* PCI Clock Disable */
  81         reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
  82         GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg & ~GPCLKR_MUX14);
  83
  84         /*
  85          * set GPIO Direction
  86          *      Output: PCI_CLK, PCI_RESET
  87          *      Input:  PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD
  88          */
  89         reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER);
  90         reg &= ~(1U << GPIO_PCI_CLK);
  91         reg &= ~(1U << GPIO_PCI_RESET);
  92         reg |= ((1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |
  93                 (1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD));
  94         GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg);
  95
  96         /* clear ISR */
  97         GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR,
  98                           (1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |
  99                           (1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD));
 100
 101         /* wait 1ms to satisfy "minimum reset assertion time" of the PCI spec */
 102         DELAY(1000);
 103         reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
 104         GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg |
 105                 (0xf << GPCLKR_CLK0DC_SHIFT) | (0xf << GPCLKR_CLK0TC_SHIFT));
 106
 107         /* PCI Clock Enable */
 108         reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
 109         GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg | GPCLKR_MUX14);
 110
 111         /*
 112          * wait 100us to satisfy "minimum reset assertion time from clock stable
 113          * requirement of the PCI spec
 114          */
 115         DELAY(100);
 116         /* PCI Reset deassert */
 117         reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
 118         GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg | (1U << GPIO_PCI_RESET));
 119
 120         /*
 121          * AHB->PCI address translation
 122          *      PCI Memory Map allocation in 0x48000000 (64MB)
 123          *      see. IXP425_PCI_MEM_HWBASE
 124          */
 125         PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b);
 126
 127         /*
 128          * PCI->AHB address translation
 129          *      begin at the physical memory start + OFFSET
 130          */
 131 #define AHB_OFFSET      0x10000000UL
 132         PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE,
 133                          (AHB_OFFSET & 0xFF000000) +
 134                         ((AHB_OFFSET & 0xFF000000) >> 8) +
 135                         ((AHB_OFFSET & 0xFF000000) >> 16) +
 136                         ((AHB_OFFSET & 0xFF000000) >> 24) +
 137                           0x00010203);
 138
 139         /* write Mapping registers PCI Configuration Registers */
 140         /* Base Address 0 - 3 */
 141         ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR0, AHB_OFFSET + 0x00000000);
 142         ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR1, AHB_OFFSET + 0x01000000);
 143         ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR2, AHB_OFFSET + 0x02000000);
 144         ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR3, AHB_OFFSET + 0x03000000);
 145
 146         /* Base Address 4 */
 147         ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR4, 0xffffffff);
 148
 149         /* Base Address 5 */
 150         ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR5, 0x00000000);
 151
 152         /* assert some PCI errors */
 153         PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE);
 154
 155         /*
 156          * Set up byte lane swapping between little-endian PCI
 157          * and the big-endian AHB bus
 158          */
 159         PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS);
 160
 161         /*
 162          * Enable bus mastering and I/O,memory access
 163          */
 164         ixp425_pci_conf_reg_write(sc, PCI_COMMAND_STATUS_REG,
 165                 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
 166                 PCI_COMMAND_MASTER_ENABLE);
 167 }
 168
 169 void
 170 ixp425_md_pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin,
 171     int swiz, int *ilinep)
 172 {
 173
 174         if (bus == 0)
 175                 *ilinep = ((swiz + (dev + pin - 1)) & 3);
 176         else
 177                 panic("ixp425_md_pci_conf_interrupt: unsupported bus number");
 178 }
 179
 180 #define IXP425_MAX_DEV  4
 181 #define IXP425_MAX_LINE 4
 182 static int
 183 ixdp425_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
 184 {
 185         static int ixp425_pci_table[IXP425_MAX_DEV][IXP425_MAX_LINE] =
 186         {
 187                 {PCI_INT_A, PCI_INT_B, PCI_INT_C, PCI_INT_D},
 188                 {PCI_INT_B, PCI_INT_C, PCI_INT_D, PCI_INT_A},
 189                 {PCI_INT_C, PCI_INT_D, PCI_INT_A, PCI_INT_B},
 190                 {PCI_INT_D, PCI_INT_A, PCI_INT_B, PCI_INT_C},
 191         };
 192
 193         int pin = pa->pa_intrpin;
 194         int dev = pa->pa_device;
 195
 196 #ifdef PCI_DEBUG
 197         void *v = pa->pa_pc;
 198         int line = pa->pa_intrline;
 199         pcitag_t intrtag = pa->pa_intrtag;
 200
 201         printf("ixdp425_pci_intr_map: v=%p, tag=%08lx intrpin=%d line=%d dev=%d\n",
 202                 v, intrtag, pin, line, dev);
 203 #endif
 204
 205         if (pin >= 1 && pin <= IXP425_MAX_LINE &&
 206             dev >= 1 && dev <= IXP425_MAX_DEV) {
 207                 *ihp = ixp425_pci_table[dev - 1][pin - 1];
 208                 return (0);
 209         } else {
 210                 printf("ixdp425_pci_intr_map: no mapping for %d/%d/%d\n",
 211                         pa->pa_bus, pa->pa_device, pa->pa_function);
 212                 return (1);
 213         }
 214 }
 215
 216 static const char *
 217 ixdp425_pci_intr_string(void *v, pci_intr_handle_t ih)
 218 {
 219         static char irqstr[IRQNAMESIZE];
 220
 221         sprintf(irqstr, "ixp425 irq %ld", ih);
 222         return (irqstr);
 223 }
 224
 225 static const struct evcnt *
 226 ixdp425_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
 227 {
 228         return (NULL);
 229 }
 230
 231 static void *
 232 ixdp425_pci_intr_establish(void *v, pci_intr_handle_t ih, int ipl,
 233     int (*func)(void *), void *arg)
 234 {
 235 #ifdef PCI_DEBUG
 236         printf("ixdp425_pci_intr_establish(v=%p, irq=%d, ipl=%d, func=%p, arg=%p)\n",
 237                 v, (int) ih, ipl, func, arg);
 238 #endif
 239
 240         return (ixp425_intr_establish(ih, ipl, func, arg));
 241 }
 242
 243 static void
 244 ixdp425_pci_intr_disestablish(void *v, void *cookie)
 245 {
 246 #ifdef PCI_DEBUG
 247         printf("ixdp425_pci_intr_disestablish(v=%p, cookie=%p)\n",
 248                 v, cookie);
 249 #endif
 250
 251         ixp425_intr_disestablish(cookie);
 252 }