| blob | 871ab92334651e5171718cb152deb74a96ced8e0 |
1 /*
2 * Machine dependant startup code for SDP2430 boards.
3 * Based on omap_start.S
4 *
5 * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved.
6 * Written by Hiroyuki Bessho for Genetec Corporation.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of Genetec Corporation may not be used to endorse or
17 * promote products derived from this software without specific prior
18 * written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 *
32 * Copyright (c) 2003
33 * Ichiro FUKUHARA <ichiro@ichiro.org>.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
44 *
45 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
48 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
49 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 * SUCH DAMAGE.
56 *
57 * Copyright (c) 2007 Microsoft
58 * All rights reserved.
59 *
60 * Redistribution and use in source and binary forms, with or without
61 * modification, are permitted provided that the following conditions
62 * are met:
63 * 1. Redistributions of source code must retain the above copyright
64 * notice, this list of conditions and the following disclaimer.
65 * 2. Redistributions in binary form must reproduce the above copyright
66 * notice, this list of conditions and the following disclaimer in the
67 * documentation and/or other materials provided with the distribution.
68 * 3. All advertising materials mentioning features or use of this software
69 * must display the following acknowledgement:
70 * This product includes software developed by Microsoft
71 *
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
73 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
74 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
75 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
76 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
77 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
78 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
82 * SUCH DAMAGE.
83 */
85 #include "opt_omap.h"
86 #include "opt_com.h"
87 #include "assym.h"
89 #include <machine/asm.h>
90 #include <arm/armreg.h>
91 #undef DOMAIN_CLIENT /* assym.h defines as 1, but pte.h defines as 0x01 */
92 #include <arm/arm32/pmap.h>
93 #include <arm/omap/omap2_obioreg.h>
94 #include <evbarm/tisdp24xx/sdp24xx.h>
96 RCSID("$NetBSD: sdp24xx_start.S,v 1.3 2008/08/27 11:03:10 matt Exp $")
98 #if 0
99 #define Invalidate_I_cache(reg) \
100 mcr p15, 0, reg, c7, c5, 0 /* Invalidate Entire I cache */
101 #else
102 /*
103 * Workaround Erratum 411920
104 *
105 * - value of arg 'reg' Should Be Zero
106 */
107 #define Invalidate_I_cache(reg) \
108 .p2align 5; \
109 mcr p15, 0, reg, c7, c5, 0; /* Invalidate Entire I cache */ \
110 mcr p15, 0, reg, c7, c5, 0; /* Invalidate Entire I cache */ \
111 mcr p15, 0, reg, c7, c5, 0; /* Invalidate Entire I cache */ \
112 mcr p15, 0, reg, c7, c5, 0; /* Invalidate Entire I cache */ \
113 nop; \
114 nop; \
115 nop; \
116 nop; \
117 nop; \
118 nop; \
119 nop; \
120 nop; \
121 nop; \
122 nop; \
123 nop;
124 #endif
126 /*
127 * Kernel start routine for OMAP 1136 boards.
128 * At this point, this code has been loaded into SDRAM
129 * and the MMU is off
130 */
131 .section .start,"ax",%progbits
133 .global _C_LABEL(sdp2430_start)
134 _C_LABEL(sdp2430_start):
135 /* Move into supervisor mode and disable IRQs/FIQs. */
136 mrs r0, cpsr
137 bic r0, r0, #PSR_MODE
138 orr r0, r0, #(I32_bit | F32_bit | PSR_SVC32_MODE)
139 msr cpsr, r0
141 /*
142 * Set up a preliminary mapping in the MMU to allow us to run
143 * at KERNEL_BASE with caches on.
144 */
145 /* Build page table from scratch */
146 ldr r0, Ltemp_l1_table
147 mov r1, r0 /* Save the page table address. */
148 /* Zero the entire table so all virtual addresses are invalid. */
149 mov r2, #L1_TABLE_SIZE /* in bytes */
150 mov r3, #0
151 mov r4, r3
152 mov r5, r3
153 mov r6, r3
154 mov r7, r3
155 mov r8, r3
156 mov r10, r3
157 mov r11, r3
158 1: stmia r1!, {r3-r8,r10-r11}
159 stmia r1!, {r3-r8,r10-r11}
160 stmia r1!, {r3-r8,r10-r11}
161 stmia r1!, {r3-r8,r10-r11}
162 subs r2, r2, #(4 * 4 * 8) /* bytes per loop */
163 bne 1b
165 /* Now create our entries per the mmu_init_table. */
166 l1table .req r0
167 va .req r1
168 pa .req r2
169 n_sec .req r3
170 attr .req r4
171 itable .req r5
172 l1sfrm .req r6
173 adr itable, mmu_init_table
174 ldr l1sfrm, Ll1_s_frame
175 b 3f
176 2: str pa, [l1table, va]
177 add va, va, #4
178 add pa, pa, #(L1_S_SIZE)
179 adds n_sec, n_sec, #-1
180 bhi 2b
181 3: ldmia itable!, {va,pa,n_sec,attr}
182 /* Convert va to l1 offset: va = 4 * (va >> L1_S_SHIFT) */
183 mov va, va, LSR #L1_S_SHIFT
184 mov va, va, LSL #2
185 /* Convert pa to l1 entry: pa = (pa & L1_S_FRAME) | attr */
186 and pa, pa, l1sfrm
187 orr pa, pa, attr
188 cmp n_sec, #0
189 bne 2b
190 .unreq va
191 .unreq pa
192 .unreq n_sec
193 .unreq attr
194 .unreq itable
195 .unreq l1table
196 .unreq l1sfrm
198 /*
199 * In theory, because the MMU is off, we shouldn't need all of this,
200 * but let's not take any chances and do a typical sequence to set
201 * the Translation Table Base.
202 */
204 Invalidate_I_cache(r0)
206 mcr p15, 0, r0, c7, c14, 0 /* Clean and Invalidate Entire Data Cache */
208 ldr r2, Lctl_ID_dis /* Disable I+D caches */
209 mrc p15, 0, r1, c1, c0, 0 /* " " " */
210 and r1, r1, r2 /* " " " */
211 mcr p15, 0, r1, c1, c0, 0 /* " " " */
213 #ifdef NOTYET
214 /*
215 * XXX Restrict cache size is reported to be unsupported on SDP2340
216 * XXX your CPU mileage may vary... as yet there is not generalized way to do this
217 */
218 ldr r2, Lauxctl_CZ_restrict /* Restrict cache size */
219 mrc p15, 0, r1, c1, c0, 1 /* " " " */
220 orr r1, r1, r2 /* " " " */
221 mcr p15, 0, r1, c1, c0, 1 /* " " " */
222 #endif
224 mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffers. */
225 mcr p15, 0, r0, c2, c0, 0 /* Set Translation Table Base */
226 mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */
228 /* Set the Domain Access register. Very important! */
229 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
230 mcr p15, 0, r0, c3, c0, 0
232 /*
233 * Enable the MMU, etc.
234 */
235 mrc p15, 0, r0, c1, c0, 0
236 ldr r1, Lcontrol_wax
237 and r0, r0, r1
238 ldr r1, Lcontrol_clr
239 mvn r1, r1
240 and r0, r0, r1
241 ldr r1, Lcontrol_set
242 orr r0, r0, r1
243 mcr p15, 0, r0, c1, c0, 0
245 /*
246 * Ensure that the coprocessor has finished turning on the MMU.
247 */
248 mrc p15, 0, r0, c2, c0, 0 /* Read an arbitrary value. */
249 mov r0, r0 /* Stall until read completes. */
251 /*
252 * Jump to start in locore.S, which in turn will call initarm and main.
253 */
254 b start /* Jump to start (flushes pipeline). */
255 nop
256 nop
257 nop
258 nop
260 /* NOTREACHED */
262 Ll1_s_frame:
263 .word L1_S_FRAME
264 Ltemp_l1_table:
265 /* Put the temporary L1 translation table at the end of SDRAM. */
266 .word 0x80000000 + MEMSIZE * 0x100000 - L1_TABLE_SIZE
268 /*
269 * Coprocessor register initialization values
270 */
271 # define CPU_AUXCTL_CZ (1 << 6) /* Restrict Cache Size */
273 /* bits to set in the Control Register */
274 Lcontrol_set:
275 .word CPU_CONTROL_MMU_ENABLE | \
276 CPU_CONTROL_AFLT_ENABLE | \
277 CPU_CONTROL_DC_ENABLE | \
278 CPU_CONTROL_WBUF_ENABLE | \
279 CPU_CONTROL_32BP_ENABLE | \
280 CPU_CONTROL_32BD_ENABLE | \
281 CPU_CONTROL_LABT_ENABLE | \
282 CPU_CONTROL_SYST_ENABLE | \
283 CPU_CONTROL_IC_ENABLE
285 /* bits to clear in the Control Register */
286 Lcontrol_clr:
287 .word 0
289 /* bits to "write as existing" in the Control Register */
290 Lcontrol_wax:
291 .word (3 << 30) | \
292 (1 << 29) | \
293 (1 << 28) | \
294 (3 << 26) | \
295 (3 << 19) | \
296 (1 << 17)
298 /* bits to disable the caches */
299 Lctl_ID_dis:
300 .word ~(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE)
302 /* bit to restrict cache size */
303 Lauxctl_CZ_restrict:
304 .word CPU_AUXCTL_CZ
307 /* We'll modify va and pa at run time so we can use relocatable addresses. */
308 #define MMU_INIT(va,pa,n_sec,attr) \
309 .word va ; \
310 .word pa ; \
311 .word n_sec ; \
312 .word attr ;
314 mmu_init_table:
315 /* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable */
316 MMU_INIT(KERNEL_BASE, KERNEL_BASE,
317 (MEMSIZE * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
318 L1_S_PROTO | L1_S_AP(AP_KRW) | L1_S_B | L1_S_C)
320 /* Map first 1MB of L4 CORE (so console will work) */
321 MMU_INIT(OMAP2430_L4_CORE_VBASE, OMAP2430_L4_CORE_BASE,
322 1,
323 L1_S_PROTO | L1_S_AP(AP_KRW))
325 /* Map first 1MB of L4 WAKEUP (so console will work) */
326 MMU_INIT(OMAP2430_L4_WAKEUP_VBASE, OMAP2430_L4_WAKEUP_BASE,
327 1,
328 L1_S_PROTO | L1_S_AP(AP_KRW))
330 /* end of table */
331 MMU_INIT(0, 0, 0, 0)