sys/arch/powerpc/pic/pic_mpcsoc.c

   1 /*      $NetBSD: pic_openpic.c,v 1.5 2008/04/29 06:53:02 martin Exp $ */
   2
   3 /*-
   4  * Copyright (c) 2007 Michael Lorenz
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  17  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  26  * POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __KERNEL_RCSID(0, "$NetBSD: pic_openpic.c,v 1.5 2008/04/29 06:53:02 martin Exp $");
  31
  32 #include <sys/param.h>
  33 #include <sys/malloc.h>
  34 #include <sys/kernel.h>
  35
  36 #include <uvm/uvm_extern.h>
  37
  38 #include <machine/pio.h>
  39 #include <powerpc/openpic.h>
  40
  41 #include <arch/powerpc/pic/picvar.h>
  42
  43 #include "opt_interrupt.h"
  44
  45 static void mpcpic_enable_irq(struct pic_ops *, int, int);
  46 static void mpcpic_disable_irq(struct pic_ops *, int);
  47 static void mpcpic_establish_irq(struct pic_ops *, int, int, int);
  48 static void mpcpic_finish_setup(struct pic_ops *);
  49
  50 static u_int steer8245[] = {
  51         0x10200,        /* external irq 0 direct/serial */
  52         0x10220,        /* external irq 1 direct/serial */
  53         0x10240,        /* external irq 2 direct/serial */
  54         0x10260,        /* external irq 3 direct/serial */
  55         0x10280,        /* external irq 4 direct/serial */
  56         0x102a0,        /* external irq 5 serial mode */
  57         0x102c0,        /* external irq 6 serial mode */
  58         0x102e0,        /* external irq 7 serial mode */
  59         0x10300,        /* external irq 8 serial mode */
  60         0x10320,        /* external irq 9 serial mode */
  61         0x10340,        /* external irq 10 serial mode */
  62         0x10360,        /* external irq 11 serial mode */
  63         0x10380,        /* external irq 12 serial mode */
  64         0x103a0,        /* external irq 13 serial mode */
  65         0x103c0,        /* external irq 14 serial mode */
  66         0x103e0,        /* external irq 15 serial mode */
  67         0x11020,        /* I2C */
  68         0x11040,        /* DMA 0 */
  69         0x11060,        /* DMA 1 */
  70         0x110c0,        /* MU/I2O */
  71         0x01120,        /* Timer 0 */
  72         0x01160,        /* Timer 1 */
  73         0x011a0,        /* Timer 2 */
  74         0x011e0,        /* Timer 3 */
  75         0x11120,        /* DUART 0, MPC8245 */
  76         0x11140,        /* DUART 1, MPC8245 */
  77 };
  78 #define MPCPIC_IVEC(n)  (steer8245[(n)])
  79 #define MPCPIC_IDST(n)  (steer8245[(n)] + 0x10)
  80
  81 static int i8259iswired = 0;
  82
  83 struct pic_ops *
  84 setup_mpcpic(void *addr)
  85 {
  86         struct openpic_ops *ops;
  87         struct pic_ops *self;
  88         int irq;
  89         u_int x;
  90
  91         openpic_base = addr;
  92         ops = malloc(sizeof(struct openpic_ops), M_DEVBUF, M_NOWAIT);
  93         KASSERT(ops != NULL);
  94         self = &ops->pic;
  95
  96         x = openpic_read(OPENPIC_FEATURE);
  97         if (((x & 0x07ff0000) >> 16) == 0)
  98                 panic("setup_mpcpic() called on distributed openpic");
  99
 100         aprint_normal("OpenPIC Version 1.%d: "
 101             "Supports %d CPUs and %d interrupt sources.\n",
 102             x & 0xff, ((x & 0x1f00) >> 8) + 1, ((x & 0x07ff0000) >> 16) + 1);
 103
 104 #ifdef PIC_I8259
 105         i8259iswired = 1;
 106 #endif
 107         self->pic_numintrs = ((x & 0x07ff0000) >> 16) + 1;
 108         self->pic_cookie = addr;
 109         self->pic_enable_irq = mpcpic_enable_irq;
 110         self->pic_reenable_irq = mpcpic_enable_irq;
 111         self->pic_disable_irq = mpcpic_disable_irq;
 112         self->pic_get_irq = opic_get_irq;
 113         self->pic_ack_irq = opic_ack_irq;
 114         self->pic_establish_irq = mpcpic_establish_irq;
 115         self->pic_finish_setup = mpcpic_finish_setup;
 116         ops->isu = NULL;
 117         ops->nrofisus = 0; /* internal only */
 118         ops->flags = 0; /* no flags (yet) */
 119         ops->irq_per = NULL; /* internal ISU only */
 120         strcpy(self->pic_name, "mpcpic");
 121         pic_add(self);
 122
 123         openpic_set_priority(0, 15);
 124         for (irq = 0; irq < self->pic_numintrs; irq++) {
 125                 /* make sure to keep disabled */
 126                 openpic_write(MPCPIC_IVEC(irq), OPENPIC_IMASK);
 127                 /* send all interrupts to CPU 0 */
 128                 openpic_write(MPCPIC_IDST(irq), 1 << 0);
 129         }
 130         openpic_write(OPENPIC_SPURIOUS_VECTOR, 0xff);
 131         openpic_set_priority(0, 0);
 132
 133         /* clear all pending interrunts */
 134         for (irq = 0; irq < self->pic_numintrs; irq++) {
 135                 openpic_read_irq(0);
 136                 openpic_eoi(0);
 137         }
 138
 139 #if 0
 140         printf("timebase freq=%d\n", openpic_read(0x10f0));
 141 #endif
 142         return self;
 143 }
 144
 145 void
 146 mpcpic_reserv16()
 147 {
 148         extern int max_base; /* intr.c */
 149
 150         /*
 151          * reserve 16 irq slot for the case when no i8259 exists to use.
 152          */
 153         max_base += 16;
 154 }
 155
 156 static void
 157 mpcpic_establish_irq(struct pic_ops *pic, int irq, int type, int pri)
 158 {
 159         int realpri = max(1, min(15, pri));
 160         u_int x;
 161
 162         x = irq;
 163         x |= OPENPIC_IMASK;
 164         x |= (i8259iswired && irq == 0) ?
 165             OPENPIC_POLARITY_POSITIVE : OPENPIC_POLARITY_NEGATIVE;
 166         x |= (type == IST_EDGE) ? OPENPIC_SENSE_EDGE : OPENPIC_SENSE_LEVEL;
 167         x |= realpri << OPENPIC_PRIORITY_SHIFT;
 168         openpic_write(MPCPIC_IVEC(irq), x);
 169
 170         aprint_debug("%s: setting IRQ %d to priority %d\n", __func__, irq,
 171             realpri);
 172 }
 173
 174 static void
 175 mpcpic_enable_irq(struct pic_ops *pic, int irq, int type)
 176 {
 177         u_int x;
 178
 179         x = openpic_read(MPCPIC_IVEC(irq));
 180         x &= ~OPENPIC_IMASK;
 181         openpic_write(MPCPIC_IVEC(irq), x);
 182 }
 183
 184 static void
 185 mpcpic_disable_irq(struct pic_ops *pic, int irq)
 186 {
 187         u_int x;
 188
 189         x = openpic_read(MPCPIC_IVEC(irq));
 190         x |= OPENPIC_IMASK;
 191         openpic_write(MPCPIC_IVEC(irq), x);
 192 }
 193
 194 static void
 195 mpcpic_finish_setup(struct pic_ops *pic)
 196 {
 197         uint32_t cpumask = 1;
 198         int i;
 199
 200         for (i = 0; i < pic->pic_numintrs; i++) {
 201                 /* send all interrupts to all active CPUs */
 202                 openpic_write(MPCPIC_IDST(i), cpumask);
 203         }
 204 }