sys/arch/sh3/sh3/cache.c

   1 /*      $NetBSD: cache.c,v 1.15 2008/04/28 20:23:35 martin Exp $        */
   2
   3 /*-
   4  * Copyright (c) 2002 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by UCHIYAMA Yasushi.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include <sys/cdefs.h>
  33 __KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.15 2008/04/28 20:23:35 martin Exp $");
  34
  35 #include "opt_cache.h"
  36 #include "opt_memsize.h"        /* IOM_RAM_BEGIN */
  37
  38 #include <sys/param.h>
  39 #include <sys/systm.h>
  40
  41 #include <sh3/cache.h>
  42 #include <sh3/cache_sh3.h>
  43 #include <sh3/cache_sh4.h>
  44
  45 /*
  46  * __cache_flush is used before sh_cache_config() is called.
  47  */
  48 static void __cache_flush(void);
  49
  50 struct sh_cache_ops sh_cache_ops = {
  51         ._icache_sync_all = (void (*)(void))__cache_flush,
  52         ._icache_sync_range = (void (*)(vaddr_t, vsize_t))__cache_flush,
  53         ._icache_sync_range_index = (void (*)(vaddr_t, vsize_t))__cache_flush,
  54         ._dcache_wbinv_all = (void (*)(void))__cache_flush,
  55         ._dcache_wbinv_range = (void (*)(vaddr_t, vsize_t))__cache_flush,
  56         ._dcache_wbinv_range_index = (void (*)(vaddr_t, vsize_t))__cache_flush,
  57         ._dcache_inv_range = (void (*)(vaddr_t, vsize_t))__cache_flush,
  58         ._dcache_wb_range = (void (*)(vaddr_t, vsize_t))__cache_flush
  59 };
  60
  61 int sh_cache_enable_icache;
  62 int sh_cache_enable_dcache;
  63 int sh_cache_write_through;
  64 int sh_cache_write_through_p0_u0_p3;
  65 int sh_cache_write_through_p1;
  66 int sh_cache_unified;
  67 int sh_cache_ways;
  68 int sh_cache_size_icache;
  69 int sh_cache_size_dcache;
  70 int sh_cache_line_size;
  71 int sh_cache_ram_mode;
  72 int sh_cache_index_mode_icache;
  73 int sh_cache_index_mode_dcache;
  74 int sh_cache_alias_mask;
  75 int sh_cache_prefer_mask;
  76
  77 void
  78 sh_cache_init(void)
  79 {
  80
  81 #ifdef CACHE_DEBUG
  82         return;
  83 #endif
  84 #ifdef SH3
  85         if (CPU_IS_SH3)
  86                 sh3_cache_config();
  87 #endif
  88 #ifdef SH4
  89         if (CPU_IS_SH4)
  90                 sh4_cache_config();
  91 #endif
  92 }
  93
  94 void
  95 sh_cache_information(void)
  96 {
  97
  98 #ifdef CACHE_DEBUG
  99         printf("*** USE CPU INDEPENDENT CACHE OPS. ***\n");
 100         return;
 101 #endif
 102
 103         /* I-cache or I/D-unified cache */
 104         aprint_normal("cpu0: %dKB/%dB",
 105                       sh_cache_size_icache >> 10,
 106                       sh_cache_line_size);
 107         if (sh_cache_ways > 1)
 108                 aprint_normal(" %d-way set-associative", sh_cache_ways);
 109         else
 110                 aprint_normal(" direct-mapped");
 111         if (sh_cache_unified)
 112                 aprint_normal(" I/D-unified cache.");
 113         else
 114                 aprint_normal(" Instruction cache.");
 115         if (!sh_cache_enable_icache)
 116                 aprint_normal(" DISABLED");
 117         if (sh_cache_unified && sh_cache_ram_mode)
 118                 aprint_normal(" RAM-mode");
 119         if (sh_cache_index_mode_icache)
 120                 aprint_normal(" INDEX-mode");
 121         aprint_normal("\n");
 122
 123         /* D-cache */
 124         if (!sh_cache_unified) {
 125                 aprint_normal("cpu0: %dKB/%dB",
 126                               sh_cache_size_dcache >> 10,
 127                               sh_cache_line_size);
 128                 if (sh_cache_ways > 1)
 129                         aprint_normal(" %d-way set-associative",
 130                                       sh_cache_ways);
 131                 else
 132                         aprint_normal(" direct-mapped");
 133                 aprint_normal(" Data cache.");
 134                 if (!sh_cache_enable_dcache)
 135                         aprint_normal(" DISABLED");
 136                 if (sh_cache_ram_mode)
 137                         aprint_normal(" RAM-mode");
 138                 if (sh_cache_index_mode_dcache)
 139                         aprint_normal(" INDEX-mode");
 140                 aprint_normal("\n");
 141         }
 142
 143         /* Write-through/back */
 144         aprint_normal("cpu0: U0, P0, P3 write-%s; P1 write-%s\n",
 145             sh_cache_write_through_p0_u0_p3 ? "through" : "back",
 146             sh_cache_write_through_p1 ? "through" : "back");
 147 }
 148
 149 /*
 150  * CPU-independent cache flush.
 151  */
 152 void
 153 __cache_flush(void)
 154 {
 155         volatile int *p = (int *)SH3_PHYS_TO_P1SEG(IOM_RAM_BEGIN);
 156         int i;
 157         int d;
 158
 159         /* Flush D-Cache */
 160         /*
 161          * Access address range [13:4].
 162          * max:
 163          * 16KB line-size 16B 4-way ... [11:4]  * 4
 164          * 16KB line-size 32B 1-way ... [13:5]
 165          */
 166         for (i = 0; i < 256/*entry*/ * 4/*way*/; i++) {
 167                 d = *p;
 168                 p += 4; /* next line index (16B) */
 169         }
 170
 171         /* Flush I-Cache */
 172         /*
 173          * this code flush I-cache. but can't compile..
 174          *  __asm volatile(".space 8192");
 175          *
 176          */
 177 }