sys/arch/arm/omap/omap2_icu.c

   1 /*      $NetBSD: omap2_icu.c,v 1.4 2008/08/27 11:03:10 matt Exp $       */
   2 /*
   3  * Define the SDP2430 specific information and then include the generic OMAP
   4  * interrupt header.
   5  */
   6
   7 /*
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain this list of conditions
  12  *    and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce this list of conditions
  14  *    and the following disclaimer in the documentation and/or other materials
  15  *    provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  18  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
  19  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ANY
  20  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  21  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  22  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  23  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  24  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  25  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  26  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28 #include "opt_omap.h"
  29
  30 #define _INTR_PRIVATE
  31
  32 #include <sys/cdefs.h>
  33 __KERNEL_RCSID(0, "$NetBSD: omap2_icu.c,v 1.4 2008/08/27 11:03:10 matt Exp $");
  34
  35 #include <sys/param.h>
  36 #include <sys/evcnt.h>
  37
  38 #include <uvm/uvm_extern.h>
  39
  40 #include <machine/intr.h>
  41 #include <machine/bus.h>
  42
  43 #include <arm/cpu.h>
  44 #include <arm/armreg.h>
  45 #include <arm/cpufunc.h>
  46 #include <arm/atomic.h>
  47
  48 #include <arm/omap/omap2_reg.h>
  49 #include <arm/omap/omap2_obiovar.h>
  50
  51
  52 #define INTC_READ(sc, g, o)             \
  53         bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (g) * 0x20 + (o))
  54 #define INTC_WRITE(sc, g, o, v) \
  55         bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (g) * 0x20 + (o), v)
  56
  57 static int omap2icu_match(device_t, cfdata_t, void *);
  58 static void omap2icu_attach(device_t, device_t, void *);
  59
  60 static void omap2icu_unblock_irqs(struct pic_softc *, size_t, uint32_t);
  61 static void omap2icu_block_irqs(struct pic_softc *, size_t, uint32_t);
  62 static void omap2icu_establish_irq(struct pic_softc *, struct intrsource *);
  63 #if 0
  64 static void omap2icu_source_name(struct pic_softc *, int, char *, size_t);
  65 #endif
  66
  67 static const struct pic_ops omap2icu_picops = {
  68         .pic_unblock_irqs = omap2icu_unblock_irqs,
  69         .pic_block_irqs = omap2icu_block_irqs,
  70         .pic_establish_irq = omap2icu_establish_irq,
  71 #if 0
  72         .pic_source_name = omap2icu_source_name,
  73 #endif
  74 };
  75
  76 #define PICTOSOFTC(pic) \
  77         ((void *)((uintptr_t)(pic) - offsetof(struct omap2icu_softc, sc_pic)))
  78
  79 static struct omap2icu_softc {
  80         device_t sc_dev;
  81         bus_space_tag_t sc_memt;
  82         bus_space_handle_t sc_memh;
  83         struct pic_softc sc_pic;
  84         uint32_t sc_enabled_irqs[3];
  85 } omap2icu_softc = {
  86         .sc_pic = {
  87                 .pic_ops = &omap2icu_picops,
  88                 .pic_maxsources = 96,
  89                 .pic_name = "omap2icu",
  90         },
  91 };
  92
  93 static void
  94 omap2icu_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
  95 {
  96         struct omap2icu_softc * const sc = PICTOSOFTC(pic);
  97         const size_t group = irqbase / 32;
  98         KASSERT((irq_mask & sc->sc_enabled_irqs[group]) == 0);
  99         sc->sc_enabled_irqs[group] |= irq_mask;
 100         INTC_WRITE(sc, group, INTC_MIR_CLEAR, irq_mask);
 101
 102         /* Force INTC to recompute IRQ availability */
 103         INTC_WRITE(sc, 0, INTC_CONTROL, INTC_CONTROL_NEWIRQAGR);
 104 }
 105
 106 static void
 107 omap2icu_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
 108 {
 109         struct omap2icu_softc * const sc = PICTOSOFTC(pic);
 110         const size_t group = irqbase / 32;
 111
 112         INTC_WRITE(sc, group, INTC_MIR_SET, irq_mask);
 113         sc->sc_enabled_irqs[group] &= ~irq_mask;
 114 }
 115
 116 /*
 117  * Called with interrupts disabled
 118  */
 119 static int
 120 find_pending_irqs(struct omap2icu_softc *sc, size_t group)
 121 {
 122         uint32_t pending = INTC_READ(sc, group, INTC_PENDING_IRQ);
 123
 124         KASSERT((sc->sc_enabled_irqs[group] & pending) == pending);
 125
 126         if (pending == 0)
 127                 return 0;
 128
 129         return pic_mark_pending_sources(&sc->sc_pic, group * 32, pending);
 130 }
 131
 132 void
 133 omap_irq_handler(void *frame)
 134 {
 135         struct cpu_info * const ci = curcpu();
 136         struct omap2icu_softc * const sc = &omap2icu_softc;
 137         const int oldipl = ci->ci_cpl;
 138         const uint32_t oldipl_mask = __BIT(oldipl);
 139         int ipl_mask = 0;
 140
 141         uvmexp.intrs++;
 142
 143         if (sc->sc_enabled_irqs[0])
 144                 ipl_mask |= find_pending_irqs(sc, 0);
 145         if (sc->sc_enabled_irqs[1])
 146                 ipl_mask |= find_pending_irqs(sc, 1);
 147         if (sc->sc_enabled_irqs[2])
 148                 ipl_mask |= find_pending_irqs(sc, 2);
 149
 150         /* force INTC to recomputq IRQ */
 151         INTC_WRITE(sc, 0, INTC_CONTROL, INTC_CONTROL_NEWIRQAGR);
 152
 153         /*
 154          * Record the pending_ipls and deliver them if we can.
 155          */
 156         if ((ipl_mask & ~oldipl_mask) > oldipl_mask)
 157                 pic_do_pending_ints(I32_bit, oldipl, frame);
 158 }
 159
 160 void
 161 omap2icu_establish_irq(struct pic_softc *pic, struct intrsource *is)
 162 {
 163         KASSERT(is->is_irq < 96);
 164         KASSERT(is->is_type == IST_LEVEL);
 165 }
 166
 167 int
 168 omap2icu_match(device_t parent, cfdata_t cf, void *aux)
 169 {
 170         struct obio_attach_args * const oa = aux;
 171
 172 #if defined(OMAP_2430) || defined(OMAP_2420)
 173         return oa->obio_addr == INTC_BASE;
 174 #elif defined(OMAP_3530)
 175         return oa->obio_addr == INTC_BASE_3530;
 176 #else
 177 #error unsupported OMAP variant
 178 #endif
 179 }
 180
 181 void
 182 omap2icu_attach(device_t parent, device_t self, void *aux)
 183 {
 184         struct obio_attach_args * const oa = aux;
 185         struct omap2icu_softc * const sc = &omap2icu_softc;
 186         int error;
 187
 188         aprint_normal("\n");
 189
 190         sc->sc_memt = oa->obio_iot;
 191
 192         error = bus_space_map(sc->sc_memt, oa->obio_addr, 0x1000, 0,
 193             &sc->sc_memh);
 194         if (error)
 195                 panic("failed to map interrupt registers: %d", error);
 196
 197         INTC_WRITE(sc, 0, INTC_MIR_SET, 0xffffffff);
 198         INTC_WRITE(sc, 1, INTC_MIR_SET, 0xffffffff);
 199         INTC_WRITE(sc, 2, INTC_MIR_SET, 0xffffffff);
 200
 201         sc->sc_dev = self;
 202         self->dv_private = sc;
 203
 204         pic_add(&sc->sc_pic, 0);
 205 }
 206
 207 CFATTACH_DECL_NEW(omap2icu,
 208     0,
 209     omap2icu_match, omap2icu_attach,
 210     NULL, NULL);