1 /* $NetBSD: omap5912_intr.c,v 1.1 2007/01/06 00:53:11 christos Exp $ */
4 * IRQ data specific to the Texas Instruments OMAP5912 processor.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain this list of conditions
12 * and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce this list of conditions
14 * and the following disclaimer in the documentation and/or other materials
15 * provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
18 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
19 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANY
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: omap5912_intr.c,v 1.1 2007/01/06 00:53:11 christos Exp $");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/malloc.h>
36 #include <machine/bus.h>
37 #include <machine/intr.h>
38 #include <machine/lock.h>
40 #include <arm/omap/omap_reg.h>
41 #include <arm/omap/omap_tipb.h>
46 CFATTACH_DECL_NEW(omap5912intc
, 0,
47 omapintc_match
, omapintc_attach
, NULL
, NULL
);
49 #define IRQ_TO_BANK_BASE(irq) \
50 (((irq) < OMAP_INT_L1_NIRQ) \
53 + (irq-OMAP_INT_L1_NIRQ)/OMAP_BANK_WIDTH*OMAP_INTL2_BANK_OFF)
54 #define IRQ_TO_BANK_NUM(irq) \
55 ((irq)/OMAP_BANK_WIDTH)
56 #define IRQ_TO_ILR(irq) \
57 (IRQ_TO_BANK_BASE(irq) + \
58 OMAP_INTB_ILR_BASE + \
59 (irq) % OMAP_BANK_WIDTH * 4)
60 #define IRQ_TO_MASK(irq) \
61 (1 << (irq) % OMAP_BANK_WIDTH)
63 #define INTR_INFO(irq,t) \
66 .bank_base = IRQ_TO_BANK_BASE(irq), \
67 .bank_num = IRQ_TO_BANK_NUM(irq), \
68 .ILR = IRQ_TO_ILR(irq), \
69 .mask = IRQ_TO_MASK(irq) \
72 const omap_intr_info_t omap_intr_info
[OMAP_NIRQ
] = {
73 INTR_INFO( 0, TRIG_LEVEL
), /* Level 2 IRQ */
74 INTR_INFO( 1, TRIG_LEVEL
), /* Camera IF */
75 INTR_INFO( 2, TRIG_LEVEL
), /* Level 2 FIQ */
76 INTR_INFO( 3, TRIG_LEVEL_OR_EDGE
), /* External FIQ */
77 INTR_INFO( 4, TRIG_EDGE
), /* McBSP2 TX */
78 INTR_INFO( 5, TRIG_EDGE
), /* McBSP2 RX */
79 INTR_INFO( 6, TRIG_EDGE
), /* IRQ_RTDX */
80 INTR_INFO( 7, TRIG_LEVEL
), /* IRQ_DSP_MMU_ABORT */
81 INTR_INFO( 8, TRIG_EDGE
), /* IRQ_HOST_INT */
82 INTR_INFO( 9, TRIG_LEVEL
), /* IRQ_ABORT */
83 INTR_INFO( 10, TRIG_LEVEL
), /* IRQ_DSP_MAILBOX1 */
84 INTR_INFO( 11, TRIG_LEVEL
), /* IRQ_DSP_MAILBOX2 */
85 INTR_INFO( 12, TRIG_LEVEL
), /* IRQ_LCD_LINE */
86 INTR_INFO( 13, TRIG_LEVEL
), /* Private TIPB Abort */
87 INTR_INFO( 14, TRIG_LEVEL
), /* IRQ1_GPIO1 */
88 INTR_INFO( 15, TRIG_LEVEL
), /* UART3 */
89 INTR_INFO( 16, TRIG_EDGE
), /* IRQ_TIMER3 */
90 INTR_INFO( 17, TRIG_LEVEL
), /* GPTIMER1 */
91 INTR_INFO( 18, TRIG_LEVEL
), /* GPTIMER2 */
92 INTR_INFO( 19, TRIG_LEVEL
), /* IRQ_DMA_CH0 */
93 INTR_INFO( 20, TRIG_LEVEL
), /* IRQ_DMA_CH1 */
94 INTR_INFO( 21, TRIG_LEVEL
), /* IRQ_DMA_CH2 */
95 INTR_INFO( 22, TRIG_LEVEL
), /* IRQ_DMA_CH3 */
96 INTR_INFO( 23, TRIG_LEVEL
), /* IRQ_DMA_CH4 */
97 INTR_INFO( 24, TRIG_LEVEL
), /* IRQ_DMA_CH5 */
98 INTR_INFO( 25, TRIG_LEVEL
), /* IRQ_DMA_CH_LCD */
99 INTR_INFO( 26, TRIG_EDGE
), /* IRQ_TIMER1 */
100 INTR_INFO( 27, TRIG_EDGE
), /* IRQ_WD_TIMER */
101 INTR_INFO( 28, TRIG_LEVEL
), /* Public TIPB Abort */
102 INTR_INFO( 30, TRIG_EDGE
), /* IRQ_TIMER2 */
103 INTR_INFO( 31, TRIG_EDGE
), /* IRQ_LCD_CTRL */
104 INTR_INFO(OMAP_INT_L1_NIRQ
+ 0, TRIG_LEVEL
), /* FAC */
105 INTR_INFO(OMAP_INT_L1_NIRQ
+ 1, TRIG_EDGE
), /* Keyboard */
106 INTR_INFO(OMAP_INT_L1_NIRQ
+ 2, TRIG_LEVEL
), /* uWIRE TX */
107 INTR_INFO(OMAP_INT_L1_NIRQ
+ 3, TRIG_LEVEL
), /* uWIRE RX */
108 INTR_INFO(OMAP_INT_L1_NIRQ
+ 4, TRIG_LEVEL
), /* I2C */
109 INTR_INFO(OMAP_INT_L1_NIRQ
+ 5, TRIG_LEVEL
), /* MPUIO */
110 INTR_INFO(OMAP_INT_L1_NIRQ
+ 6, TRIG_LEVEL
), /* USB HHC 1 */
111 INTR_INFO(OMAP_INT_L1_NIRQ
+ 7, TRIG_LEVEL
), /* USB HHC 2 */
112 INTR_INFO(OMAP_INT_L1_NIRQ
+ 8, TRIG_LEVEL
), /* USB_OTG */
113 INTR_INFO(OMAP_INT_L1_NIRQ
+ 10, TRIG_EDGE
), /* McBSP3 TX */
114 INTR_INFO(OMAP_INT_L1_NIRQ
+ 11, TRIG_EDGE
), /* McBSP3 RX */
115 INTR_INFO(OMAP_INT_L1_NIRQ
+ 12, TRIG_EDGE
), /* McBSP1 TX */
116 INTR_INFO(OMAP_INT_L1_NIRQ
+ 13, TRIG_EDGE
), /* McBSP1 RX */
117 INTR_INFO(OMAP_INT_L1_NIRQ
+ 14, TRIG_LEVEL
), /* UART1 */
118 INTR_INFO(OMAP_INT_L1_NIRQ
+ 15, TRIG_LEVEL
), /* UART2 */
119 INTR_INFO(OMAP_INT_L1_NIRQ
+ 16, TRIG_LEVEL
), /* MCSI1 */
120 INTR_INFO(OMAP_INT_L1_NIRQ
+ 17, TRIG_LEVEL
), /* MCSI2 */
121 INTR_INFO(OMAP_INT_L1_NIRQ
+ 18, TRIG_EDGE
), /* Free 1 */
122 INTR_INFO(OMAP_INT_L1_NIRQ
+ 20, TRIG_LEVEL
), /* USB Geni IT */
123 INTR_INFO(OMAP_INT_L1_NIRQ
+ 21, TRIG_LEVEL
), /* 1-Wire */
124 INTR_INFO(OMAP_INT_L1_NIRQ
+ 22, TRIG_EDGE
), /* OS timer */
125 INTR_INFO(OMAP_INT_L1_NIRQ
+ 23, TRIG_LEVEL
), /* MMC/SDIO1 */
126 INTR_INFO(OMAP_INT_L1_NIRQ
+ 24, TRIG_EDGE
), /* USB client wakeup */
127 INTR_INFO(OMAP_INT_L1_NIRQ
+ 25, TRIG_EDGE
), /* RTC periodic */
128 INTR_INFO(OMAP_INT_L1_NIRQ
+ 26, TRIG_LEVEL
), /* RTC alarm */
129 INTR_INFO(OMAP_INT_L1_NIRQ
+ 28, TRIG_LEVEL
), /* DSP_MMU_IRQ */
130 INTR_INFO(OMAP_INT_L1_NIRQ
+ 29, TRIG_LEVEL
), /* USB IRQ_ISO_ON */
131 INTR_INFO(OMAP_INT_L1_NIRQ
+ 30, TRIG_LEVEL
), /* USB IRQ_NON_ISO_ON */
132 INTR_INFO(OMAP_INT_L1_NIRQ
+ 34, TRIG_LEVEL
), /* GPTIMER3 */
133 INTR_INFO(OMAP_INT_L1_NIRQ
+ 35, TRIG_LEVEL
), /* GPTIMER4 */
134 INTR_INFO(OMAP_INT_L1_NIRQ
+ 36, TRIG_LEVEL
), /* GPTIMER5 */
135 INTR_INFO(OMAP_INT_L1_NIRQ
+ 37, TRIG_LEVEL
), /* GPTIMER6 */
136 INTR_INFO(OMAP_INT_L1_NIRQ
+ 38, TRIG_LEVEL
), /* GPTIMER7 */
137 INTR_INFO(OMAP_INT_L1_NIRQ
+ 39, TRIG_LEVEL
), /* GPTIMER8 */
138 INTR_INFO(OMAP_INT_L1_NIRQ
+ 40, TRIG_LEVEL
), /* IRQ1_GPIO2 */
139 INTR_INFO(OMAP_INT_L1_NIRQ
+ 41, TRIG_LEVEL
), /* IRQ1_GPIO3 */
140 INTR_INFO(OMAP_INT_L1_NIRQ
+ 42, TRIG_LEVEL
), /* MMC/SDIO2 */
141 INTR_INFO(OMAP_INT_L1_NIRQ
+ 43, TRIG_EDGE
), /* CompactFlash */
142 INTR_INFO(OMAP_INT_L1_NIRQ
+ 44, TRIG_LEVEL
), /* COMMRX */
143 INTR_INFO(OMAP_INT_L1_NIRQ
+ 45, TRIG_LEVEL
), /* COMMTX */
144 INTR_INFO(OMAP_INT_L1_NIRQ
+ 46, TRIG_EDGE
), /* Peripheral wake up */
145 INTR_INFO(OMAP_INT_L1_NIRQ
+ 47, TRIG_EDGE
), /* Free 2 */
146 INTR_INFO(OMAP_INT_L1_NIRQ
+ 48, TRIG_LEVEL
), /* IRQ1_GPIO4 */
147 INTR_INFO(OMAP_INT_L1_NIRQ
+ 49, TRIG_LEVEL
), /* SPI */
148 INTR_INFO(OMAP_INT_L1_NIRQ
+ 53, TRIG_LEVEL
), /* IRQ_DMA_CH6 */
149 INTR_INFO(OMAP_INT_L1_NIRQ
+ 54, TRIG_LEVEL
), /* IRQ_DMA_CH7 */
150 INTR_INFO(OMAP_INT_L1_NIRQ
+ 55, TRIG_LEVEL
), /* IRQ_DMA_CH8 */
151 INTR_INFO(OMAP_INT_L1_NIRQ
+ 56, TRIG_LEVEL
), /* IRQ_DMA_CH9 */
152 INTR_INFO(OMAP_INT_L1_NIRQ
+ 57, TRIG_LEVEL
), /* IRQ_DMA_CH10 */
153 INTR_INFO(OMAP_INT_L1_NIRQ
+ 58, TRIG_LEVEL
), /* IRQ_DMA_CH11 */
154 INTR_INFO(OMAP_INT_L1_NIRQ
+ 59, TRIG_LEVEL
), /* IRQ_DMA_CH12 */
155 INTR_INFO(OMAP_INT_L1_NIRQ
+ 60, TRIG_LEVEL
), /* IRQ_DMA_CH13 */
156 INTR_INFO(OMAP_INT_L1_NIRQ
+ 61, TRIG_LEVEL
), /* IRQ_DMA_CH14 */
157 INTR_INFO(OMAP_INT_L1_NIRQ
+ 62, TRIG_LEVEL
), /* IRQ_DMA_CH15 */
158 INTR_INFO(OMAP_INT_L1_NIRQ
+ 66, TRIG_EDGE
), /* Free 3 */
159 INTR_INFO(OMAP_INT_L1_NIRQ
+ 91, TRIG_LEVEL
), /* SHA1/MD5 */
160 INTR_INFO(OMAP_INT_L1_NIRQ
+ 92, TRIG_LEVEL
), /* RNG */
161 INTR_INFO(OMAP_INT_L1_NIRQ
+ 93, TRIG_LEVEL
), /* RNGIDLE */
162 INTR_INFO(OMAP_INT_L1_NIRQ
+103, TRIG_EDGE
), /* Free 4 */
163 INTR_INFO(OMAP_INT_L1_NIRQ
+104, TRIG_EDGE
), /* Free 5 */
164 INTR_INFO(OMAP_INT_L1_NIRQ
+105, TRIG_EDGE
), /* Free 6 */
165 INTR_INFO(OMAP_INT_L1_NIRQ
+106, TRIG_EDGE
), /* Free 7 */
166 INTR_INFO(OMAP_INT_L1_NIRQ
+107, TRIG_EDGE
), /* Free 8 */
167 INTR_INFO(OMAP_INT_L1_NIRQ
+108, TRIG_EDGE
), /* Free 9 */
168 INTR_INFO(OMAP_INT_L1_NIRQ
+109, TRIG_EDGE
), /* Free 10 */
169 INTR_INFO(OMAP_INT_L1_NIRQ
+110, TRIG_EDGE
), /* Free 11 */
170 INTR_INFO(OMAP_INT_L1_NIRQ
+111, TRIG_EDGE
), /* Free 12 */
171 INTR_INFO(OMAP_INT_L1_NIRQ
+112, TRIG_EDGE
), /* Free 13 */
172 INTR_INFO(OMAP_INT_L1_NIRQ
+113, TRIG_EDGE
), /* Free 14 */
173 INTR_INFO(OMAP_INT_L1_NIRQ
+114, TRIG_EDGE
), /* Free 15 */
174 INTR_INFO(OMAP_INT_L1_NIRQ
+115, TRIG_EDGE
), /* Free 16 */
175 INTR_INFO(OMAP_INT_L1_NIRQ
+116, TRIG_EDGE
), /* Free 17 */
176 INTR_INFO(OMAP_INT_L1_NIRQ
+117, TRIG_EDGE
), /* Free 18 */
177 INTR_INFO(OMAP_INT_L1_NIRQ
+118, TRIG_EDGE
), /* Free 19 */
178 INTR_INFO(OMAP_INT_L1_NIRQ
+119, TRIG_EDGE
), /* Free 20 */
179 INTR_INFO(OMAP_INT_L1_NIRQ
+120, TRIG_EDGE
), /* Free 21 */
180 INTR_INFO(OMAP_INT_L1_NIRQ
+121, TRIG_EDGE
), /* Free 22 */
181 INTR_INFO(OMAP_INT_L1_NIRQ
+122, TRIG_EDGE
), /* Free 23 */
182 INTR_INFO(OMAP_INT_L1_NIRQ
+123, TRIG_EDGE
), /* Free 24 */
183 INTR_INFO(OMAP_INT_L1_NIRQ
+124, TRIG_EDGE
), /* Free 25 */
184 INTR_INFO(OMAP_INT_L1_NIRQ
+125, TRIG_EDGE
), /* Free 26 */
185 INTR_INFO(OMAP_INT_L1_NIRQ
+126, TRIG_EDGE
), /* Free 27 */
186 INTR_INFO(OMAP_INT_L1_NIRQ
+127, TRIG_EDGE
), /* Free 28 */
189 /* Array of pointers to each bank's base. */
190 vaddr_t omap_intr_bank_bases
[OMAP_NBANKS
] = {
192 OMAP_INT_L2_BASE
+ 0*OMAP_INTL2_BANK_OFF
,
193 OMAP_INT_L2_BASE
+ 1*OMAP_INTL2_BANK_OFF
,
194 OMAP_INT_L2_BASE
+ 2*OMAP_INTL2_BANK_OFF
,
195 OMAP_INT_L2_BASE
+ 3*OMAP_INTL2_BANK_OFF
,
198 /* Array to translate from software interrupt numbers to an irq number. */
199 int omap_si_to_irq
[OMAP_FREE_IRQ_NUM
] = {
200 OMAP_INT_L1_NIRQ
+ 18, /* Free 1 */
201 OMAP_INT_L1_NIRQ
+ 47, /* Free 2 */
202 OMAP_INT_L1_NIRQ
+ 66, /* Free 3 */
203 OMAP_INT_L1_NIRQ
+103, /* Free 4 */
204 OMAP_INT_L1_NIRQ
+104, /* Free 5 */
205 OMAP_INT_L1_NIRQ
+105, /* Free 6 */
206 OMAP_INT_L1_NIRQ
+106, /* Free 7 */
207 OMAP_INT_L1_NIRQ
+107, /* Free 8 */
208 OMAP_INT_L1_NIRQ
+108, /* Free 9 */
209 OMAP_INT_L1_NIRQ
+109, /* Free 10 */
210 OMAP_INT_L1_NIRQ
+110, /* Free 11 */
211 OMAP_INT_L1_NIRQ
+111, /* Free 12 */
212 OMAP_INT_L1_NIRQ
+112, /* Free 13 */
213 OMAP_INT_L1_NIRQ
+113, /* Free 14 */
214 OMAP_INT_L1_NIRQ
+114, /* Free 15 */
215 OMAP_INT_L1_NIRQ
+115, /* Free 16 */
216 OMAP_INT_L1_NIRQ
+116, /* Free 17 */
217 OMAP_INT_L1_NIRQ
+117, /* Free 18 */
218 OMAP_INT_L1_NIRQ
+118, /* Free 19 */
219 OMAP_INT_L1_NIRQ
+119, /* Free 20 */
220 OMAP_INT_L1_NIRQ
+120, /* Free 21 */
221 OMAP_INT_L1_NIRQ
+121, /* Free 22 */
222 OMAP_INT_L1_NIRQ
+122, /* Free 23 */
223 OMAP_INT_L1_NIRQ
+123, /* Free 24 */
224 OMAP_INT_L1_NIRQ
+124, /* Free 25 */
225 OMAP_INT_L1_NIRQ
+125, /* Free 26 */
226 OMAP_INT_L1_NIRQ
+126, /* Free 27 */
227 OMAP_INT_L1_NIRQ
+127, /* Free 28 */
