sys/arch/arm/omap/omap_com.h

   1 /*      $NetBSD: $      */
   2
   3 /*
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain this list of conditions
   8  *    and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce this list of conditions
  10  *    and the following disclaimer in the documentation and/or other materials
  11  *    provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  14  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
  15  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ANY
  16  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  17  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  18  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  19  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  20  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  21  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  22  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  */
  24
  25 #ifndef _ARM_OMAP_OMAP_COM_H_
  26 #define _ARM_OMAP_OMAP_COM_H_
  27
  28 /*
  29  * Minimal defines for the bits and bytes we need.  We need these definitions
  30  * in both omap_com.c and the machdep startup file to get the console and kgdb
  31  * ports initialized.
  32  */
  33 #define OMAP_COM_SIZE                   1024    /* Per the OMAP TRM. */
  34
  35 /*
  36  * Registers 0x00 to 0x07 are pretty much 16550 compatible.  Let the com
  37  * driver handle them.
  38  */
  39
  40 /* Mode Definition Register 1 */
  41 #define OMAP_COM_MDR1                   0x08
  42 /* There are IrDA specific bits as well. */
  43 #define  OMAP_COM_MDR1_MODE_MASK                (7<<0)
  44 #define  OMAP_COM_MDR1_MODE_UART_16X            (0<<0)
  45 #define  OMAP_COM_MDR1_MODE_SIR                 (1<<0)
  46 #define  OMAP_COM_MDR1_MODE_UART_16X_AUTOBAUD   (2<<0)
  47 #define  OMAP_COM_MDR1_MODE_UART_13X            (3<<0)
  48 #define  OMAP_COM_MDR1_MODE_MIR                 (4<<0)
  49 #define  OMAP_COM_MDR1_MODE_FIR                 (5<<0)
  50 #define  OMAP_COM_MDR1_MODE_DISABLE             (7<<0)
  51
  52 /* Mode Definition Register 2 (0x09) is for IrDA */
  53
  54 /* Status FIFO Line Status and Transmit Frame Length Low (0x0A) are for IrDA */
  55 /* Resume and Transmit Frame Length High (0x0B) are for IrDA */
  56 /* Status FIFO Low and Received Frame Length Low (0x0C) are for IrDA */
  57 /* Status FIFO High and Received Frame Length High (0x0D) are for IrDA */
  58 /* BOF Control Register (0x0E) is for IrDA */
  59
  60 /* UART Autobauding Status Register */
  61 #define OMAP_COM_UASR                   0x0E
  62 #define  OMAP_COM_UASR_PARITY_MASK              (3<<6)
  63 #define   OMAP_COM_UASR_PARITY_NONE             (0<<6)
  64 #define   OMAP_COM_UASR_PARITY_SPACE            (1<<6)
  65 #define   OMAP_COM_UASR_PARITY_EVEN             (2<<6)
  66 #define   OMAP_COM_UASR_PARITY_ODD              (3<<6)
  67 #define  OMAP_COM_UASR_BIT_BY_CHAR_MASK         (1<<5)
  68 #define   OMAP_COM_UASR_BIT_BY_CHAR_7           (0<<5)
  69 #define   OMAP_COM_UASR_BIT_BY_CHAR_8           (1<<5)
  70 #define  OMAP_COM_UASR_SPEED_MASK               (0x1F<<0)
  71 #define   OMAP_COM_UASR_SPEED_NONE              (0x00<<0)
  72 #define   OMAP_COM_UASR_SPEED_115200            (0x01<<0)
  73 #define   OMAP_COM_UASR_SPEED_57600             (0x02<<0)
  74 #define   OMAP_COM_UASR_SPEED_38400             (0x03<<0)
  75 #define   OMAP_COM_UASR_SPEED_28800             (0x04<<0)
  76 #define   OMAP_COM_UASR_SPEED_19200             (0x05<<0)
  77 #define   OMAP_COM_UASR_SPEED_14400             (0x06<<0)
  78 #define   OMAP_COM_UASR_SPEED_9600              (0x07<<0)
  79 #define   OMAP_COM_UASR_SPEED_4800              (0x08<<0)
  80 #define   OMAP_COM_UASR_SPEED_2400              (0x09<<0)
  81 #define   OMAP_COM_UASR_SPEED_1200              (0x0A<<0)
  82
  83 /* Auxiliary Control Register (0x0F) is for IrDA */
  84
  85 /* Supplementary Control Register */
  86 #define OMAP_COM_SCR                    0x10
  87 #define  OMAP_COM_SCR_RX_TRIG_GRANU1            (1<<7)
  88 #define  OMAP_COM_SCR_TX_TRIG_GRANU1            (1<<6)
  89 #define  OMAP_COM_SCR_DSR_IT                    (1<<5)
  90 #define  OMAP_COM_SCR_RX_CTS_DSR_WAKE_UP_ENABLE (1<<4)
  91 #define  OMAP_COM_SCR_TX_EMPTY_CTL_IT           (1<<3)
  92 #define  OMAP_COM_SCR_DMA_MODE_2_0              (0<<1)
  93 #define  OMAP_COM_SCR_DMA_MODE_2_1              (1<<1)
  94 #define  OMAP_COM_SCR_DMA_MODE_2_2              (2<<1)
  95 #define  OMAP_COM_SCR_DMA_MODE_2_3              (3<<1)
  96 #define  OMAP_COM_SCR_DMA_MODE_CTL              (1<<0)
  97
  98 /* Supplementary Status Register */
  99 #define OMAP_COM_SSR                    0x11
 100 #define  OMAP_COM_SSR_RX_CTS_DSR_WAKE_UP_STS    (1<<1)
 101 #define  OMAP_COM_SSR_TX_FIFO_FULL              (1<<0)
 102
 103 /* BOF Length Register (0x12) is for IrDA */
 104
 105 /* Module Version Register */
 106 #define OMAP_COM_MVR                    0x14
 107 #define  OMAP_COM_MVR_MAJOR(r)                  ((r>>4) & 0x0F)
 108 #define  OMAP_COM_MVR_MINOR(r)                  ((r>>0) & 0x0F)
 109
 110 /* System Configuration Register */
 111 #define OMAP_COM_SYSC                   0x15
 112 #define  OMAP_COM_SYSC_FORCE_IDLE               (0<<3)
 113 #define  OMAP_COM_SYSC_NO_IDLE                  (1<<3)
 114 #define  OMAP_COM_SYSC_SMART_IDLE               (2<<3)
 115 #define  OMAP_COM_SYSC_ENA_WAKE_UP              (1<<2)
 116 #define  OMAP_COM_SYSC_SOFT_RESET               (1<<1)
 117 #define  OMAP_COM_SYSC_AUTOIDLE                 (1<<0)
 118
 119 /* System Status Register */
 120 #define OMAP_COM_SYSS                   0x16
 121 #define  OMAP_COM_SYSS_RESET_DONE               (1<<0)
 122
 123 /* Wake-Up Enable Register */
 124 #define OMAP_COM_WER                    0x17
 125 #define  OMAP_COM_WER_LINE_STATUS               (1<<6)
 126 #define  OMAP_COM_WER_RHR                       (1<<5)
 127 #define  OMAP_COM_WER_RX                        (1<<4)
 128 #define  OMAP_COM_WER_DCD                       (1<<3)
 129 #define  OMAP_COM_WER_RI                        (1<<2)
 130 #define  OMAP_COM_WER_DSR                       (1<<1)
 131 #define  OMAP_COM_WER_CTS                       (1<<0)
 132
 133 /* Base frequency */
 134 #define OMAP_COM_FREQ   48000000L
 135
 136 #endif /* _ARM_OMAP_OMAP_COM_H_ */