1 /* $NetBSD: gb225_slhci.c,v 1.3 2006/02/23 05:37:47 thorpej Exp $ */
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
33 * SL811HS USB host controller for GB-225 Option board of G4250EBX.
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/device.h>
40 #include <machine/bus.h>
41 #include <machine/cpu.h>
43 #include <dev/usb/usb.h>
44 #include <dev/usb/usbdi.h>
45 #include <dev/usb/usbdivar.h>
47 #include <dev/ic/sl811hsreg.h>
48 #include <dev/ic/sl811hsvar.h>
50 #include <arch/arm/xscale/pxa2x0reg.h>
51 #include <arch/arm/xscale/pxa2x0var.h>
52 #include <arch/evbarm/g42xxeb/g42xxeb_reg.h>
53 #include <arch/evbarm/g42xxeb/g42xxeb_var.h>
54 #include <arch/evbarm/g42xxeb/gb225reg.h>
55 #include <arch/evbarm/g42xxeb/gb225var.h>
57 struct slhci_opio_softc
{
58 struct slhci_softc sc_sc
;
63 static int slhci_opio_match(struct device
*, struct cfdata
*, void *);
64 static void slhci_opio_attach(struct device
*, struct device
*, void *);
65 static void slhci_opio_enable_power(void *, int);
66 static void slhci_opio_enable_intr(void *, int);
67 static int slhci_opio_intr(void *);
69 CFATTACH_DECL(slhci_opio
, sizeof(struct slhci_opio_softc
),
70 slhci_opio_match
, slhci_opio_attach
, NULL
, NULL
);
72 #define PORTSIZE (SL11_PORTSIZE*4)
75 slhci_opio_match(struct device
*parent
, struct cfdata
*cf
, void *aux
)
77 struct obio_attach_args
*oba
= aux
;
78 bus_space_tag_t iot
= &pxa2x0_a4x_bs_tag
; /* Use special BS funcs */
79 bus_space_handle_t ioh
;
80 struct obio_softc
*bsc
= (struct obio_softc
*)device_parent(parent
);
81 struct pxa2x0_softc
*psc
;
85 struct slhci_softc sc
;
87 obio_peripheral_reset(bsc
, 2, 0);
88 psc
= (struct pxa2x0_softc
*)device_parent(&bsc
->sc_dev
);
90 reg
= bus_space_read_4(psc
->saip
.sc_iot
, psc
->sc_memctl_ioh
,
93 bus_space_write_4(psc
->saip
.sc_iot
, psc
->sc_memctl_ioh
, MEMCTL_MSC2
,xxx
)
98 if (oba
->oba_addr
== OBIOCF_ADDR_DEFAULT
)
99 oba
->oba_addr
= PXA2X0_CS5_START
;
100 if (oba
->oba_intr
== OBIOCF_INTR_DEFAULT
)
101 oba
->oba_intr
= G4250EBX_INT_EXT2
;
103 if (bus_space_map(iot
, oba
->oba_addr
, PORTSIZE
, 0, &ioh
))
106 /* construct fake softc to call sl811hs */
109 type
= sl811hs_find(&sc
);
111 bus_space_unmap(iot
, ioh
, PORTSIZE
);
117 slhci_opio_attach(struct device
*parent
, struct device
*self
, void *aux
)
119 struct slhci_opio_softc
*sc
= (struct slhci_opio_softc
*)self
;
120 struct obio_attach_args
*oba
= aux
;
121 struct opio_softc
*psc
=
122 (struct opio_softc
*)device_parent(self
);
123 struct obio_softc
*bsc
=
124 (struct obio_softc
*)device_parent(&psc
->sc_dev
);
125 bus_space_tag_t iot
= oba
->oba_iot
;
126 bus_space_handle_t ioh
;
131 if (bus_space_map(iot
, oba
->oba_addr
, PORTSIZE
, 0, &ioh
)) {
132 printf("%s: can't map I/O space\n",
133 sc
->sc_sc
.sc_bus
.bdev
.dv_xname
);
138 sc
->sc_sc
.sc_iot
= iot
;
139 sc
->sc_sc
.sc_ioh
= ioh
;
140 sc
->sc_sc
.sc_dmat
= &pxa2x0_bus_dma_tag
; /* XXX */
141 sc
->sc_sc
.sc_enable_power
= slhci_opio_enable_power
;
142 sc
->sc_sc
.sc_enable_intr
= slhci_opio_enable_intr
;
143 sc
->sc_sc
.sc_arg
= sc
;
145 /* Establish the interrupt handler */
146 sc
->sc_ih
= obio_intr_establish(bsc
, oba
->oba_intr
, IPL_BIO
,
147 IST_LEVEL_HIGH
, slhci_opio_intr
, sc
);
148 if( sc
->sc_ih
== NULL
) {
149 printf("%s: can't establish interrupt\n",
150 sc
->sc_sc
.sc_bus
.bdev
.dv_xname
);
155 /* Reset controller */
156 obio_peripheral_reset(bsc
, 2, 1);
158 obio_peripheral_reset(bsc
, 2, 0);
162 bus_space_write_1(iot
, ioh
, SL11_IDX_ADDR
, SL11_CTRL
);
163 bus_space_write_1(iot
, ioh
, SL11_IDX_DATA
, 0x01);
165 /* Attach SL811HS/T */
166 if (slhci_attach(&sc
->sc_sc
, self
))
171 slhci_opio_enable_power(void *arg
, int mode
)
174 struct slhci_opio_softc
*sc
= arg
;
175 bus_space_tag_t iot
= sc
->sc_sc
.sc_iot
;
178 r
= bus_space_read_1(iot
, sc
->sc_nch
, NEREID_CTRL
);
179 if (mode
== POWER_ON
)
180 bus_space_write_1(iot
, sc
->sc_nch
, NEREID_CTRL
,
181 r
| NEREID_CTRL_POWER
);
183 bus_space_write_1(iot
, sc
->sc_nch
, NEREID_CTRL
,
184 r
& ~NEREID_CTRL_POWER
);
189 slhci_opio_enable_intr(void *arg
, int mode
)
191 struct slhci_opio_softc
*sc
= arg
;
192 struct obio_softc
*bsc
;
194 bsc
= (struct obio_softc
*)device_parent(
195 device_parent(&sc
->sc_sc
.sc_bus
.bdev
));
198 obio_intr_unmask(bsc
, sc
->sc_ih
);
200 obio_intr_mask(bsc
, sc
->sc_ih
);
204 slhci_opio_intr(void *arg
)
206 struct slhci_opio_softc
*sc
= arg
;
208 return slhci_intr(&sc
->sc_sc
);