sys/arch/hpcmips/tx/tx39timerreg.h

   1 /*      $NetBSD: tx39timerreg.h,v 1.4 2000/09/28 16:18:26 uch Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by UCHIYAMA Yasushi.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * Toshiba TX3912/3922 Timer module
  34  */
  35 #define TX39_TIMERRTCHI_REG             0x140
  36 #define TX39_TIMERRTCLO_REG             0x144
  37 #define TX39_TIMERALARMHI_REG           0x148
  38 #define TX39_TIMERALARMLO_REG           0x14C
  39 #define TX39_TIMERCONTROL_REG           0x150
  40 #define TX39_TIMERPERIODIC_REG          0x154
  41
  42 /* Periodic timer (1.15MHz) */
  43 #ifdef TX391X
  44 /*
  45  * TX3912 base clock is 36.864MHz
  46  */
  47 #define TX39_TIMERCLK                   1152000
  48 #endif
  49 #ifdef TX392X
  50 /*
  51  * TX3922 base clock seems to be 32.25MHz (Telios)
  52  */
  53 #define TX39_TIMERCLK                   1007812
  54 #endif
  55
  56 /* Real timer clock (32.768kHz) */
  57 #define TX39_RTCLOCK                    32768
  58 #define TX39_MSEC2RTC(m)                ((TX39_RTCLOCK * (m)) / 1000)
  59
  60 /*
  61  *      RTC Register High/Low
  62  */
  63 /* R */
  64 #define TX39_TIMERRTCHI_SHIFT           0
  65 #ifdef TX391X
  66 #define TX39_TIMERRTCHI_MASK            0xff
  67 #endif /* TX391X */
  68 #ifdef TX392X
  69 #define TX39_TIMERRTCHI_MASK            0x7ff
  70 #endif /* TX392X */
  71
  72 #define TX39_TIMERRTCHI(cr)             ((cr) & TX39_TIMERRTCHI_MASK)
  73
  74 /*
  75  *      Alarm Register High/Low
  76  */
  77 /* R/W */
  78 #ifdef TX391X /* 40bit */
  79 #define TX39_TIMERALARMHI_SHIFT         0
  80 #define TX39_TIMERALARMHI_MASK          0xff
  81 #endif /* TX391X */
  82 #ifdef TX392X /* 43bit */
  83 #define TX39_TIMERALARMHI_SHIFT         0
  84 #define TX39_TIMERALARMHI_MASK          0x7ff
  85 #endif /* TX392X */
  86
  87 #define TX39_TIMERALARMHI(cr)           ((cr) & TX39_TIMERALARMHI_MASK)
  88
  89 /*
  90  *      Timer Control Register
  91  */
  92 #define TX39_TIMERCONTROL_FREEZEPRE     0x00000080
  93 #define TX39_TIMERCONTROL_FREEZERTC     0x00000040
  94 #define TX39_TIMERCONTROL_FREEZETIMER   0x00000020
  95 #define TX39_TIMERCONTROL_ENPERTIMER    0x00000010
  96 #define TX39_TIMERCONTROL_RTCCLR        0x00000008
  97 #define TX39_TIMERCONTROL_TESTCMS       0x00000004      /* Don't set */
  98 #define TX39_TIMERCONTROL_ENTESTCLK     0x00000002      /* Don't set */
  99 #define TX39_TIMERCONTROL_ENRTCTST      0x00000001
 100
 101 /*
 102  *      Periodic Timer Register
 103  */
 104 /* R */
 105 #define TX39_TIMERPERIODIC_PERCNT_SHIFT 15
 106 #define TX39_TIMERPERIODIC_PERCNT_MASK  0xffff
 107 #define TX39_TIMERPERIODIC_PERCNT(cr)                                   \
 108         (((cr) >> TX39_TIMERPERIODIC_PERCNT_SHIFT) &                    \
 109         TX39_TIMERPERIODIC_PERCNT_MASK)
 110 /* R/W */
 111 #define TX39_TIMERPERIODIC_PERVAL_SHIFT 0
 112 #define TX39_TIMERPERIODIC_PERVAL_MASK  0xffff
 113 #define TX39_TIMERPERIODIC_PERVAL(cr)                                   \
 114         (((cr) >> TX39_TIMERPERIODIC_PERVAL_SHIFT) &                    \
 115         TX39_TIMERPERIODIC_PERVAL_MASK)
 116 #define TX39_TIMERPERIODIC_PERVAL_SET(cr, val)                          \
 117         ((cr) | (((val) << TX39_TIMERPERIODIC_PERVAL_SHIFT) &           \
 118         (TX39_TIMERPERIODIC_PERVAL_MASK << TX39_TIMERPERIODIC_PERVAL_SHIFT)))
 119 #define TX39_TIMERPERIODIC_PERVAL_CLR(cr) ((cr) &=                      \
 120          ~(TX39_TIMERPERIODIC_PERVAL_MASK << TX39_TIMERPERIODIC_PERVAL_SHIFT))
 121 #define TX39_TIMERPERIODIC_INTRRATE(val)                                \
 122         ((val) + 1)/TX39_TIMERCLK /* unit:Hz */
 123