1 /* $NetBSD: dcr403cgx.h,v 1.3 2006/05/30 22:44:13 freza Exp $ */
4 * Copyright (c) 2003 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Juergen Hannken-Illjes.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 #ifndef _DCR403GCXP_H_
33 #define _DCR403GCXP_H_
35 /* Device Control Register declarations */
37 #define DCR_EXISR 0x040 /* External Interrupt Status Register */
38 #define DCR_EXIER 0x042 /* External Interrupt Enable Register */
39 #define DCR_BRH0 0x070 /* Bank Register High 0 */
40 #define DCR_BRH1 0x071 /* Bank Register High 1 */
41 #define DCR_BRH2 0x072 /* Bank Register High 2 */
42 #define DCR_BRH3 0x073 /* Bank Register High 3 */
43 #define DCR_BRH4 0x074 /* Bank Register High 4 */
44 #define DCR_BRH5 0x075 /* Bank Register High 5 */
45 #define DCR_BRH6 0x076 /* Bank Register High 6 */
46 #define DCR_BRH7 0x077 /* Bank Register High 7 */
47 #define DCR_BR0 0x080 /* Bank Register 0 */
48 #define DCR_BR1 0x081 /* Bank Register 1 */
49 #define DCR_BR2 0x082 /* Bank Register 2 */
50 #define DCR_BR3 0x083 /* Bank Register 3 */
51 #define DCR_BR4 0x084 /* Bank Register 4 */
52 #define DCR_BR5 0x085 /* Bank Register 5 */
53 #define DCR_BR6 0x086 /* Bank Register 6 */
54 #define DCR_BR7 0x087 /* Bank Register 7 */
55 #define DCR_BEAR 0x090 /* Bus Error Address Register */
56 #define DCR_BESR 0x091 /* Bus Error Syndrome Register */
57 #define DCR_IOCR 0x0a0 /* I/O Configuration Register */
58 #define DCR_DMACR0 0x0c0 /* DMA Channel Control Register 0 */
59 #define DCR_DMACT0 0x0c1 /* DMA Count Register 0 */
60 #define DCR_DMADA0 0x0c2 /* DMA Destination Address Reg. 0 */
61 #define DCR_DMASA0 0x0c3 /* DMA Source Address Register 0 */
62 #define DCR_DMACC0 0x0c4 /* DMA Chained Count 0 */
63 #define DCR_DMACR1 0x0c8 /* DMA Channel Control Register 1 */
64 #define DCR_DMACT1 0x0c9 /* DMA Count Register 1 */
65 #define DCR_DMADA1 0x0cA /* DMA Destination Address Reg. 1 */
66 #define DCR_DMACC1 0x0cC /* DMA Chained Count 1 */
67 #define DCR_DMASA1 0x0cb /* DMA Source Address Register 1 */
68 #define DCR_DMACR2 0x0d0 /* DMA Channel Control Register 2 */
69 #define DCR_DMACT2 0x0d1 /* DMA Count Register 2 */
70 #define DCR_DMADA2 0x0d2 /* DMA Destination Address Reg. 2 */
71 #define DCR_DMASA2 0x0d3 /* DMA Source Address Register 2 */
72 #define DCR_DMACC2 0x0d4 /* DMA Chained Count 2 */
73 #define DCR_DMACR3 0x0d8 /* DMA Channel Control Register 3 */
74 #define DCR_DMACT3 0x0d9 /* DMA Count Register 3 */
75 #define DCR_DMADA3 0x0da /* DMA Destination Address Reg. 3 */
76 #define DCR_DMASA3 0x0db /* DMA Source Address Register 3 */
77 #define DCR_DMACC3 0x0dc /* DMA Chained Count 3 */
78 #define DCR_DMASR 0x0e0 /* DMA Status Register */
80 #endif /* _DCR403GCXP_H_ */
