| blob | 2206c2b4fb11674dfaeb8a45aeb15a711fc67109 |
1 /* $NetBSD: dcr405xx.h,v 1.4 2005/12/24 22:45:36 perry Exp $ */
3 /*
4 * Copyright (c) 2004 Shigeyuki Fukushima.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above
13 * copyright notice, this list of conditions and the following
14 * disclaimer in the documentation and/or other materials provided
15 * with the distribution.
16 * 3. The name of the author may not be used to endorse or promote
17 * products derived from this software without specific prior
18 * written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
21 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
26 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
29 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 #ifndef _IBM4XX_DCR405XX_H_
34 #define _IBM4XX_DCR405XX_H_
36 /*
37 * Declarations of DCRs (Device Control Registers)
38 * for AMCC(IBM) PowerPC 405 series
39 * 405CR/NPe405L/NPe405H/405EP/405GP/405GPr
40 */
42 /*****************************************************************************/
43 /*
44 * Memory Controller Registers (0x010-0x011)
45 *
46 * [DCRs]
47 * DCR_SDRAM0_CFGADDR Read/Write 0x010
48 * SDRAM Controller Address Register
49 * DCR_SDRAM0_CFGDATA Read/Write 0x011
50 * SDRAM Controller Data Register
51 *
52 * [Indirectly accessed SDRAM Configuration and Status Registers]
53 * SDRAM0_BESR0 Read/Clear 0x00
54 * Bus Error Syndrome Register 0
55 * 0 DCE SDRAM Controller Enable
56 * 1 SRE Self-Refresh Enable
57 * 2 PME Power Management Enable
58 * 3 MEMCHK Memory Data Error Checking
59 * 4 REGEN Registered Memory Enable
60 * 5:6 DRW SDRAM Width
61 * 7:8 BRPF Burst Read Prefetch Granularity
62 * 9 ECCDD ECC Drive Disable
63 * 10 EMDULR Enable Memory Data Unless Read
64 * 11:31 Reserved
65 * SDRAM0_BESR1 Read/Clear 0x08
66 * Bus Error Syndrome Register 1
67 * SDRAM0_BEAR Read 0x10
68 * Bus Error Address Register
69 * SDRAM0_CFG Read/Write 0x20
70 * SDRAM Configuration
71 * SDRAM0_STATUS Read 0x24
72 * SDRAM Controller Status
73 * 0 MRSCMP Mode Register Set Complete
74 * 1 SRSTATUS Self-Refresh State
75 * 2:31 Reserved
76 * SDRAM0_RTR Read/Write 0x30
77 * Refresh Timer Register
78 * SDRAM0_PMIT Read/Write 0x34
79 * Power Management Idle Timer
80 * SDRAM0_BnCR Read/Write 0x40,0x44,
81 * Memory Bank Configuration Register (n = 0-3) 0x48,0x4c
82 * 0:9 BA Base Address
83 * 10:11 Reserved
84 * 12:14 SZ Size
85 * 15 Reserved
86 * 16:18 AM Addressing Mode
87 * 19:30 Reserved
88 * 31 BE Memory Bank Enable
89 * SDRAM0_TR Read/Write 0x80
90 * SDRAM Timing Register
91 * SDRAM0_ECCCFG Read/Write 0x94
92 * ECC Configuration
93 * SDRAM0_ECCESR Read/Clear 0x98
94 * ECC Error Status
95 */
97 #define DCR_SDRAM0_CFGADDR (0x010)
98 #define DCR_SDRAM0_CFGDATA (0x011)
100 #define SDRAM0_BESR0 (0x00)
101 #define SDRAM0_BESR0_EET0 (0xe0000000)
102 #define SDRAM0_BESR0_RWS0 (0x10000000)
103 #define SDRAM0_BESR0_EET1 (0x03800000)
104 #define SDRAM0_BESR0_RWS1 (0x00400000)
105 #define SDRAM0_BESR0_EET2 (0x000e0000)
106 #define SDRAM0_BESR0_RWS2 (0x00010000)
107 #define SDRAM0_BESR0_EET3 (0x00003800)
108 #define SDRAM0_BESR0_RWS3 (0x00000400)
109 #define SDRAM0_BESR0_FL3 (0x00000200)
110 #define SDRAM0_BESR0_AL3 (0x00000100)
111 #define SDRAM0_BESR1 (0x08)
112 #define SDRAM0_BESR1_EET4 (0xe0000000)
113 #define SDRAM0_BESR1_RWS4 (0x10000000)
114 #define SDRAM0_BESR1_FL4 (0x08000000)
115 #define SDRAM0_BESR1_AL4 (0x04000000)
116 #define SDRAM0_BESR1_EET5 (0x03800000)
117 #define SDRAM0_BESR1_RWS5 (0x00400000)
118 #define SDRAM0_BEAR (0x10)
119 #define SDRAM0_CFG (0x20)
120 #define SDRAM0_CFG_DCE (0x80000000)
121 #define SDRAM0_CFG_SRE (0x40000000)
122 #define SDRAM0_CFG_PME (0x20000000)
123 #define SDRAM0_CFG_MEMCHK (0x10000000)
124 #define SDRAM0_CFG_REGEN (0x08000000)
125 #define SDRAM0_CFG_DRW (0x06000000)
126 #define SDRAM0_CFG_BRPF (0x01800000)
127 #define SDRAM0_CFG_ECCDD (0x00400000)
128 #define SDRAM0_CFG_EMDULR (0x00200000)
129 #define SDRAM0_STATUS (0x24)
130 #define SDRAM0_STAT_MRSCMP (0x80000000)
131 #define SDRAM0_STAT_SRSSTATUS (0x40000000)
132 #define SDRAM0_RTR (0x30)
133 #define SDRAM0_RTR_IV (0x3ff10000)
134 #define SDRAM0_PMIT (0x34)
135 #define SDRAM0_PMIT_CNT (0xf1000000)
136 #define SDRAM0_BnCR(n) (0x40 + (4 * (n)))
137 #define SDRAM0_B0CR (0x40)
138 #define SDRAM0_B1CR (0x44)
139 #define SDRAM0_B2CR (0x48)
140 #define SDRAM0_B3CR (0x4c)
141 #define SDRAM0_BnCR_BA (0xffc00000)
142 #define SDRAM0_BnCR_SZ (0x000e0000)
143 #define SDRAM0_BnCR_AM (0x0000e000)
144 #define SDRAM0_BnCR_BE (0x00000001)
145 #define SDRAM0_TR (0x80)
146 #define SDRAM0_TR_CASL (0x01800000)
147 #define SDRAM0_TR_PTA (0x000c0000)
148 #define SDRAM0_TR_CTP (0x00030000)
149 #define SDRAM0_TR_LDF (0x0000c000)
150 #define SDRAM0_TR_RFTA (0x000001c0)
151 #define SDRAM0_TR_RCD (0x00000003)
152 #define SDRAM0_ECCCFG (0x94)
153 #define SDRAM0_ECCCFG_CEn(n) (0x00800000 >> (n))
154 #define SDRAM0_ECCESR (0x98)
155 #define SDRAM0_ECCESR_EWBLnCE (0xf0000000)
156 #define SDRAM0_ECCESR_OWBLnCE (0x0f000000)
157 #define SDRAM0_ECCESR_CBE (0x00c00000)
158 #define SDRAM0_ECCESR_CE (0x00200000)
159 #define SDRAM0_ECCESR_UE (0x00100000)
160 #define SDRAM0_ECCESR_BKnE(n) (0x00008000 >> (n))
161 #define SDRAM0_ECCESR_CBEn(n) (0x00800000 >> (n))
162 #define SDRAM0_ECCESR_BLnCE(n) (0x80000000 >> (n))
165 /*****************************************************************************/
166 /*
167 * External Bus Controller Registers (0x012-0x013)
168 *
169 * [DCRs]
170 * DCR_EBC0_CFGADDR Read/Write 0x012
171 * EBC Address Register
172 * DCR_EBC0_CFGDATA Read/Write 0x013
173 * EBC Data Register
174 *
175 * [Indirectly accessed EBC Configuration and Status Registers]
176 * EBC0_BnCR Read/Write 0x00-0x07
177 * Peripheral Bank Configuration Registers (n = 0-7)
178 * 0:11 BAS Base Address Select (n = 0-7)
179 * 12:14 BS Bank Size
180 * 15:16 BU Bank Usage
181 * 17:18 BW Bus Width
182 * 19:31 Reserved
183 * EBC0_BnAP Read/Write 0x10-0x17
184 * Peripheral Bank Access Parameters (n = 0-7)
185 * 0 BME Burst Mode Enable
186 * 1:8 TWT Transfer Wait
187 * 1:5 FWT First Wait
188 * 6:8 BWT Burst Wait
189 * 9:11 Reserved
190 * 12:13 CSN Chip Select On Timing
191 * 14:15 OEN Output Enable On Timing
192 * 16:17 WBN Write Byte Enable On Timing
193 * 18:19 WBF Write Byte Enable Off Timing
194 * 20:22 TH Transfer Hold
195 * 23 RE Ready Enable
196 * 24 SOR Sample on Ready
197 * 25 BEM Byte Enable Mode
198 * 26 PEN Parity Enable
199 * 27:31 Reserved
200 * EBC0_BEAR Read 0x20
201 * Peripheral Bus Error Address Regester
202 * 0:31 Address of Bus Error (asynchronous)
203 * EBC0_BESR0 Read/Write 0x21
204 * Peripheral Bus Error Status Register 0
205 * 0:2 EET0 Error type for master 0
206 * 3 RWS0 Read/Write status for master 0
207 * 4:5 Reserved
208 * 6:8 EET1 Error type for master 1
209 * 9 RWS1 Read/Write status for master 1
210 * 10:11 Reserved
211 * 12:14 EET2 Error type for master 2
212 * 15 RWS2 Read/Write status for master 2
213 * 16:17 Reserved
214 * 18:20 EET3 Error type for master 3
215 * 21 RWS3 Read/Write status for master 3
216 * 22 FL3 Field lock for master 3
217 * 23 AL3 EBC0_BEAR address lock for master 3
218 * 24:31 Reserved
219 * EBC0_BESR1 Read/Write 0x22
220 * Peripheral Bus Error Status Register 1
221 * 0:2 EET4 Error type for master 4
222 * 3 RWS4 Read/Write status for master 4
223 * 4 FL4 Field lock for master 4
224 * 5 AL4 EBC0_BEAR address lock for master 4
225 * 6:8 EET5 Error type for master 5
226 * 9 RWS5 Read/Write status for master 5
227 * 10 FL5 Field lock for master 5
228 * 11 AL5 EBC0_BEAR address lock for master 5
229 * 12:31 Reserved
230 * EBC0_CFG Read/Write 0x23
231 * EBC Configuration Register
232 * 0 EBTC External Bus Three-State Control
233 * 1 PTD Device-Paced Time-out Disable
234 * 2:4 RTC Ready Timeout Count
235 * 5:6 EMPL External Master Priority Low
236 * 7:8 EMPH External Master Priority High
237 * 9 CSTC Chip Select Three-state Control
238 * 10:11 BPF Burst Prefetch
239 * 12:13 EMS External Master Size
240 * 14 PME Power Management Enable
241 * 15:19 PMT Power Management Timer
242 * 20:31 Reserved
243 */
244 #define DCR_EBC0_CFGADDR (0x012)
245 #define DCR_EBC0_CFGDATA (0x013)
247 #define EBC0_BnCR(n) (0x00 + (n))
248 #define EBC0_BnCR_BAS (0xfff00000)
249 #define EBC0_BnCR_BS (0x000e0000)
250 #define EBC0_BnCR_BU (0x00018000)
251 #define EBC0_BnCR_BW (0x00006000)
252 #define EBC0_BnAP(n) (0x10 + (n))
253 #define EBC0_BnAP_BME (0x80000000)
254 #define EBC0_BnAP_TWT (0x7f800000)
255 #define EBC0_BnAP_FWT (0x7c000000)
256 #define EBC0_BnAP_BWT (0x03800000)
257 #define EBC0_BnAP_CSN (0x000c0000)
258 #define EBC0_BnAP_OEN (0x00030000)
259 #define EBC0_BnAP_WBN (0x0000c000)
260 #define EBC0_BnAP_WBF (0x00003000)
261 #define EBC0_BnAP_TH (0x00000e00)
262 #define EBC0_BnAP_RE (0x00000100)
263 #define EBC0_BnAP_SOR (0x00000080)
264 #define EBC0_BnAP_BEM (0x00000040)
265 #define EBC0_BnAP_PEN (0x00000020)
266 #define EBC0_BEAR (0x20)
267 #define EBC0_BESR0 (0x21)
268 #define EBC0_BESR0_EET0 (0xe0000000)
269 #define EBC0_BESR0_RWS0 (0x10000000)
270 #define EBC0_BESR0_EET1 (0x03800000)
271 #define EBC0_BESR0_RWS1 (0x00400000)
272 #define EBC0_BESR0_EET2 (0x000e0000)
273 #define EBC0_BESR0_RWS2 (0x00010000)
274 #define EBC0_BESR0_EET3 (0x00003800)
275 #define EBC0_BESR0_RWS3 (0x00000400)
276 #define EBC0_BESR0_FL3 (0x00000200)
277 #define EBC0_BESR0_AL3 (0x00000100)
278 #define EBC0_BESR1 (0x22)
279 #define EBC0_BESR0_EET4 (0xe0000000)
280 #define EBC0_BESR0_RWS4 (0x10000000)
281 #define EBC0_BESR0_FL4 (0x08000000)
282 #define EBC0_BESR0_AL4 (0x04000000)
283 #define EBC0_BESR0_EET5 (0x03800000)
284 #define EBC0_BESR0_RWS5 (0x00400000)
285 #define EBC0_BESR0_FL5 (0x00200000)
286 #define EBC0_BESR0_AL5 (0x00100000)
287 #define EBC0_CFG (0x23)
288 #define EBC0_CFG_EBTC (0x80000000)
289 #define EBC0_CFG_PTD (0x40000000)
290 #define EBC0_CFG_RTC (0x38000000)
291 #define EBC0_CFG_EMPL (0x06000000)
292 #define EBC0_CFG_EMPH (0x01800000)
293 #define EBC0_CFG_CSTC (0x00400000)
294 #define EBC0_CFG_BPF (0x00300000)
295 #define EBC0_CFG_EMS (0x000c0000)
296 #define EBC0_CFG_PME (0x00020000)
297 #define EBC0_CFG_PMT (0x0001f000)
300 /*****************************************************************************/
301 /*
302 * Decompression Controller Registers (0x014-0x015)
303 *
304 * [DCRs]
305 * DCR_DCP0_CFGADDR Read/Write 0x014
306 * Decompression Controller Address Register
307 * DCR_DCP0_CFGDATA Read/Write 0x015
308 * Decompression Controller Data Register
309 *
310 * [Offsets for Decompression Controller Registers]
311 * DCP0_ITORn Read/Write 0x00-0x03
312 * Index Table Origin Register 0-3 (n = 0-3)
313 * 0:20 Reserved
314 * 21:31 ITO Index Table Origin
315 * DCP0_ADDR{0,1} Read/Write 0x04-0x05
316 * Address Decode Definition Register 0-1
317 * 0:9 DRBA Decode Region Base Address
318 * 10:11 Reserved
319 * 12:15 DRS Decode Region Size
320 * 16:30 Reserved
321 * 31 DREN Enable Decode Region
322 * DCP0_CFG Read/Write 0x40
323 * Decompression Controller Configuration Register
324 * 0:17 Reserved
325 * 18:27 SLDY Sleep Delay
326 * 28 SLEN Sleep Enable
327 * 29 CDB Clear Decompression Buffer
328 * 30 Reserved
329 * 31 IKB Enable Decompression
330 * DCP0_ID Read 0x41
331 * Decompression Controller ID Register
332 * 0:31 Decompression Controller ID
333 * DCP0_VER Read 0x42
334 * Decompression Controller Version Register
335 * 0:31 Decompression Controller Version
336 * DCP0_PLBBEAR Read 0x50
337 * Bus Error Address Register (PLB)
338 * 0:31 Address of PLB Error
339 * DCP0_MEMBEAR Read 0x51
340 * Bus Error Address Register (EBC/SDRAM)
341 * 0:31 Address of SDRAM or EBC Error
342 * DCP0_ESR Read/Clear 0x52
343 * Bus Error Address Register 0 (Masters 0-3)
344 * 0:2 DET0 Decompression Error Type for Master 0
345 * 3 RW0 Read/Write Status for Master 0
346 * 4 FL0 DCP0_ESR Field Lock for Master 0
347 * 5 AL0 DCP0_MEMBEAR/DCP0_PLBBEAR Address Lock for Master 0
348 * 6:8 DET1 Decompression Error Type for Master 1
349 * 9 RW1 Read/Write Status for Master 1
350 * 10 FL1 DCP0_ESR Field Lock for Master 1
351 * 11 AL1 DCP0_MEMBEAR/DCP0_PLBBEAR Address Lock for Master 1
352 * 12:14 DET2 Decompression Error Type for Master 2
353 * 15 RW2 Read/Write Status for Master 2
354 * 16 FL2 DCP0_ESR Field Lock for Master 2
355 * 17 AL2 DCP0_MEMBEAR/DCP0_PLBBEAR Address Lock for Master 2
356 * 18:20 DET3 Decompression Error Type for Master 3
357 * 21 RW3 Read/Write Status for Master 3
358 * 22 FL3 DCP0_ESR Field Lock for Master 3
359 * 23 AL3 DCP0_MEMBEAR/DCP0_PLBBEAR Address Lock for Master 3
360 * 24:31 Reserved
361 * DCP0_RAM{000-3FF} Read/Write 0x400-7ff
362 * Decompression Decode Table Entries (SRAM)
363 * 0x400-0x5ff Low 16-bit decode table
364 * 0x600-0x7ff High 16-bit decode table
365 * 0:15 Reserved
366 * 16:31 DTE Decode Table Entry
367 */
368 #if defined(PPC_IBM405_HAVE_CODEPACK)
369 # define DCR_DCP0_CFGADDR (0x014)
370 # define DCR_DCP0_CFGDATA (0x015)
372 # define DCP0_ITORn(n) (0x00 + (n))
373 # define DCP0_ITORn_ITO (0x00000fff)
374 # define DCP0_ADDR0 (0x04)
375 # define DCP0_ADDR1 (0x05)
376 # define DCP0_ADDR_DRBA (0xffc00000)
377 # define DCP0_ADDR_DRS (0x000f0000)
378 # define DCP0_ADDR_DREN (0x00000001)
379 # define DCP0_CFG (0x40)
380 # define DCP0_CFG_SLDY (0x00003ff0)
381 # define DCP0_CFG_SLEN (0x00000008)
382 # define DCP0_CFG_CDB (0x00000004)
383 # define DCP0_CFG_IKB (0x00000001)
384 # define DCP0_ID (0x41)
385 # define DCP0_VER (0x42)
386 # define DCP0_PLBBEAR (0x50)
387 # define DCP0_MEMBEAR (0x51)
388 # define DCP0_ESR (0x52)
389 # define DCP0_ESR_DET0 (0xe0000000)
390 # define DCP0_ESR_RW0 (0x10000000)
391 # define DCP0_ESR_FL0 (0x08000000)
392 # define DCP0_ESR_AL0 (0x04000000)
393 # define DCP0_ESR_DET1 (0x03800000)
394 # define DCP0_ESR_RW1 (0x00400000)
395 # define DCP0_ESR_FL1 (0x00200000)
396 # define DCP0_ESR_AL1 (0x00100000)
397 # define DCP0_ESR_DET2 (0x000e0000)
398 # define DCP0_ESR_RW2 (0x00010000)
399 # define DCP0_ESR_FL2 (0x00008000)
400 # define DCP0_ESR_AL2 (0x00004000)
401 # define DCP0_ESR_DET3 (0x00003800)
402 # define DCP0_ESR_RW3 (0x00000400)
403 # define DCP0_ESR_FL3 (0x00000200)
404 # define DCP0_ESR_AL3 (0x00000100)
405 # define DCP0_RAM(n) (0x400 + n)
406 # define DCP0_RAM_LOW(n) (0x400 + n)
407 # define DCP0_RAM_HIGH(n) (0x600 + n)
408 # define DCP0_RAM_END (0x7ff)
409 # define DCP0_RAM_DTE (0x0000ffff)
413 /*****************************************************************************/
414 /*
415 * On-Chip Memory (OCM) Controller Registers (0x018-0x01f)
416 *
417 * DCR_OCM0_ISARC Read/Write 0x018
418 * OCM Instruction-Side Address Range Compare Register
419 * 0:5 ISAR Instruction-Side OCM address range
420 * 6:31 Reserved
421 * DCR_OCM0_ISCNTL Read/Write 0x019
422 * OCM Instruction-Side Control Register
423 * 0 ISEN Instruction-Side OCM Enable
424 * 1 ISTCM Instruction-Side Two-Cycle Mode
425 * 2:31 Reserved
426 * DCR_OCM0_DSARC Read/Write 0x01a
427 * OCM Data-Side Address Range Compare Register
428 * 0:5 DSAR Data-Side OCM address range
429 * 6:31 Reserved
430 * DCR_OCM0_DSCNTL Read/Write 0x01b
431 * OCM Data-Side Control Register
432 * 0 DSEN Data-Side OCM Enable
433 * 1 DOF This field shoud remain set to 1
434 * 2:31 Reserved
435 */
436 #if defined(PPC_IBM405_HAVE_OCM0)
437 # define DCR_OCM0_ISARC (0x018)
438 # define OCM0_ISARC_ISAR (0xfc000000)
439 # define DCR_OCM0_ISCNTL (0x019)
440 # define OCM0_ISCNTL_ISEN (0x80000000)
441 # define OCM0_ISCNTL_ISTCM (0x40000000)
442 # define DCR_OCM0_DSARC (0x01a)
443 # define OCM0_DSARC_DSAR (0xfc000000)
444 # define DCR_OCM0_DSCNTL (0x01b)
445 # define OCM0_DSCNTL_DSEN (0x80000000)
446 # define OCM0_DSCNTL_DOF (0x40000000)
450 /*****************************************************************************/
451 /*
452 * Processor Local Bus (PLB) Registers (0x080-0x08f)
453 *
454 * DCR_PLB0_BESR Read/Clear 0x084
455 * PLB Error Status Register
456 * 0 PTE0 Master 0 PLB Timeout Error Status
457 * (Master 0 is the processor core ICU)
458 * 1 R/W0 Master 0 Read/Write Status
459 * 2:3 Reserved
460 * 4 PTE1 Master 1 PLB Timeout Error Status
461 * (Master 1 is the processor core DCU)
462 * 5 R/W1 Master 1 Read/Write Status
463 * 6:7 Reserved
464 * 8 PTE2 Master 2 PLB Timeout Error Status
465 * (Master 2 is the external master)
466 * 9 R/W2 Master 2 Read/Write Status
467 * 10:11 Reserved
468 * 12 PTE3 Master 3 PLB Timeout Error Status (Master 3 is PCI)
469 * 13 R/W3 Master 3 Read/Write Status
470 * 14 FLK3 Master 3 PLB0_BESR Field Lock
471 * 15 ALK3 Master 3 PLB0_BESR Address Lock
472 * 16 PTE4 Master 4 PLB Timeout Error Status (Master 4 is MAL)
473 * 17 R/W4 Master 4 Read/Write Status
474 * 18 FLK4 Master 4 PLB0_BESR Field Lock
475 * 19 ALK4 Master 4 PLB0_BESR Address Lock
476 * 20 PTE5 Master 5 PLB Timeout Error Status (Master 5 is DMA)
477 * 21 R/W5 Master 5 Read/Write Status
478 * 22:31 Reserved
479 * DCR_PLB0_BEAR Read 0x086
480 * PLB Error Address Register
481 * 0:31 Address of bus timeout error
482 * DCR_PLB0_ACR Read/Write 0x087
483 * PLB Arbiter Control Register
484 * 0 PPM PLB Priority Mode
485 * 1:3 PPO PLB Priority Order
486 * 4 HBU High Bus Utilization
487 * 5:31 Reserved
488 */
490 #define DCR_PLB0_BESR (0x084)
491 #define PLB0_BESR_PTE(n) (0x80000000 >> (n * 4))
492 #define PLB0_BESR_RW(n) (0x40000000 >> (n * 4))
493 #define PLB0_BESR_FLK(n) (0x20000000 >> (n * 4))
494 #define PLB0_BESR_ALK(n) (0x10000000 >> (n * 4))
495 #define DCR_PLB0_BEAR (0x086)
496 #define DCR_PLB0_ACR (0x087)
497 #define PLB0_ACR_PPM (0x80000000)
498 #define PLB0_ACR_PPO (0x70000000)
499 #define PLB0_ACR_HBU (0x08000000)
502 /*****************************************************************************/
503 /*
504 * Peformance Counters (0x090-0x091)
505 */
506 #if defined(PPC_IBM405_HAVE_PERFCOUNT)
510 /*****************************************************************************/
511 /*
512 * On-chip Peripheral Bus (OPB) Bridge Out Registers (0x0a0-0x0a7)
513 * (PLB to OPB Bridge Registers)
514 *
515 *
516 * DCR_POB0_BESR0 Read/Clear 0x0a0
517 * Bridge Error Status Register 0 (Master IDs 0, 1, 2, 3)
518 * 0:1 PTE0 PLB Timeout Error Status Master 0
519 * (Master 0 is the processor core ICU)
520 * 2 R/W0 Read/Write Status Master 0
521 * 3:4 Reserved
522 * 5:6 PTE1 PLB Timeout Error Status Master 1
523 * (Master 1 is the processor core DCU)
524 * 7 R/W1 Read/Write Status Master 1
525 * 8:9 Reserved
526 * 10:11 PTE2 PLB Timeout Error Status Master 2
527 * (Master 2 is the external master)
528 * 12 R/W2 Read/Write Status Master 2
529 * 13:14 Reserved
530 * 15:16 PTE3 PLB Timeout Error Status Master 3 (Master 3 is PCI)
531 * 17 R/W3 Read/Write Status Master 3
532 * 18 FLK3 POB0_BESR0 Field Lock Master 3
533 * 19 ALK3 POB0_BEAR Address Lock Master 3
534 * 20:31 Reserved
535 * DCR_POB0_BEAR Read 0x0a2
536 * Bridge Error Address Register
537 * 0:31 BEA Address of bus error
538 * DCR_POB0_BESR1 Read/Clear 0x0a4
539 * Bridge Error Status Register 1 (Master IDs 0, 1, 2, 3)
540 * 0:1 PTE4 PLB Timeout Error Status Master 4 (Master 4 is MAL)
541 * 2 R/W4 Read/Write Status Master 4
542 * 3 FLK4 POB0_BESR0 Field Lock Master 4
543 * 4 ALK4 POB0_BEAR Address Lock Master 4
544 * 5:6 PTE5 PLB Timeout Error Status Master 5 (Master 5 is DMA)
545 * 7 R/W5 Read/Write Status Master 5
546 * 831 Reserved
547 *
548 */
549 #define DCR_POB0_BESR0 (0x0a0)
550 #define POB0_BESR0_PTE0 (0xc0000000)
551 #define POB0_BESR0_RW0 (0x20000000)
552 #define POB0_BESR0_PTE1 (0x06000000)
553 #define POB0_BESR0_RW1 (0x01000000)
554 #define POB0_BESR0_PTE2 (0x00300000)
555 #define POB0_BESR0_RW2 (0x00080000)
556 #define POB0_BESR0_PTE3 (0x00018000)
557 #define POB0_BESR0_RW3 (0x00004000)
558 #define POB0_BESR0_FLK3 (0x00002000)
559 #define POB0_BESR0_ALK3 (0x00001000)
560 #define DCR_POB0_BEAR (0x0a2)
561 #define DCR_POB0_BESR1 (0x0a4)
562 #define POB0_BESR1_PTE4 (0xc0000000)
563 #define POB0_BESR1_RW4 (0x20000000)
564 #define POB0_BESR1_FLK4 (0x10000000)
565 #define POB0_BESR1_ALK4 (0x08000000)
566 #define POB0_BESR1_PTE5 (0x06000000)
567 #define POB0_BESR1_RW5 (0x01000000)
570 /*****************************************************************************/
571 /*
572 * Electronic Chip ID (ECID) Registers (0x0a8-0x0a9)
573 *
574 * DCR_CPC0_ECID0 Read 0x0a8
575 * Electronic Chip ID Register 0
576 * 0:31 ECID Electronic Chip ID
577 * DCR_CPC0_ECID1 Read 0x0a9
578 * Electronic Chip ID Register 1
579 * 0:31 ECID Electronic Chip ID
580 */
581 #if defined(PPC_IBM405_HAVE_ECID)
582 # define DCR_CPC0_ECID0 (0x0a8)
583 # define DCR_CPC0_ECID1 (0x0a9)
587 /*****************************************************************************/
588 /*
589 * Chip Edge Conditioning Register
590 *
591 * DCR_CPC0_ECR Read/Write 0x0aa
592 * Edge Conditioner Register
593 * 0:2 Rx Ethernet RX clock edge conditioning
594 * 3:7 Reserved
595 * 8:10 Tx Ethernet TX clock edge conditioning
596 * 11:15 Reserved
597 * 16:18 UIC UIC edge triggered external interrupts edge conditioning
598 * 19:31 Reserved
599 */
600 #if defined(PPC_IBM405_HAVE_CEC)
601 # define DCR_CPC0_ECR (0x0aa)
602 # define CPC0_ECR_RX (0xe0000000)
603 # define CPC0_ECR_TX (0x00e00000)
604 # define CPC0_ECR_UIC (0x0000e000)
608 /*****************************************************************************/
609 /*
610 * Clock, Control, and Reset Registers
611 *
612 * DCR_CPC0_PLLMR Read 0x0b0
613 * PLL Mode Register
614 * 0:2 FWDV Forward Divisor
615 * FMDVA Forward Divisor A
616 * 3:6 FBDV Feedback Divisor
617 * 7:12 TUN Tune[5:0] Field
618 * 13:14 CBDV CPU:PLB Frequency Divisor
619 * 15:16 OPDV OPB:PLB Frequency Divisor
620 * 17:18 PPDV PCI:PLB Frequency Divisor
621 * 19:20 EPDV External Bus:PLB Frequency Divisor
622 * 21:24 UTUN Upper PLL Tune[9:6]
623 * 25 BYPS PLL Bypass Mode
624 * 26:28 Reserved
625 * 29:31 FMDVB Forward Divisor B
626 * DCR_CPC0_CR0 Read/Write 0x0b1
627 * Chip Control Register 0
628 * 0:3 Reserved
629 * 4 TRE CPU Trace Enable
630 * 5 G10E GPIO 10 Enable
631 * 6 G11E GPIO 11 Enable
632 * 7 G12E GPIO 12 Enable
633 * 8 G13E GPIO 13 Enable
634 * 9 G14E GPIO 14 Enable
635 * 10 G15E GPIO 15 Enable
636 * 11 G16E GPIO 16 Enable
637 * 12 G17E GPIO 17 Enable
638 * 13 G18E GPIO 18 Enable
639 * 14 G19E GPIO 19 Enable
640 * 15 G20E GPIO 20 Enable
641 * 16 G21E GPIO 21 Enable
642 * 17 G22E GPIO 22 Enable
643 * 18 G23E GPIO 23 Enable
644 * 19 DCS DSR/CTS select for UART1
645 * 20 RDS RTS/DTR select for UART1
646 * 21 DTE DMA Transmit Enable for UART0
647 * 22 DRE DMA Receive Enable for UART0
648 * 23 DAEC DMA Allow Enable Clear for UART0
649 * 24 U0EC Select External Clock for UART0
650 * 25 U1EC Select External Clock for UART1
651 * 26:30 UDIC UART Internal Clock Divisor
652 * 31 Reserved
653 * DCR_CPC0_CR1 Read/Write 0x0b2
654 * Chip Control Register 1
655 * 0:7 Reserved
656 * 8 CETE CPU External Timer Enable
657 * 9:16 Reserved
658 * 17 PCIPW PCI Interrupt/Peripheral Write Enable
659 * 18:20 Reserved
660 * 21:24 PARG Peripheral Address Bus Receiver Gating
661 * 25:26 PDRG Peripheral Data Bus Receiver Gating
662 * 27 PCIRG PCI Interface Receiver Gating
663 * 28 SDRG SDRAM Interface Receiver Gating
664 * 29 ENRG Ethernet Interface Receiver Gating
665 * 30 U0RG UART 0 Interface Receiver Gating
666 * 31 U1RG UART 1 Interface Receiver Gating
667 * DCR_CPC0_PSR Read 0x0b4
668 * Chip Pin Strapping Register
669 * 0:1 PFWD PLL Forward Divisor
670 * 2:3 PFBD PLL Feedback Divisor
671 * 4:6 PT PLL Tuning
672 * 7:8 PDC PLB Divisor from CPU
673 * 9:10 ODP OPB Divisor from PLB
674 * 11:12 PDP PCI Divisor from PLB
675 * 13:14 EBDP External Bus Divisor from PLB
676 * 15:16 RW ROM Width
677 * 17 RL ROM Location
678 * 18 Reserved
679 * 19 PAME PCI Asynchronous Mode Enable
680 * 20 ESME PerClk synch mode when in PLL
681 * 21 PAE PCI Arbiter Enable
682 * 22 PFWDA Forward A Divisor Bit 2
683 * 23 PFWDB Forward B Divisor Bit 2
684 * 24 PFBD2 Feedback Divisor Bit 2
685 * 25 PFBD3 Feedback Divisor Bit 3
686 * 26 NEWE New Mode Enable
687 * 27 FCD Flip Circuit Disable
688 * 28:31 Reserved
689 * DCR_CPC0_JTAGID Read 0x0b5
690 * JTAG ID Register
691 * 0:3 VERS Version
692 * 4:7 LOC Developer Location
693 * 8:19 PART Part Number
694 * 20:31 MANF Manufacturer Identifier
695 * DCR_CPC0_EIRR Read/Write 0x0b6
696 * External Interrupt Routing Register
697 * 0:4 IRQ19 Selection from GPIO[1:24] alternate output
698 * 5:9 IRQ20 Selection from GPIO[1:24] alternate output
699 * 10:14 IRQ21 Selection from GPIO[1:24] alternate output
700 * 15:19 IRQ22 Selection from GPIO[1:24] alternate output
701 * 20:24 IRQ23 Selection from GPIO[1:24] alternate output
702 * 25:29 IRQ24 Selection from GPIO[1:24] alternate output
703 * 30 Reserved
704 * 31 DAC PCI Dual Address Cycle
705 *
706 */
707 #define DCR_CPC0_PLLMR (0x0b0)
708 #define CPC0_PLLMR_FMDV (0xe0000000)
709 #define CPC0_PLLMR_FMDVA (0xe0000000)
710 #define CPC0_PLLMR_FBDV (0x1c000000)
711 #define CPC0_PLLMR_TUN (0x03f00000)
712 #define CPC0_PLLMR_CBDV (0x000c0000)
713 #define CPC0_PLLMR_OPDV (0x00030000)
714 #define CPC0_PLLMR_PPDV (0x0000c000)
715 #define CPC0_PLLMR_EPDV (0x00003000)
716 #define CPC0_PLLMR_UTUN (0x00000780)
717 #define CPC0_PLLMR_BYPS (0x00000040)
718 #define CPC0_PLLMR_FMDVB (0x00000007)
719 #define DCR_CPC0_CR0 (0x0b1)
720 #define CPC0_CR0_TRE (0x08000000)
721 #define CPC0_CR0_G10E (0x04000000)
722 #define CPC0_CR0_G11E (0x02000000)
723 #define CPC0_CR0_G12E (0x01000000)
724 #define CPC0_CR0_G13E (0x00800000)
725 #define CPC0_CR0_G14E (0x00400000)
726 #define CPC0_CR0_G15E (0x00200000)
727 #define CPC0_CR0_G16E (0x00100000)
728 #define CPC0_CR0_G17E (0x00080000)
729 #define CPC0_CR0_G18E (0x00040000)
730 #define CPC0_CR0_G19E (0x00020000)
731 #define CPC0_CR0_G20E (0x00010000)
732 #define CPC0_CR0_G21E (0x00008000)
733 #define CPC0_CR0_G22E (0x00004000)
734 #define CPC0_CR0_G23E (0x00002000)
735 #define CPC0_CR0_DCS (0x00001000)
736 #define CPC0_CR0_RDS (0x00000800)
737 #define CPC0_CR0_DTE (0x00000400)
738 #define CPC0_CR0_DRE (0x00000200)
739 #define CPC0_CR0_DAEC (0x00000100)
740 #define CPC0_CR0_U0EC (0x00000080)
741 #define CPC0_CR0_U1EC (0x00000040)
742 #define CPC0_CR0_UDIV (0x0000003e)
743 #define DCR_CPC0_CR1 (0x0b2)
744 #define CPC0_CR1_CETE (0x00800000)
745 #define CPC0_CR1_PCIPW (0x00008000)
746 #define CPC0_CR1_PARG (0x00000780)
747 #define CPC0_CR1_PDRG (0x00000060)
748 #define CPC0_CR1_PCIRG (0x00000010)
749 #define CPC0_CR1_SDRG (0x00000008)
750 #define CPC0_CR1_ENRG (0x00000004)
751 #define CPC0_CR1_U0RG (0x00000002)
752 #define CPC0_CR1_U1RG (0x00000001)
753 #define DCR_CPC0_PSR (0x0b4)
754 #define CPC0_PSR_PFWD (0xc0000000)
755 #define CPC0_PSR_PFBD (0x30000000)
756 #define CPC0_PSR_PT (0x0e000000)
757 #define CPC0_PSR_PDC (0x01800000)
758 #define CPC0_PSR_ODP (0x00600000)
759 #define CPC0_PSR_PDP (0x00180000)
760 #define CPC0_PSR_EBDP (0x00060000)
761 #define CPC0_PSR_RW (0x00018000)
762 #define CPC0_PSR_RL (0x00004000)
763 #define CPC0_PSR_PAME (0x00001000)
764 #define CPC0_PSR_ESME (0x00000800)
765 #define CPC0_PSR_PAE (0x00000400)
766 #define CPC0_PSR_PFWDA (0x00000200)
767 #define CPC0_PSR_PFWDB (0x00000100)
768 #define CPC0_PSR_PFBD2 (0x00000080)
769 #define CPC0_PSR_PFBD3 (0x00000040)
770 #define CPC0_PSR_NEWE (0x00000020)
771 #define CPC0_PSR_FCD (0x00000010)
772 #define DCR_CPC0_JTAGID (0x0b5)
773 #define CPC0_JTAGID_VERS (0xf0000000)
774 #define CPC0_JTAGID_LOC (0x0f000000)
775 #define CPC0_JTAGID_PART (0x00fff000)
776 #define CPC0_JTAGID_MANF (0x00000fff)
777 #define DCR_CPC0_EIRR (0x0b6)
778 #define CPC0_EIRR_IRQ19 (0xf8000000)
779 #define CPC0_EIRR_IRQ20 (0x07c00000)
780 #define CPC0_EIRR_IRQ21 (0x003e0000)
781 #define CPC0_EIRR_IRQ22 (0x0001f000)
782 #define CPC0_EIRR_IRQ23 (0x00000f80)
783 #define CPC0_EIRR_IRQ24 (0x0000007c)
784 #define CPC0_EIRR_DAC (0x00000001)
787 /*****************************************************************************/
788 /*
789 * Power Management Registers
790 *
791 * CPC0_SR Read 0x0b8
792 * CPM Status Register
793 * CPC0_ER Read/Write 0x0b9
794 * CPM Enable Register
795 * CPC0_FR Read/Write 0x0ba
796 * CPM Force Register
797 *
798 * CPC0_{SR,ER,FR}
799 * All above CPM Registers
800 * 0 IIC IIC Interface
801 * 1 PCI PCI Bridge
802 * 2 CPU Processor Core
803 * 3 DMA DMA Controller
804 * 4 BRG PLB to OPB Bridge
805 * 5 DCP CodePack
806 * 6 EBC ROM/SRAM Peripheral Controller
807 * 7 SDRAM SDRAM Memory Controller
808 * 8 PLB PLB Bus Arbiter
809 * 9 CPIO General Purpose Interrupt Controller
810 * 10 UART0 Serial Port 0
811 * 11 UART1 Serial Port 1
812 * 12 UIC Univeral Interrupt Controller
813 * 13 CPU_TMRCLK CPU Timers
814 * 14 EMAC_MM Ethernet MM Unit
815 * 15 EMAC_RM Ethernet RM Unit
816 * 16 EMAC_TM Ethernet TM Unit
817 * 17:31 Reserved
818 */
819 #define DCR_CPC0_SR (0x0b8)
820 #define DCR_CPC0_ER (0x0b9)
821 #define DCR_CPC0_FR (0x0ba)
822 #define CPC0_CPMR_IIC (0x80000000)
823 #define CPC0_CPMR_PCI (0x40000000)
824 #define CPC0_CPMR_CPU (0x20000000)
825 #define CPC0_CPMR_DMA (0x10000000)
826 #define CPC0_CPMR_BRG (0x08000000)
827 #define CPC0_CPMR_DCP (0x04000000)
828 #define CPC0_CPMR_EBC (0x02000000)
829 #define CPC0_CPMR_SDRAM (0x01000000)
830 #define CPC0_CPMR_PLB (0x00800000)
831 #define CPC0_CPMR_GPIO (0x00400000)
832 #define CPC0_CPMR_UART0 (0x00200000)
833 #define CPC0_CPMR_UART1 (0x00100000)
834 #define CPC0_CPMR_UIC (0x00080000)
835 #define CPC0_CPMR_CPU_TMRCLK (0x00040000)
836 #define CPC0_CPMR_EMAC_MM (0x00020000)
837 #define CPC0_CPMR_EMAC_RM (0x00010000)
838 #define CPC0_CPMR_EMAC_TM (0x00008000)
841 /*****************************************************************************/
842 /*
843 * Universal Interrupt Controller 0 Registers
844 *
845 * DCR_UIC0_SR Read/Clear 0x0c0
846 * UIC Status Register
847 * DCR_UIC0_ER Read/Write 0x0c2
848 * UIC Enable Register
849 * DCR_UIC0_CR Read/Write 0x0c3
850 * UIC Critical Register
851 * DCR_UIC0_PR Read/Write 0x0c4
852 * UIC Polarity Register
853 * DCR_UIC0_TR Read/Write 0x0c5
854 * UIC Trigger Register
855 * DCR_UIC0_MSR Read 0x0c6
856 * UIC Masked Status Register
857 *
858 * DCR_UIC0_{SR,ER,CR,PR,TR,MSR}
859 * 0 U0I UART0 Interrupt
860 * 1 U1I UART1 Interrupt
861 * 2 IIC IIC Interrupt
862 * 3 EMI External Master Interrupt
863 * 4 PCII PCI Interrupt
864 * 5 D0I DMA Channel 0 Interrupt
865 * 6 D1I DMA Channel 1 Interrupt
866 * 7 D2I DMA Channel 2 Interrupt
867 * 8 D3I DMA Channel 3 Interrupt
868 * 9 EWI Ethernet Wake-up Interrupt
869 * 10 MSI MAL SERR Interrupt
870 * 11 MTEI MAL TX EOB Interrupt
871 * 12 MREI MAL RX EOB Interrupt
872 * 13 MTDI MAL TX DE Interrupt
873 * 14 MRDI MAL RX DE Interrupt
874 * 15 EI Ethernet Interrupt
875 * 16 EPSI External PCI SERR Interrupt
876 * 17 ECI ECC Correctable Error Interrupt
877 * 18 PPMI PCI Power Management Interrupt
878 * 19 EIR7 External IRQ 7 Interrupt
879 * 20 EIR8 External IRQ 8 Interrupt
880 * 21 EIR9 External IRQ 9 Interrupt
881 * 22 EIR10 External IRQ 10 Interrupt
882 * 23 EIR11 External IRQ 11 Interrupt
883 * 24 EIR12 External IRQ 12 Interrupt
884 * 25 EIR0 External IRQ 0 Interrupt
885 * 26 EIR1 External IRQ 1 Interrupt
886 * 27 EIR2 External IRQ 2 Interrupt
887 * 28 EIR3 External IRQ 3 Interrupt
888 * 29 EIR4 External IRQ 4 Interrupt
889 * 30 EIR5 External IRQ 5 Interrupt
890 * 31 EIR6 External IRQ 6 Interrupt
891 *
892 * DCR_UIC0_VR Read 0x0c7
893 * UIC Vector Register
894 * 0:31 VBA Interrupt Vector
895 * DCR_UIC0_VCR Write 0x0c8
896 * UIC Vector Configuration Register
897 * 0:29 VBA Vector Base Address
898 * 30 Reserved
899 * 31 PRO Priority Ordering
900 */
901 #define DCR_UIC0_SR (0x0c0)
902 #define DCR_UIC0_ER (0x0c2)
903 #define DCR_UIC0_CR (0x0c3)
904 #define DCR_UIC0_PR (0x0c4)
905 #define DCR_UIC0_TR (0x0c5)
906 #define DCR_UIC0_MSR (0x0c6)
907 #define UIC0_SR_U0I (0x80000000)
908 #define UIC0_SR_U1I (0x40000000)
909 #define UIC0_SR_IICI (0x20000000)
910 #define UIC0_SR_EMI (0x10000000)
911 #define UIC0_SR_PCII (0x08000000)
912 #define UIC0_SR_D0I (0x04000000)
913 #define UIC0_SR_D1I (0x02000000)
914 #define UIC0_SR_D2I (0x01000000)
915 #define UIC0_SR_D3I (0x00800000)
916 #define UIC0_SR_EWI (0x00400000)
917 #define UIC0_SR_MSI (0x00200000)
918 #define UIC0_SR_MTEI (0x00100000)
919 #define UIC0_SR_MREI (0x00080000)
920 #define UIC0_SR_MTDI (0x00040000)
921 #define UIC0_SR_MRDI (0x00020000)
922 #define UIC0_SR_ENI (0x00010000)
923 #define UIC0_SR_EPSI (0x00008000)
924 #define UIC0_SR_ECI (0x00004000)
925 #define UIC0_SR_PPMI (0x00002000)
926 #define UIC0_SR_EIR0 (0x00000040)
927 #define UIC0_SR_EIR1 (0x00000020)
928 #define UIC0_SR_EIR2 (0x00000010)
929 #define UIC0_SR_EIR3 (0x00000008)
930 #define UIC0_SR_EIR4 (0x00000004)
931 #define UIC0_SR_EIR5 (0x00000002)
932 #define UIC0_SR_EIR6 (0x00000001)
933 #define DCR_UIC0_VR (0x0c7)
934 #define DCR_UIC0_VCR (0x0c8)
935 #define UIC0_VCR_VBA (0xfffffffc)
936 #define UIC0_VCR_PRO (0x00000001)
939 /*****************************************************************************/
940 /*
941 * Universal Interrupt Controller 1 Registers (0x0d0-0x0df)
942 */
943 #if defined(PPC_IBM405_HAVE_UIC1)
947 /*****************************************************************************/
948 /*
949 * Miscellaneous Registers (0x0f0-0x0ff)
950 */
951 #if defined(PPC_IBM405_HAVE_MISC)
955 /*****************************************************************************/
956 /*
957 * DMA Controller Registers
958 *
959 * DCR_DMA0_CRn Read/Write 0x100,0x108.
960 * DMA Channel Control Registers (n = 0-3) 0x110,0x118
961 * 0 CE Channel Enable
962 * 1 CIE Channel Interrupt Enable
963 * 2 TD Transfer Direction
964 * 3 PL Peripheral Location
965 * 4:5 PW Peripheral Width/Memory alignment
966 * 6 DAI Destination Address Increment
967 * 7 SAI Source Address Increment
968 * 8 BEN Buffer Enable
969 * 9:10 TM Transfer mode
970 * 11:12 PSC Peripheral Setup Cycles
971 * 13:18 PWC Peripheral Wait Cycles
972 * 19:21 PHC Peripheral Hold Cycles
973 * 22 ETD End-of-Transfer/Terminal Count (EOTn[TCn]) Pin Dirction
974 * 23 TCE Terminal Count (TC) Enable
975 * 24:25 CP Channel Parity
976 * 26:27 PF Memory Read Prefeth Transfer
977 * 28 PCE Parity Check Enable
978 * 29 DEC Address Decrement
979 * 30:31 Reserved
980 * DCR_DMA0_CTn Read/Write 0x101,0x109.
981 * DMA Count Registers (n = 0-3) 0x111,0x119
982 * 0:15 Reserved
983 * 16:31 NTR Number of transfers remaining
984 * DCR_DMA0_DAn Read/Write 0x102,0x10a,
985 * DMA Source Address Registers (n = 0-3) 0x112,0x11a
986 * 0:31 Destination address for memory-to-memory
987 * and memory-to-peripheral transfers
988 * DCR_DMA0_SAn Read/Write 0x103,0x10b,
989 * DMA Source Address Registers (n = 0-3) 0x113,0x11b
990 * 0:31 Source address for memory-to-memory
991 * and memory-to-peripheral transfers
992 * DCR_DMA0_SGn Read/Write 0x104,0x10c.
993 * DMA Scatter/Gather Descriptor Address Registers 0x114,0x11c
994 * (n = 0-3)
995 * 0:31 Address of next scatter/gather descriptor table
996 * DCR_DMA0_SR Read/Clear 0x120
997 * DMA Status Register
998 * 0:3 CS[0:3] Channel 0-3 Terminal Count Status
999 * 4:7 TS[0:3] Channel 0-3 End of Transfer Status
1000 * 8:11 RI[0:3] Channel 0-3 Error Status
1001 * 12:15 IR[0:3] Internal DMA Request
1002 * 16:19 ER[0:3] External DMA Request
1003 * 20:23 CB[0:3] Channel Busy
1004 * 24:27 SG[0:3] Scatter/Gather Status
1005 * 28:31 Reserved
1006 * DCR_DMA0_SGC Read/Write 0x123
1007 * DMA Scatter/Gather Command Register
1008 * 0:3 SSG[0:3] Start Scatter/Gather for channels 0-3
1009 * 4:15 Reserved
1010 * 16:19 EM[0:3] Enable Mask for channels 0-3
1011 * 20:31 Reserved
1012 * DCR_DMA0_SLP Read/Write 0x125
1013 * DMA Sleep Mode Register
1014 * 0:4 IDU Idle Timer Upper
1015 * 5:9 IDL Idle Timer Lower
1016 * 10 SME Sleep Mode Enable
1017 * 11:31 Reserved
1018 * DCR_DMA0_POL Read/Write 0x126
1019 * DMA Polarity Configuration Register
1020 * 0 R0P DMAReq0 Polarity
1021 * 1 A0P DMAAck0 Polarity
1022 * 2 E0P EOT0[TC0] Polarity
1023 * 3 R1P DMAReq1 Polarity
1024 * 4 A1P DMAAck1 Polarity
1025 * 5 E1P EOT1[TC1] Polarity
1026 * 6 R2P DMAReq2 Polarity
1027 * 7 A2P DMAAck2 Polarity
1028 * 8 E2P EOT2[TC2] Polarity
1029 * 9 R3P DMAReq3 Polarity
1030 * 10 A3P DMAAck3 Polarity
1031 * 11 E3P EOT3[TC3] Polarity
1032 * 12 Reserved
1033 */
1034 /* DMA Channel Control Register 0-3 */
1035 #define DCR_DMA0_CRn(n) (0x100 + (8 * (n)))
1036 #define DMA0_CRn_CE (0x80000000)
1037 #define DMA0_CRn_CIE (0x40000000)
1038 #define DMA0_CRn_TD (0x20000000)
1039 #define DMA0_CRn_PL (0x10000000)
1040 #define DMA0_CRn_PW (0x0c000000)
1041 #define DMA0_CRn_DAI (0x02000000)
1042 #define DMA0_CRn_SAI (0x01000000)
1043 #define DMA0_CRn_BEN (0x00800000)
1044 #define DMA0_CRn_TM (0x00600000)
1045 #define DMA0_CRn_PSC (0x00180000)
1046 #define DMA0_CRn_PWC (0x0007e000)
1047 #define DMA0_CRn_PHC (0x00001c00)
1048 #define DMA0_CRn_ETD (0x00000200)
1049 #define DMA0_CRn_TCE (0x00000100)
1050 #define DMA0_CRn_CP (0x000000c0)
1051 #define DMA0_CRn_PF (0x00000030)
1052 #define DMA0_CRn_PCE (0x00000008)
1053 #define DMA0_CRn_DEC (0x00000004)
1054 #define DCR_DMA0_CTn(n) (0x101 + (8 * (n)))
1055 #define DMA0_CTn_NTR (0x0000ffff)
1056 #define DCR_DMA0_DAn(n) (0x102 + (8 * (n)))
1057 #define DCR_DMA0_SAn(n) (0x103 + (8 * (n)))
1058 #define DCR_DMA0_SGn(n) (0x104 + (8 * (n)))
1059 #define DCR_DMA0_SR (0x120)
1060 #define DMA0_SR_CSn(n) (0x80000000 >> (n))
1061 #define DMA0_SR_TSn(n) (0x08000000 >> (n))
1062 #define DMA0_SR_RIn(n) (0x00800000 >> (n))
1063 #define DMA0_SR_IRn(n) (0x00080000 >> (n))
1064 #define DMA0_SR_ERn(n) (0x00008000 >> (n))
1065 #define DMA0_SR_CBn(n) (0x00000800 >> (n))
1066 #define DMA0_SR_SGn(n) (0x00000080 >> (n))
1067 #define DCR_DMA0_SGC (0x123)
1068 #define DMA0_SGC_SSGn(n) (0x80000000 >> (n))
1069 #define DMA0_SGC_EMn(n) (0x00008000 >> (n))
1070 #define DCR_DMA0_SLP (0x125)
1071 #define DMA0_SLP_IDU (0xf8000000)
1072 #define DMA0_SLP_IDL (0x07c00000)
1073 #define DMA0_SLP_SME (0x00200000)
1074 #define DCR_DMA0_POL (0x126)
1075 #define DMA0_POL_RnP(n) (0x80000000 >> (3 * (n)))
1076 #define DMA0_POL_AnP(n) (0x40000000 >> (3 * (n)))
1077 #define DMA0_POL_EnP(n) (0x20000000 >> (3 * (n)))
1080 /*****************************************************************************/
1081 /*
1082 * Memory Access Layer 0 Registers (0x180-0x01f)
1083 *
1084 * DCR_MAL0_CFG Read/Write 0x180
1085 * Configuration Register
1086 * 0 SR MAL Software Reset
1087 * 1:7 Reserved
1088 * 8:9 PLBP PLB Priority
1089 * 10 GA Guarded Active
1090 * 11 OA Ordered Active
1091 * 12 PLBLE PLB Lock Error
1092 * 13:16 PLBLT PLB Latency Timer
1093 * 17 PLBB PLB Burst
1094 * 18:23 Reserved
1095 * 24 OPBBL OPB Bus Lock
1096 * 25:28 Reserved
1097 * 29 EOPIE End of Packet Interrupt Enable
1098 * 30 LEA Locked Error Active
1099 * 31 SD MAL Scroll Descriptor
1100 * DCR_MAL0_ESR Read/Clear 0x181
1101 * Error Status Register
1102 * 0 EVB Error Valid Bit
1103 * 1:6 CID Channel ID
1104 * 7:10 Reserved
1105 * 11 DE Descriptor Error
1106 * 12 ONE OPB Non-fullword Error
1107 * 13 OTE OPB Timeout Error
1108 * 14 OSE OPB Slave Error
1109 * 15 PEIN PLB Bus Error Indication
1110 * 16:26 Reserved
1111 * 27 DEI Descriptor Error Interrupt
1112 * 28 ONEI OPB Non-fullword Error Interrupt
1113 * 29 OTEI OPB Timeout Error Interrupt
1114 * 30 OSEI OPB Slave Error Interrupt
1115 * 31 PBEI PLB Bus Error Interrupt
1116 * DCR_MAL0_IER Read/Write 0x182
1117 * Interrupt Enable Register
1118 * 0:26 Reserved
1119 * 27 DE Descriptor Error
1120 * 28 NWE Non_W_Err_Int_Enable
1121 * 29 TO Time_Out_Int_Enable
1122 * 30 OPB OPB_Err_Int_Enable
1123 * 31 PLB PLB_Err_Int_Enable
1124 * DCR_MAL0_TXCASR Read/Write 0x184
1125 * Transmit Channel Active Set Register
1126 * 0:1 Transmit Channel Active Set
1127 * 2:31 Reserved
1128 * DCR_MAL0_TXCARR Read/Write 0x185
1129 * Transmit Channel Active Reset Register
1130 * 0:1 Transmit Channel Active Reset
1131 * 2:31 Reserved
1132 * DCR_MAL0_TXEOBISR Read/Clear 0x186
1133 * Transmit End of Buffer Interrupt Status Register
1134 * 0:1 Transmit Channel End-of-Buffer Interrupt
1135 * 2:31 Reserved
1136 * DCR_MAL0_TXDEIR Read/Clear 0x187
1137 * Transmit Descriptor Error Interrupt Register
1138 * 0:1 Transmit Descriptor Error Interrupt
1139 * 2:31 Reserved
1140 * DCR_MAL0_RXCASR Read/Write 0x190
1141 * Receive Channel Active Set Register
1142 * 0:1 Receive Channel Active Set
1143 * 2:31 Reserved
1144 * DCR_MAL0_RXCARR Read/Write 0x191
1145 * Receive Channel Active Reset Register
1146 * 0:1 Receive Channel Active Reset
1147 * 2:31 Reserved
1148 * DCR_MAL0_RXEOBISR Read/Clear 0x192
1149 * Receive End of Buffer Interrupt Status Register
1150 * 0:1 Receive Channel End-of-Buffer Interrupt
1151 * 2:31 Reserved
1152 * DCR_MAL0_RXDEIR Read/Clear 0x193
1153 * Receive Descriptor Error Interrupt Register
1154 * 0:1 Receive Descriptor Error Interrupt
1155 * 2:31 Reserved
1156 * DCR_MAL0_TXCTPnR(n) Read/Write 0x1a0-0x1a3
1157 * Transmit Channel n Table Pointer Register (n = 0-3)
1158 * 0:31 Channel Table Pointer
1159 * DCR_MAL0_RXCTP0R Read/Write 0x1c0
1160 * Receive Channel 0 Table Pointer Register
1161 * 0:31 Channel Table Pointer
1162 * DCR_MAL0_RCBS0 Read/Write 0x1e0
1163 * Receive Channel 0 Buffer Size Register
1164 * 0:23 Reserved
1165 * 24:31 Receive Channel Buffer Size
1166 */
1167 #if defined(PPC_IBM405_HAVE_MAL0)
1168 #define DCR_MAL0_CFG (0x180)
1169 #define MAL0_CFG_SR (0x80000000)
1170 #define MAL0_CFG_PLBP (0x00c00000)
1171 #define MAL0_CFG_GA (0x00200000)
1172 #define MAL0_CFG_OA (0x00100000)
1173 #define MAL0_CFG_PLBLE (0x00080000)
1174 #define MAL0_CFG_PLBLT (0x00078000)
1175 #define MAL0_CFG_PLBB (0x00004000)
1176 #define MAL0_CFG_OPBBL (0x00000080)
1177 #define MAL0_CFG_EOPIE (0x00000004)
1178 #define MAL0_CFG_LEA (0x00000002)
1179 #define MAL0_CFG_SD (0x00000001)
1180 #define DCR_MAL0_ESR (0x181)
1181 #define MAL0_ESR_EVB (0x80000000)
1182 #define MAL0_ESR_CID (0x7e000000)
1183 #define MAL0_ESR_DE (0x00100000)
1184 #define MAL0_ESR_ONE (0x00080000)
1185 #define MAL0_ESR_OTE (0x00040000)
1186 #define MAL0_ESR_OSE (0x00020000)
1187 #define MAL0_ESR_PEIN (0x00010000)
1188 #define MAL0_ESR_DEI (0x00000010)
1189 #define MAL0_ESR_ONEI (0x00000008)
1190 #define MAL0_ESR_OTEI (0x00000004)
1191 #define MAL0_ESR_OSEI (0x00000002)
1192 #define MAL0_ESR_PBEI (0x00000001)
1193 #define DCR_MAL0_IER (0x182)
1194 #define MAL0_IER_DE (0x00000010)
1195 #define MAL0_IER_NWE (0x00000008)
1196 #define MAL0_IER_TO (0x00000004)
1197 #define MAL0_IER_OPB (0x00000002)
1198 #define MAL0_IER_PLB (0x00000001)
1199 #define DCR_MAL0_TXCASR (0x184)
1200 #define MAL0_TXCASR_TCAS0 (0x80000000)
1201 #define MAL0_TXCASR_TCAS1 (0x40000000)
1202 #define DCR_MAL0_TXCARR (0x185)
1203 #define MAL0_TXCARR_TCAR0 (0x80000000)
1204 #define MAL0_TXCARR_TCAR1 (0x40000000)
1205 #define DCR_MAL0_TXEOBISR (0x186)
1206 #define MAL0_TXEOBISR_TCEBI0 (0x80000000)
1207 #define MAL0_TXEOBISR_TCEBI1 (0x40000000)
1208 #define DCR_MAL0_TXDEIR (0x187)
1209 #define MAL0_TXDEIR_TDEI0 (0x80000000)
1210 #define MAL0_TXDEIR_TDEI1 (0x40000000)
1211 #define DCR_MAL0_RXCASR (0x190)
1212 #define MAL0_RXCASR_RCAS0 (0x80000000)
1213 #define DCR_MAL0_RXCARR (0x191)
1214 #define MAL0_RXCARR_RCAR0 (0x80000000)
1215 #define DCR_MAL0_RXEOBISR (0x192)
1216 #define MAL0_RXEOBISR_RCEBI0 (0x80000000)
1217 #define DCR_MAL0_RXDEIR (0x193)
1218 #define MAL0_RXDEIR_RDEI0 (0x80000000)
1219 #define DCR_MAL0_TXCTPnR(n) (0x1a0 + n)
1220 #define DCR_MAL0_RXCTP0R (0x1c0)
1221 #define DCR_MAL0_RCBS0 (0x1e0)
1222 #define MAL0_RCBS0_RCBS (0x000000ff)
1226 /*****************************************************************************/
1227 /*
1228 * Memory Access Layer 1 Registers (0x200-0x27f)
1229 */
1230 #if defined(PPC_IBM405_HAVE_MAL1) && !defined(PPC_IBM405_HAVE_EVTCOUNT)
1234 /*****************************************************************************/
1235 /*
1236 * Memory Access Layer 2 Registers (0x280-0x2ff)
1237 */
1238 #if defined(PPC_IBM405_HAVE_MAL2)
1242 /*****************************************************************************/
1243 /*
1244 * Event Counters Registers (0x200-0x203)
1245 */
1246 #if defined(PPC_IBM405_HAVE_EVTCOUNT) && !defined(PPC_IBM405_HAVE_MAL1)