sys/dev/i2c/spdmemreg.h

   1 /* $NetBSD: spdmemreg.h,v 1.2 2008/09/27 06:58:09 pgoyette Exp $ */
   2
   3 /*
   4  * Copyright (c) 2007 Paul Goyette
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The name of the author may not be used to endorse or promote products
  16  *    derived from this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS
  19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  20  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  28  * POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 /* Constants for matching i2c bus address */
  32 #define SPDMEM_ADDRMASK 0x78
  33 #define SPDMEM_ADDR     0x50
  34
  35 /* possible values for the memory type */
  36 #define SPDMEM_MEMTYPE_FPM              0x01
  37 #define SPDMEM_MEMTYPE_EDO              0x02
  38 #define SPDMEM_MEMTYPE_PIPE_NIBBLE      0x03
  39 #define SPDMEM_MEMTYPE_SDRAM            0x04
  40 #define SPDMEM_MEMTYPE_ROM              0x05
  41 #define SPDMEM_MEMTYPE_DDRSGRAM         0x06
  42 #define SPDMEM_MEMTYPE_DDRSDRAM         0x07
  43 #define SPDMEM_MEMTYPE_DDR2SDRAM        0x08
  44 #define SPDMEM_MEMTYPE_FBDIMM           0x09
  45 #define SPDMEM_MEMTYPE_FBDIMM_PROBE     0x0A
  46 #define SPDMEM_MEMTYPE_DDR3SDRAM        0x0B
  47
  48 #define SPDMEM_MEMTYPE_RAMBUS           0x11
  49 #define SPDMEM_MEMTYPE_DIRECTRAMBUS     0x01
  50
  51 /* Encodings of the size used/total byte for certain memory types    */
  52 #define SPDMEM_SPDSIZE_MASK             0x0F    /* SPD EEPROM Size   */
  53
  54 #define SPDMEM_SPDLEN_128               0x00    /* SPD EEPROM Sizes  */
  55 #define SPDMEM_SPDLEN_176               0x10
  56 #define SPDMEM_SPDLEN_256               0x20
  57 #define SPDMEM_SPDLEN_MASK              0x70    /* Bits 4 - 6        */
  58
  59 #define SPDMEM_SPDCRC_116               0x80    /* CRC Bytes covered */
  60 #define SPDMEM_SPDCRC_125               0x00
  61 #define SPDMEM_SPDCRC_MASK              0x80    /* Bit 7             */
  62
  63 /* possible values for the supply voltage */
  64 #define SPDMEM_VOLTAGE_TTL_5V           0x00
  65 #define SPDMEM_VOLTAGE_TTL_LV           0x01
  66 #define SPDMEM_VOLTAGE_HSTTL_1_5V       0x02
  67 #define SPDMEM_VOLTAGE_SSTL_3_3V        0x03
  68 #define SPDMEM_VOLTAGE_SSTL_2_5V        0x04
  69 #define SPDMEM_VOLTAGE_SSTL_1_8V        0x05
  70
  71 /* possible values for module configuration */
  72 #define SPDMEM_MODCONFIG_PARITY         0x01
  73 #define SPDMEM_MODCONFIG_ECC            0x02
  74
  75 /* for DDR2, module configuration is a bit-mask field */
  76 #define SPDMEM_MODCONFIG_HAS_DATA_PARITY        0x01
  77 #define SPDMEM_MODCONFIG_HAS_DATA_ECC           0x02
  78 #define SPDMEM_MODCONFIG_HAS_ADDR_CMD_PARITY    0x04
  79
  80 /* possible values for the refresh field */
  81 #define SPDMEM_REFRESH_STD              0x00
  82 #define SPDMEM_REFRESH_QUARTER          0x01
  83 #define SPDMEM_REFRESH_HALF             0x02
  84 #define SPDMEM_REFRESH_TWOX             0x03
  85 #define SPDMEM_REFRESH_FOURX            0x04
  86 #define SPDMEM_REFRESH_EIGHTX           0x05
  87 #define SPDMEM_REFRESH_SELFREFRESH      0x80
  88
  89 /* superset types */
  90 #define SPDMEM_SUPERSET_ESDRAM          0x01
  91 #define SPDMEM_SUPERSET_DDR_ESDRAM      0x02
  92 #define SPDMEM_SUPERSET_EDO_PEM         0x03
  93 #define SPDMEM_SUPERSET_SDRAM_PEM       0x04
  94
  95 /* bit masks for "registered" module attribute */
  96 #define SPDMEM_SDR_MASK_REG             0x02
  97 #define SPDMEM_DDR_MASK_REG             0x02
  98 #define SPDMEM_DDR2_MASK_REG            0x05
  99
 100 #define SPDMEM_DDR3_TYPE_RDIMM          0x01
 101 #define SPDMEM_DDR3_TYPE_UDIMM          0x02
 102 #define SPDMEM_DDR3_TYPE_SODIMM         0x03
 103 #define SPDMEM_DDR3_TYPE_MICRODIMM      0x04
 104 #define SPDMEM_DDR3_TYPE_MINI_RDIMM     0x05
 105 #define SPDMEM_DDR3_TYPE_MINI_UDIMM     0x06