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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / ic / adw.c
blobd072722f3fcf52a8eb045a2a6d45565c8b05128a
1 /* $NetBSD: adw.c,v 1.49 2008/04/08 12:07:25 cegger Exp $ */
2
3 /*
4 * Generic driver for the Advanced Systems Inc. SCSI controllers
5 *
6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
7 * All rights reserved.
8 *
9 * Author: Baldassare Dante Profeta <dante@mclink.it>
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 #include <sys/cdefs.h>
41 __KERNEL_RCSID(0, "$NetBSD: adw.c,v 1.49 2008/04/08 12:07:25 cegger Exp $");
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/callout.h>
46 #include <sys/kernel.h>
47 #include <sys/errno.h>
48 #include <sys/ioctl.h>
49 #include <sys/device.h>
50 #include <sys/malloc.h>
51 #include <sys/buf.h>
52 #include <sys/proc.h>
53
54 #include <sys/bus.h>
55 #include <sys/intr.h>
56
57 #include <uvm/uvm_extern.h>
58
59 #include <dev/scsipi/scsi_all.h>
60 #include <dev/scsipi/scsipi_all.h>
61 #include <dev/scsipi/scsiconf.h>
62
63 #include <dev/ic/adwlib.h>
64 #include <dev/ic/adwmcode.h>
65 #include <dev/ic/adw.h>
66
67 #ifndef DDB
68 #define Debugger() panic("should call debugger here (adw.c)")
69 #endif /* ! DDB */
70
71 /******************************************************************************/
72
73
74 static int adw_alloc_controls(ADW_SOFTC *);
75 static int adw_alloc_carriers(ADW_SOFTC *);
76 static int adw_create_ccbs(ADW_SOFTC *, ADW_CCB *, int);
77 static void adw_free_ccb(ADW_SOFTC *, ADW_CCB *);
78 static void adw_reset_ccb(ADW_CCB *);
79 static int adw_init_ccb(ADW_SOFTC *, ADW_CCB *);
80 static ADW_CCB *adw_get_ccb(ADW_SOFTC *);
81 static int adw_queue_ccb(ADW_SOFTC *, ADW_CCB *);
82
83 static void adw_scsipi_request(struct scsipi_channel *,
84 scsipi_adapter_req_t, void *);
85 static int adw_build_req(ADW_SOFTC *, ADW_CCB *);
86 static void adw_build_sglist(ADW_CCB *, ADW_SCSI_REQ_Q *, ADW_SG_BLOCK *);
87 static void adwminphys(struct buf *);
88 static void adw_isr_callback(ADW_SOFTC *, ADW_SCSI_REQ_Q *);
89 static void adw_async_callback(ADW_SOFTC *, u_int8_t);
90
91 static void adw_print_info(ADW_SOFTC *, int);
92
93 static int adw_poll(ADW_SOFTC *, struct scsipi_xfer *, int);
94 static void adw_timeout(void *);
95 static void adw_reset_bus(ADW_SOFTC *);
96
97
98 /******************************************************************************/
99 /* DMA Mapping for Control Blocks */
100 /******************************************************************************/
101
102
103 static int
104 adw_alloc_controls(ADW_SOFTC *sc)
105 {
106 bus_dma_segment_t seg;
107 int error, rseg;
108
109 /*
110 * Allocate the control structure.
111 */
112 if ((error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct adw_control),
113 PAGE_SIZE, 0, &seg, 1, &rseg,
114 BUS_DMA_NOWAIT)) != 0) {
115 aprint_error_dev(&sc->sc_dev, "unable to allocate control structures,"
116 " error = %d\n", error);
117 return (error);
118 }
119 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
120 sizeof(struct adw_control), (void **) & sc->sc_control,
121 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
122 aprint_error_dev(&sc->sc_dev, "unable to map control structures, error = %d\n",
123 error);
124 return (error);
125 }
126
127 /*
128 * Create and load the DMA map used for the control blocks.
129 */
130 if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct adw_control),
131 1, sizeof(struct adw_control), 0, BUS_DMA_NOWAIT,
132 &sc->sc_dmamap_control)) != 0) {
133 aprint_error_dev(&sc->sc_dev, "unable to create control DMA map, error = %d\n",
134 error);
135 return (error);
136 }
137 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_control,
138 sc->sc_control, sizeof(struct adw_control), NULL,
139 BUS_DMA_NOWAIT)) != 0) {
140 aprint_error_dev(&sc->sc_dev, "unable to load control DMA map, error = %d\n",
141 error);
142 return (error);
143 }
144
145 return (0);
146 }
147
148
149 static int
150 adw_alloc_carriers(ADW_SOFTC *sc)
151 {
152 bus_dma_segment_t seg;
153 int error, rseg;
154
155 /*
156 * Allocate the control structure.
157 */
158 sc->sc_control->carriers = malloc(sizeof(ADW_CARRIER) * ADW_MAX_CARRIER,
159 M_DEVBUF, M_WAITOK);
160 if(!sc->sc_control->carriers) {
161 aprint_error_dev(&sc->sc_dev,
162 "malloc() failed in allocating carrier structures\n");
163 return (ENOMEM);
164 }
165
166 if ((error = bus_dmamem_alloc(sc->sc_dmat,
167 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER,
168 0x10, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
169 aprint_error_dev(&sc->sc_dev, "unable to allocate carrier structures,"
170 " error = %d\n", error);
171 return (error);
172 }
173 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
174 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER,
175 (void **) &sc->sc_control->carriers,
176 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
177 aprint_error_dev(&sc->sc_dev, "unable to map carrier structures,"
178 " error = %d\n", error);
179 return (error);
180 }
181
182 /*
183 * Create and load the DMA map used for the control blocks.
184 */
185 if ((error = bus_dmamap_create(sc->sc_dmat,
186 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 1,
187 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, 0,BUS_DMA_NOWAIT,
188 &sc->sc_dmamap_carrier)) != 0) {
189 aprint_error_dev(&sc->sc_dev, "unable to create carriers DMA map,"
190 " error = %d\n", error);
191 return (error);
192 }
193 if ((error = bus_dmamap_load(sc->sc_dmat,
194 sc->sc_dmamap_carrier, sc->sc_control->carriers,
195 sizeof(ADW_CARRIER) * ADW_MAX_CARRIER, NULL,
196 BUS_DMA_NOWAIT)) != 0) {
197 aprint_error_dev(&sc->sc_dev, "unable to load carriers DMA map,"
198 " error = %d\n", error);
199 return (error);
200 }
201
202 return (0);
203 }
204
205
206 /******************************************************************************/
207 /* Control Blocks routines */
208 /******************************************************************************/
209
210
211 /*
212 * Create a set of ccbs and add them to the free list. Called once
213 * by adw_init(). We return the number of CCBs successfully created.
214 */
215 static int
216 adw_create_ccbs(ADW_SOFTC *sc, ADW_CCB *ccbstore, int count)
217 {
218 ADW_CCB *ccb;
219 int i, error;
220
221 for (i = 0; i < count; i++) {
222 ccb = &ccbstore[i];
223 if ((error = adw_init_ccb(sc, ccb)) != 0) {
224 aprint_error_dev(&sc->sc_dev, "unable to initialize ccb, error = %d\n",
225 error);
226 return (i);
227 }
228 TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, chain);
229 }
230
231 return (i);
232 }
233
234
235 /*
236 * A ccb is put onto the free list.
237 */
238 static void
239 adw_free_ccb(ADW_SOFTC *sc, ADW_CCB *ccb)
240 {
241 int s;
242
243 s = splbio();
244
245 adw_reset_ccb(ccb);
246 TAILQ_INSERT_HEAD(&sc->sc_free_ccb, ccb, chain);
247
248 splx(s);
249 }
250
251
252 static void
253 adw_reset_ccb(ADW_CCB *ccb)
254 {
255
256 ccb->flags = 0;
257 }
258
259
260 static int
261 adw_init_ccb(ADW_SOFTC *sc, ADW_CCB *ccb)
262 {
263 int hashnum, error;
264
265 /*
266 * Create the DMA map for this CCB.
267 */
268 error = bus_dmamap_create(sc->sc_dmat,
269 (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
270 ADW_MAX_SG_LIST, (ADW_MAX_SG_LIST - 1) * PAGE_SIZE,
271 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ccb->dmamap_xfer);
272 if (error) {
273 aprint_error_dev(&sc->sc_dev, "unable to create CCB DMA map, error = %d\n",
274 error);
275 return (error);
276 }
277
278 /*
279 * put in the phystokv hash table
280 * Never gets taken out.
281 */
282 ccb->hashkey = htole32(sc->sc_dmamap_control->dm_segs[0].ds_addr +
283 ADW_CCB_OFF(ccb));
284 hashnum = CCB_HASH(ccb->hashkey);
285 ccb->nexthash = sc->sc_ccbhash[hashnum];
286 sc->sc_ccbhash[hashnum] = ccb;
287 adw_reset_ccb(ccb);
288 return (0);
289 }
290
291
292 /*
293 * Get a free ccb
294 *
295 * If there are none, see if we can allocate a new one
296 */
297 static ADW_CCB *
298 adw_get_ccb(ADW_SOFTC *sc)
299 {
300 ADW_CCB *ccb = 0;
301 int s;
302
303 s = splbio();
304
305 ccb = sc->sc_free_ccb.tqh_first;
306 if (ccb != NULL) {
307 TAILQ_REMOVE(&sc->sc_free_ccb, ccb, chain);
308 ccb->flags |= CCB_ALLOC;
309 }
310 splx(s);
311 return (ccb);
312 }
313
314
315 /*
316 * Given a physical address, find the ccb that it corresponds to.
317 */
318 ADW_CCB *
319 adw_ccb_phys_kv(ADW_SOFTC *sc, u_int32_t ccb_phys)
320 {
321 int hashnum = CCB_HASH(ccb_phys);
322 ADW_CCB *ccb = sc->sc_ccbhash[hashnum];
323
324 while (ccb) {
325 if (ccb->hashkey == ccb_phys)
326 break;
327 ccb = ccb->nexthash;
328 }
329 return (ccb);
330 }
331
332
333 /*
334 * Queue a CCB to be sent to the controller, and send it if possible.
335 */
336 static int
337 adw_queue_ccb(ADW_SOFTC *sc, ADW_CCB *ccb)
338 {
339 int errcode = ADW_SUCCESS;
340
341 TAILQ_INSERT_TAIL(&sc->sc_waiting_ccb, ccb, chain);
342
343 while ((ccb = sc->sc_waiting_ccb.tqh_first) != NULL) {
344
345 TAILQ_REMOVE(&sc->sc_waiting_ccb, ccb, chain);
346 errcode = AdwExeScsiQueue(sc, &ccb->scsiq);
347 switch(errcode) {
348 case ADW_SUCCESS:
349 break;
350
351 case ADW_BUSY:
352 printf("ADW_BUSY\n");
353 return(ADW_BUSY);
354
355 case ADW_ERROR:
356 printf("ADW_ERROR\n");
357 return(ADW_ERROR);
358 }
359
360 TAILQ_INSERT_TAIL(&sc->sc_pending_ccb, ccb, chain);
361
362 if ((ccb->xs->xs_control & XS_CTL_POLL) == 0)
363 callout_reset(&ccb->xs->xs_callout,
364 mstohz(ccb->timeout), adw_timeout, ccb);
365 }
366
367 return(errcode);
368 }
369
370
371 /******************************************************************************/
372 /* SCSI layer interfacing routines */
373 /******************************************************************************/
374
375
376 int
377 adw_init(ADW_SOFTC *sc)
378 {
379 u_int16_t warn_code;
380
381
382 sc->cfg.lib_version = (ADW_LIB_VERSION_MAJOR << 8) |
383 ADW_LIB_VERSION_MINOR;
384 sc->cfg.chip_version =
385 ADW_GET_CHIP_VERSION(sc->sc_iot, sc->sc_ioh, sc->bus_type);
386
387 /*
388 * Reset the chip to start and allow register writes.
389 */
390 if (ADW_FIND_SIGNATURE(sc->sc_iot, sc->sc_ioh) == 0) {
391 panic("adw_init: adw_find_signature failed");
392 } else {
393 AdwResetChip(sc->sc_iot, sc->sc_ioh);
394
395 warn_code = AdwInitFromEEPROM(sc);
396
397 if (warn_code & ADW_WARN_EEPROM_CHKSUM)
398 aprint_error_dev(&sc->sc_dev, "Bad checksum found. "
399 "Setting default values\n");
400 if (warn_code & ADW_WARN_EEPROM_TERMINATION)
401 aprint_error_dev(&sc->sc_dev, "Bad bus termination setting."
402 "Using automatic termination.\n");
403 }
404
405 sc->isr_callback = (ADW_CALLBACK) adw_isr_callback;
406 sc->async_callback = (ADW_CALLBACK) adw_async_callback;
407
408 return 0;
409 }
410
411
412 void
413 adw_attach(ADW_SOFTC *sc)
414 {
415 struct scsipi_adapter *adapt = &sc->sc_adapter;
416 struct scsipi_channel *chan = &sc->sc_channel;
417 int ncontrols, error;
418
419 TAILQ_INIT(&sc->sc_free_ccb);
420 TAILQ_INIT(&sc->sc_waiting_ccb);
421 TAILQ_INIT(&sc->sc_pending_ccb);
422
423 /*
424 * Allocate the Control Blocks.
425 */
426 error = adw_alloc_controls(sc);
427 if (error)
428 return; /* (error) */ ;
429
430 memset(sc->sc_control, 0, sizeof(struct adw_control));
431
432 /*
433 * Create and initialize the Control Blocks.
434 */
435 ncontrols = adw_create_ccbs(sc, sc->sc_control->ccbs, ADW_MAX_CCB);
436 if (ncontrols == 0) {
437 aprint_error_dev(&sc->sc_dev, "unable to create Control Blocks\n");
438 return; /* (ENOMEM) */ ;
439 } else if (ncontrols != ADW_MAX_CCB) {
440 aprint_error_dev(&sc->sc_dev, "WARNING: only %d of %d Control Blocks"
441 " created\n",
442 ncontrols, ADW_MAX_CCB);
443 }
444
445 /*
446 * Create and initialize the Carriers.
447 */
448 error = adw_alloc_carriers(sc);
449 if (error)
450 return; /* (error) */ ;
451
452 /*
453 * Zero's the freeze_device status
454 */
455 memset(sc->sc_freeze_dev, 0, sizeof(sc->sc_freeze_dev));
456
457 /*
458 * Initialize the adapter
459 */
460 switch (AdwInitDriver(sc)) {
461 case ADW_IERR_BIST_PRE_TEST:
462 panic("%s: BIST pre-test error",
463 device_xname(&sc->sc_dev));
464 break;
465
466 case ADW_IERR_BIST_RAM_TEST:
467 panic("%s: BIST RAM test error",
468 device_xname(&sc->sc_dev));
469 break;
470
471 case ADW_IERR_MCODE_CHKSUM:
472 panic("%s: Microcode checksum error",
473 device_xname(&sc->sc_dev));
474 break;
475
476 case ADW_IERR_ILLEGAL_CONNECTION:
477 panic("%s: All three connectors are in use",
478 device_xname(&sc->sc_dev));
479 break;
480
481 case ADW_IERR_REVERSED_CABLE:
482 panic("%s: Cable is reversed",
483 device_xname(&sc->sc_dev));
484 break;
485
486 case ADW_IERR_HVD_DEVICE:
487 panic("%s: HVD attached to LVD connector",
488 device_xname(&sc->sc_dev));
489 break;
490
491 case ADW_IERR_SINGLE_END_DEVICE:
492 panic("%s: single-ended device is attached to"
493 " one of the connectors",
494 device_xname(&sc->sc_dev));
495 break;
496
497 case ADW_IERR_NO_CARRIER:
498 panic("%s: unable to create Carriers",
499 device_xname(&sc->sc_dev));
500 break;
501
502 case ADW_WARN_BUSRESET_ERROR:
503 aprint_error_dev(&sc->sc_dev, "WARNING: Bus Reset Error\n");
504 break;
505 }
506
507 /*
508 * Fill in the scsipi_adapter.
509 */
510 memset(adapt, 0, sizeof(*adapt));
511 adapt->adapt_dev = &sc->sc_dev;
512 adapt->adapt_nchannels = 1;
513 adapt->adapt_openings = ncontrols;
514 adapt->adapt_max_periph = adapt->adapt_openings;
515 adapt->adapt_request = adw_scsipi_request;
516 adapt->adapt_minphys = adwminphys;
517
518 /*
519 * Fill in the scsipi_channel.
520 */
521 memset(chan, 0, sizeof(*chan));
522 chan->chan_adapter = adapt;
523 chan->chan_bustype = &scsi_bustype;
524 chan->chan_channel = 0;
525 chan->chan_ntargets = ADW_MAX_TID + 1;
526 chan->chan_nluns = 8;
527 chan->chan_id = sc->chip_scsi_id;
528
529 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint);
530 }
531
532
533 static void
534 adwminphys(struct buf *bp)
535 {
536
537 if (bp->b_bcount > ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE))
538 bp->b_bcount = ((ADW_MAX_SG_LIST - 1) * PAGE_SIZE);
539 minphys(bp);
540 }
541
542
543 /*
544 * start a scsi operation given the command and the data address.
545 * Also needs the unit, target and lu.
546 */
547 static void
548 adw_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req,
549 void *arg)
550 {
551 struct scsipi_xfer *xs;
552 ADW_SOFTC *sc = (void *)chan->chan_adapter->adapt_dev;
553 ADW_CCB *ccb;
554 int s, retry;
555
556 switch (req) {
557 case ADAPTER_REQ_RUN_XFER:
558 xs = arg;
559
560 /*
561 * get a ccb to use. If the transfer
562 * is from a buf (possibly from interrupt time)
563 * then we can't allow it to sleep
564 */
565
566 ccb = adw_get_ccb(sc);
567 #ifdef DIAGNOSTIC
568 /*
569 * This should never happen as we track the resources
570 * in the mid-layer.
571 */
572 if (ccb == NULL) {
573 scsipi_printaddr(xs->xs_periph);
574 printf("unable to allocate ccb\n");
575 panic("adw_scsipi_request");
576 }
577 #endif
578
579 ccb->xs = xs;
580 ccb->timeout = xs->timeout;
581
582 if (adw_build_req(sc, ccb)) {
583 s = splbio();
584 retry = adw_queue_ccb(sc, ccb);
585 splx(s);
586
587 switch(retry) {
588 case ADW_BUSY:
589 xs->error = XS_RESOURCE_SHORTAGE;
590 adw_free_ccb(sc, ccb);
591 scsipi_done(xs);
592 return;
593
594 case ADW_ERROR:
595 xs->error = XS_DRIVER_STUFFUP;
596 adw_free_ccb(sc, ccb);
597 scsipi_done(xs);
598 return;
599 }
600 if ((xs->xs_control & XS_CTL_POLL) == 0)
601 return;
602 /*
603 * Not allowed to use interrupts, poll for completion.
604 */
605 if (adw_poll(sc, xs, ccb->timeout)) {
606 adw_timeout(ccb);
607 if (adw_poll(sc, xs, ccb->timeout))
608 adw_timeout(ccb);
609 }
610 }
611 return;
612
613 case ADAPTER_REQ_GROW_RESOURCES:
614 /* XXX Not supported. */
615 return;
616
617 case ADAPTER_REQ_SET_XFER_MODE:
618 /* XXX XXX XXX */
619 return;
620 }
621 }
622
623
624 /*
625 * Build a request structure for the Wide Boards.
626 */
627 static int
628 adw_build_req(ADW_SOFTC *sc, ADW_CCB *ccb)
629 {
630 struct scsipi_xfer *xs = ccb->xs;
631 struct scsipi_periph *periph = xs->xs_periph;
632 bus_dma_tag_t dmat = sc->sc_dmat;
633 ADW_SCSI_REQ_Q *scsiqp;
634 int error;
635
636 scsiqp = &ccb->scsiq;
637 memset(scsiqp, 0, sizeof(ADW_SCSI_REQ_Q));
638
639 /*
640 * Set the ADW_SCSI_REQ_Q 'ccb_ptr' to point to the
641 * physical CCB structure.
642 */
643 scsiqp->ccb_ptr = ccb->hashkey;
644
645 /*
646 * Build the ADW_SCSI_REQ_Q request.
647 */
648
649 /*
650 * Set CDB length and copy it to the request structure.
651 * For wide boards a CDB length maximum of 16 bytes
652 * is supported.
653 */
654 memcpy(&scsiqp->cdb, xs->cmd, ((scsiqp->cdb_len = xs->cmdlen) <= 12)?
655 xs->cmdlen : 12 );
656 if(xs->cmdlen > 12)
657 memcpy(&scsiqp->cdb16, &(xs->cmd[12]), xs->cmdlen - 12);
658
659 scsiqp->target_id = periph->periph_target;
660 scsiqp->target_lun = periph->periph_lun;
661
662 scsiqp->vsense_addr = &ccb->scsi_sense;
663 scsiqp->sense_addr = htole32(sc->sc_dmamap_control->dm_segs[0].ds_addr +
664 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsi_sense));
665 scsiqp->sense_len = sizeof(struct scsi_sense_data);
666
667 /*
668 * Build ADW_SCSI_REQ_Q for a scatter-gather buffer command.
669 */
670 if (xs->datalen) {
671 /*
672 * Map the DMA transfer.
673 */
674 #ifdef TFS
675 if (xs->xs_control & SCSI_DATA_UIO) {
676 error = bus_dmamap_load_uio(dmat,
677 ccb->dmamap_xfer, (struct uio *) xs->data,
678 ((flags & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT :
679 BUS_DMA_WAITOK) | BUS_DMA_STREAMING |
680 ((flags & XS_CTL_DATA_IN) ? BUS_DMA_READ :
681 BUS_DMA_WRITE));
682 } else
683 #endif /* TFS */
684 {
685 error = bus_dmamap_load(dmat,
686 ccb->dmamap_xfer, xs->data, xs->datalen, NULL,
687 ((xs->xs_control & XS_CTL_NOSLEEP) ?
688 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) |
689 BUS_DMA_STREAMING |
690 ((xs->xs_control & XS_CTL_DATA_IN) ?
691 BUS_DMA_READ : BUS_DMA_WRITE));
692 }
693
694 switch (error) {
695 case 0:
696 break;
697 case ENOMEM:
698 case EAGAIN:
699 xs->error = XS_RESOURCE_SHORTAGE;
700 goto out_bad;
701
702 default:
703 xs->error = XS_DRIVER_STUFFUP;
704 aprint_error_dev(&sc->sc_dev, "error %d loading DMA map\n",
705 error);
706 out_bad:
707 adw_free_ccb(sc, ccb);
708 scsipi_done(xs);
709 return(0);
710 }
711
712 bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
713 ccb->dmamap_xfer->dm_mapsize,
714 (xs->xs_control & XS_CTL_DATA_IN) ?
715 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
716
717 /*
718 * Build scatter-gather list.
719 */
720 scsiqp->data_cnt = htole32(xs->datalen);
721 scsiqp->vdata_addr = xs->data;
722 scsiqp->data_addr = htole32(ccb->dmamap_xfer->dm_segs[0].ds_addr);
723 memset(ccb->sg_block, 0,
724 sizeof(ADW_SG_BLOCK) * ADW_NUM_SG_BLOCK);
725 adw_build_sglist(ccb, scsiqp, ccb->sg_block);
726 } else {
727 /*
728 * No data xfer, use non S/G values.
729 */
730 scsiqp->data_cnt = 0;
731 scsiqp->vdata_addr = 0;
732 scsiqp->data_addr = 0;
733 }
734
735 return (1);
736 }
737
738
739 /*
740 * Build scatter-gather list for Wide Boards.
741 */
742 static void
743 adw_build_sglist(ADW_CCB *ccb, ADW_SCSI_REQ_Q *scsiqp, ADW_SG_BLOCK *sg_block)
744 {
745 u_long sg_block_next_addr; /* block and its next */
746 u_int32_t sg_block_physical_addr;
747 int i; /* how many SG entries */
748 bus_dma_segment_t *sg_list = &ccb->dmamap_xfer->dm_segs[0];
749 int sg_elem_cnt = ccb->dmamap_xfer->dm_nsegs;
750
751
752 sg_block_next_addr = (u_long) sg_block; /* allow math operation */
753 sg_block_physical_addr = le32toh(ccb->hashkey) +
754 offsetof(struct adw_ccb, sg_block[0]);
755 scsiqp->sg_real_addr = htole32(sg_block_physical_addr);
756
757 /*
758 * If there are more than NO_OF_SG_PER_BLOCK DMA segments (hw sg-list)
759 * then split the request into multiple sg-list blocks.
760 */
761
762 do {
763 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
764 sg_block->sg_list[i].sg_addr = htole32(sg_list->ds_addr);
765 sg_block->sg_list[i].sg_count = htole32(sg_list->ds_len);
766
767 if (--sg_elem_cnt == 0) {
768 /* last entry, get out */
769 sg_block->sg_cnt = i + 1;
770 sg_block->sg_ptr = 0; /* next link = NULL */
771 return;
772 }
773 sg_list++;
774 }
775 sg_block_next_addr += sizeof(ADW_SG_BLOCK);
776 sg_block_physical_addr += sizeof(ADW_SG_BLOCK);
777
778 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
779 sg_block->sg_ptr = htole32(sg_block_physical_addr);
780 sg_block = (ADW_SG_BLOCK *) sg_block_next_addr; /* virt. addr */
781 } while (1);
782 }
783
784
785 /******************************************************************************/
786 /* Interrupts and TimeOut routines */
787 /******************************************************************************/
788
789
790 int
791 adw_intr(void *arg)
792 {
793 ADW_SOFTC *sc = arg;
794
795
796 if(AdwISR(sc) != ADW_FALSE) {
797 return (1);
798 }
799
800 return (0);
801 }
802
803
804 /*
805 * Poll a particular unit, looking for a particular xs
806 */
807 static int
808 adw_poll(ADW_SOFTC *sc, struct scsipi_xfer *xs, int count)
809 {
810
811 /* timeouts are in msec, so we loop in 1000 usec cycles */
812 while (count) {
813 adw_intr(sc);
814 if (xs->xs_status & XS_STS_DONE)
815 return (0);
816 delay(1000); /* only happens in boot so ok */
817 count--;
818 }
819 return (1);
820 }
821
822
823 static void
824 adw_timeout(void *arg)
825 {
826 ADW_CCB *ccb = arg;
827 struct scsipi_xfer *xs = ccb->xs;
828 struct scsipi_periph *periph = xs->xs_periph;
829 ADW_SOFTC *sc =
830 (void *)periph->periph_channel->chan_adapter->adapt_dev;
831 int s;
832
833 scsipi_printaddr(periph);
834 printf("timed out");
835
836 s = splbio();
837
838 if (ccb->flags & CCB_ABORTED) {
839 /*
840 * Abort Timed Out
841 *
842 * No more opportunities. Lets try resetting the bus and
843 * reinitialize the host adapter.
844 */
845 callout_stop(&xs->xs_callout);
846 printf(" AGAIN. Resetting SCSI Bus\n");
847 adw_reset_bus(sc);
848 splx(s);
849 return;
850 } else if (ccb->flags & CCB_ABORTING) {
851 /*
852 * Abort the operation that has timed out.
853 *
854 * Second opportunity.
855 */
856 printf("\n");
857 xs->error = XS_TIMEOUT;
858 ccb->flags |= CCB_ABORTED;
859 #if 0
860 /*
861 * - XXX - 3.3a microcode is BROKEN!!!
862 *
863 * We cannot abort a CCB, so we can only hope the command
864 * get completed before the next timeout, otherwise a
865 * Bus Reset will arrive inexorably.
866 */
867 /*
868 * ADW_ABORT_CCB() makes the board to generate an interrupt
869 *
870 * - XXX - The above assertion MUST be verified (and this
871 * code changed as well [callout_*()]), when the
872 * ADW_ABORT_CCB will be working again
873 */
874 ADW_ABORT_CCB(sc, ccb);
875 #endif
876 /*
877 * waiting for multishot callout_reset() let's restart it
878 * by hand so the next time a timeout event will occur
879 * we will reset the bus.
880 */
881 callout_reset(&xs->xs_callout,
882 mstohz(ccb->timeout), adw_timeout, ccb);
883 } else {
884 /*
885 * Abort the operation that has timed out.
886 *
887 * First opportunity.
888 */
889 printf("\n");
890 xs->error = XS_TIMEOUT;
891 ccb->flags |= CCB_ABORTING;
892 #if 0
893 /*
894 * - XXX - 3.3a microcode is BROKEN!!!
895 *
896 * We cannot abort a CCB, so we can only hope the command
897 * get completed before the next 2 timeout, otherwise a
898 * Bus Reset will arrive inexorably.
899 */
900 /*
901 * ADW_ABORT_CCB() makes the board to generate an interrupt
902 *
903 * - XXX - The above assertion MUST be verified (and this
904 * code changed as well [callout_*()]), when the
905 * ADW_ABORT_CCB will be working again
906 */
907 ADW_ABORT_CCB(sc, ccb);
908 #endif
909 /*
910 * waiting for multishot callout_reset() let's restart it
911 * by hand so to give a second opportunity to the command
912 * which timed-out.
913 */
914 callout_reset(&xs->xs_callout,
915 mstohz(ccb->timeout), adw_timeout, ccb);
916 }
917
918 splx(s);
919 }
920
921
922 static void
923 adw_reset_bus(ADW_SOFTC *sc)
924 {
925 ADW_CCB *ccb;
926 int s;
927 struct scsipi_xfer *xs;
928
929 s = splbio();
930 AdwResetSCSIBus(sc);
931 while((ccb = TAILQ_LAST(&sc->sc_pending_ccb,
932 adw_pending_ccb)) != NULL) {
933 callout_stop(&ccb->xs->xs_callout);
934 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain);
935 xs = ccb->xs;
936 adw_free_ccb(sc, ccb);
937 xs->error = XS_RESOURCE_SHORTAGE;
938 scsipi_done(xs);
939 }
940 splx(s);
941 }
942
943
944 /******************************************************************************/
945 /* Host Adapter and Peripherals Information Routines */
946 /******************************************************************************/
947
948
949 static void
950 adw_print_info(ADW_SOFTC *sc, int tid)
951 {
952 bus_space_tag_t iot = sc->sc_iot;
953 bus_space_handle_t ioh = sc->sc_ioh;
954 u_int16_t wdtr_able, wdtr_done, wdtr;
955 u_int16_t sdtr_able, sdtr_done, sdtr, period;
956 static int wdtr_reneg = 0, sdtr_reneg = 0;
957
958 if (tid == 0){
959 wdtr_reneg = sdtr_reneg = 0;
960 }
961
962 printf("%s: target %d ", device_xname(&sc->sc_dev), tid);
963
964 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, wdtr_able);
965 if(wdtr_able & ADW_TID_TO_TIDMASK(tid)) {
966 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, wdtr_done);
967 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_DEVICE_HSHK_CFG_TABLE +
968 (2 * tid), wdtr);
969 printf("using %d-bits wide, ", (wdtr & 0x8000)? 16 : 8);
970 if((wdtr_done & ADW_TID_TO_TIDMASK(tid)) == 0)
971 wdtr_reneg = 1;
972 } else {
973 printf("wide transfers disabled, ");
974 }
975
976 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able);
977 if(sdtr_able & ADW_TID_TO_TIDMASK(tid)) {
978 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, sdtr_done);
979 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_DEVICE_HSHK_CFG_TABLE +
980 (2 * tid), sdtr);
981 sdtr &= ~0x8000;
982 if((sdtr & 0x1F) != 0) {
983 if((sdtr & 0x1F00) == 0x1100){
984 printf("80.0 MHz");
985 } else if((sdtr & 0x1F00) == 0x1000){
986 printf("40.0 MHz");
987 } else {
988 /* <= 20.0 MHz */
989 period = (((sdtr >> 8) * 25) + 50)/4;
990 if(period == 0) {
991 /* Should never happen. */
992 printf("? MHz");
993 } else {
994 printf("%d.%d MHz", 250/period,
995 ADW_TENTHS(250, period));
996 }
997 }
998 printf(" synchronous transfers\n");
999 } else {
1000 printf("asynchronous transfers\n");
1001 }
1002 if((sdtr_done & ADW_TID_TO_TIDMASK(tid)) == 0)
1003 sdtr_reneg = 1;
1004 } else {
1005 printf("synchronous transfers disabled\n");
1006 }
1007
1008 if(wdtr_reneg || sdtr_reneg) {
1009 printf("%s: target %d %s", device_xname(&sc->sc_dev), tid,
1010 (wdtr_reneg)? ((sdtr_reneg)? "wide/sync" : "wide") :
1011 ((sdtr_reneg)? "sync" : "") );
1012 printf(" renegotiation pending before next command.\n");
1013 }
1014 }
1015
1016
1017 /******************************************************************************/
1018 /* WIDE boards Interrupt callbacks */
1019 /******************************************************************************/
1020
1021
1022 /*
1023 * adw_isr_callback() - Second Level Interrupt Handler called by AdwISR()
1024 *
1025 * Interrupt callback function for the Wide SCSI Adv Library.
1026 *
1027 * Notice:
1028 * Interrupts are disabled by the caller (AdwISR() function), and will be
1029 * enabled at the end of the caller.
1030 */
1031 static void
1032 adw_isr_callback(ADW_SOFTC *sc, ADW_SCSI_REQ_Q *scsiq)
1033 {
1034 bus_dma_tag_t dmat = sc->sc_dmat;
1035 ADW_CCB *ccb;
1036 struct scsipi_xfer *xs;
1037 struct scsi_sense_data *s1, *s2;
1038
1039
1040 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr);
1041
1042 callout_stop(&ccb->xs->xs_callout);
1043
1044 xs = ccb->xs;
1045
1046 /*
1047 * If we were a data transfer, unload the map that described
1048 * the data buffer.
1049 */
1050 if (xs->datalen) {
1051 bus_dmamap_sync(dmat, ccb->dmamap_xfer, 0,
1052 ccb->dmamap_xfer->dm_mapsize,
1053 (xs->xs_control & XS_CTL_DATA_IN) ?
1054 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1055 bus_dmamap_unload(dmat, ccb->dmamap_xfer);
1056 }
1057
1058 if ((ccb->flags & CCB_ALLOC) == 0) {
1059 aprint_error_dev(&sc->sc_dev, "exiting ccb not allocated!\n");
1060 Debugger();
1061 return;
1062 }
1063
1064 /*
1065 * 'done_status' contains the command's ending status.
1066 * 'host_status' contains the host adapter status.
1067 * 'scsi_status' contains the scsi peripheral status.
1068 */
1069 if ((scsiq->host_status == QHSTA_NO_ERROR) &&
1070 ((scsiq->done_status == QD_NO_ERROR) ||
1071 (scsiq->done_status == QD_WITH_ERROR))) {
1072 switch (scsiq->scsi_status) {
1073 case SCSI_STATUS_GOOD:
1074 if ((scsiq->cdb[0] == INQUIRY) &&
1075 (scsiq->target_lun == 0)) {
1076 adw_print_info(sc, scsiq->target_id);
1077 }
1078 xs->error = XS_NOERROR;
1079 xs->resid = le32toh(scsiq->data_cnt);
1080 sc->sc_freeze_dev[scsiq->target_id] = 0;
1081 break;
1082
1083 case SCSI_STATUS_CHECK_CONDITION:
1084 case SCSI_STATUS_CMD_TERMINATED:
1085 s1 = &ccb->scsi_sense;
1086 s2 = &xs->sense.scsi_sense;
1087 *s2 = *s1;
1088 xs->error = XS_SENSE;
1089 sc->sc_freeze_dev[scsiq->target_id] = 1;
1090 break;
1091
1092 default:
1093 xs->error = XS_BUSY;
1094 sc->sc_freeze_dev[scsiq->target_id] = 1;
1095 break;
1096 }
1097 } else if (scsiq->done_status == QD_ABORTED_BY_HOST) {
1098 xs->error = XS_DRIVER_STUFFUP;
1099 } else {
1100 switch (scsiq->host_status) {
1101 case QHSTA_M_SEL_TIMEOUT:
1102 xs->error = XS_SELTIMEOUT;
1103 break;
1104
1105 case QHSTA_M_SXFR_OFF_UFLW:
1106 case QHSTA_M_SXFR_OFF_OFLW:
1107 case QHSTA_M_DATA_OVER_RUN:
1108 aprint_error_dev(&sc->sc_dev, "Overrun/Overflow/Underflow condition\n");
1109 xs->error = XS_DRIVER_STUFFUP;
1110 break;
1111
1112 case QHSTA_M_SXFR_DESELECTED:
1113 case QHSTA_M_UNEXPECTED_BUS_FREE:
1114 aprint_error_dev(&sc->sc_dev, "Unexpected BUS free\n");
1115 xs->error = XS_DRIVER_STUFFUP;
1116 break;
1117
1118 case QHSTA_M_SCSI_BUS_RESET:
1119 case QHSTA_M_SCSI_BUS_RESET_UNSOL:
1120 aprint_error_dev(&sc->sc_dev, "BUS Reset\n");
1121 xs->error = XS_DRIVER_STUFFUP;
1122 break;
1123
1124 case QHSTA_M_BUS_DEVICE_RESET:
1125 aprint_error_dev(&sc->sc_dev, "Device Reset\n");
1126 xs->error = XS_DRIVER_STUFFUP;
1127 break;
1128
1129 case QHSTA_M_QUEUE_ABORTED:
1130 aprint_error_dev(&sc->sc_dev, "Queue Aborted\n");
1131 xs->error = XS_DRIVER_STUFFUP;
1132 break;
1133
1134 case QHSTA_M_SXFR_SDMA_ERR:
1135 case QHSTA_M_SXFR_SXFR_PERR:
1136 case QHSTA_M_RDMA_PERR:
1137 /*
1138 * DMA Error. This should *NEVER* happen!
1139 *
1140 * Lets try resetting the bus and reinitialize
1141 * the host adapter.
1142 */
1143 aprint_error_dev(&sc->sc_dev, "DMA Error. Reseting bus\n");
1144 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain);
1145 adw_reset_bus(sc);
1146 xs->error = XS_BUSY;
1147 goto done;
1148
1149 case QHSTA_M_WTM_TIMEOUT:
1150 case QHSTA_M_SXFR_WD_TMO:
1151 /* The SCSI bus hung in a phase */
1152 printf("%s: Watch Dog timer expired. Reseting bus\n",
1153 device_xname(&sc->sc_dev));
1154 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain);
1155 adw_reset_bus(sc);
1156 xs->error = XS_BUSY;
1157 goto done;
1158
1159 case QHSTA_M_SXFR_XFR_PH_ERR:
1160 aprint_error_dev(&sc->sc_dev, "Transfer Error\n");
1161 xs->error = XS_DRIVER_STUFFUP;
1162 break;
1163
1164 case QHSTA_M_BAD_CMPL_STATUS_IN:
1165 /* No command complete after a status message */
1166 printf("%s: Bad Completion Status\n",
1167 device_xname(&sc->sc_dev));
1168 xs->error = XS_DRIVER_STUFFUP;
1169 break;
1170
1171 case QHSTA_M_AUTO_REQ_SENSE_FAIL:
1172 aprint_error_dev(&sc->sc_dev, "Auto Sense Failed\n");
1173 xs->error = XS_DRIVER_STUFFUP;
1174 break;
1175
1176 case QHSTA_M_INVALID_DEVICE:
1177 aprint_error_dev(&sc->sc_dev, "Invalid Device\n");
1178 xs->error = XS_DRIVER_STUFFUP;
1179 break;
1180
1181 case QHSTA_M_NO_AUTO_REQ_SENSE:
1182 /*
1183 * User didn't request sense, but we got a
1184 * check condition.
1185 */
1186 aprint_error_dev(&sc->sc_dev, "Unexpected Check Condition\n");
1187 xs->error = XS_DRIVER_STUFFUP;
1188 break;
1189
1190 case QHSTA_M_SXFR_UNKNOWN_ERROR:
1191 aprint_error_dev(&sc->sc_dev, "Unknown Error\n");
1192 xs->error = XS_DRIVER_STUFFUP;
1193 break;
1194
1195 default:
1196 panic("%s: Unhandled Host Status Error %x",
1197 device_xname(&sc->sc_dev), scsiq->host_status);
1198 }
1199 }
1200
1201 TAILQ_REMOVE(&sc->sc_pending_ccb, ccb, chain);
1202 done: adw_free_ccb(sc, ccb);
1203 scsipi_done(xs);
1204 }
1205
1206
1207 /*
1208 * adw_async_callback() - Adv Library asynchronous event callback function.
1209 */
1210 static void
1211 adw_async_callback(ADW_SOFTC *sc, u_int8_t code)
1212 {
1213 switch (code) {
1214 case ADV_ASYNC_SCSI_BUS_RESET_DET:
1215 /* The firmware detected a SCSI Bus reset. */
1216 printf("%s: SCSI Bus reset detected\n", device_xname(&sc->sc_dev));
1217 break;
1218
1219 case ADV_ASYNC_RDMA_FAILURE:
1220 /*
1221 * Handle RDMA failure by resetting the SCSI Bus and
1222 * possibly the chip if it is unresponsive.
1223 */
1224 printf("%s: RDMA failure. Resetting the SCSI Bus and"
1225 " the adapter\n", device_xname(&sc->sc_dev));
1226 AdwResetSCSIBus(sc);
1227 break;
1228
1229 case ADV_HOST_SCSI_BUS_RESET:
1230 /* Host generated SCSI bus reset occurred. */
1231 printf("%s: Host generated SCSI bus reset occurred\n",
1232 device_xname(&sc->sc_dev));
1233 break;
1234
1235 case ADV_ASYNC_CARRIER_READY_FAILURE:
1236 /* Carrier Ready failure. */
1237 printf("%s: Carrier Ready failure!\n", device_xname(&sc->sc_dev));
1238 break;
1239
1240 default:
1241 break;
1242 }
1243 }
NetBSD on the FriendlyARM MINI2440