sys/dev/ic/ahareg.h

   1 /*      $NetBSD: ahareg.h,v 1.14 2008/04/28 20:23:49 martin Exp $       */
   2
   3 /*-
   4  * Copyright (c) 1997-1999 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
   9  * Simulation Facility, NASA Ames Research Center.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30  * POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 /*
  34  * Originally written by Julian Elischer (julian@tfs.com)
  35  * for TRW Financial Systems for use under the MACH(2.5) operating system.
  36  *
  37  * TRW Financial Systems, in accordance with their agreement with Carnegie
  38  * Mellon University, makes this software available to CMU to distribute
  39  * or use in any manner that they see fit as long as this message is kept with
  40  * the software. For this reason TFS also grants any other persons or
  41  * organisations permission to use or modify this software.
  42  *
  43  * TFS supplies this software to be publicly redistributed
  44  * on the understanding that TFS is not responsible for the correct
  45  * functioning of this software in any circumstances.
  46  */
  47
  48 typedef u_int8_t physaddr[3];
  49 typedef u_int8_t physlen[3];
  50 #define ltophys _lto3b
  51 #define phystol _3btol
  52
  53 /*
  54  * I/O port offsets
  55  */
  56 #define AHA_CTRL_PORT           0       /* control (wo) */
  57 #define AHA_STAT_PORT           0       /* status (ro) */
  58 #define AHA_CMD_PORT            1       /* command (wo) */
  59 #define AHA_DATA_PORT           1       /* data (ro) */
  60 #define AHA_INTR_PORT           2       /* interrupt status (ro) */
  61
  62 /*
  63  * AHA_CTRL bits
  64  */
  65 #define AHA_CTRL_HRST           0x80    /* Hardware reset */
  66 #define AHA_CTRL_SRST           0x40    /* Software reset */
  67 #define AHA_CTRL_IRST           0x20    /* Interrupt reset */
  68 #define AHA_CTRL_SCRST          0x10    /* SCSI bus reset */
  69
  70 /*
  71  * AHA_STAT bits
  72  */
  73 #define AHA_STAT_STST           0x80    /* Self test in Progress */
  74 #define AHA_STAT_DIAGF          0x40    /* Diagnostic Failure */
  75 #define AHA_STAT_INIT           0x20    /* Mbx Init required */
  76 #define AHA_STAT_IDLE           0x10    /* Host Adapter Idle */
  77 #define AHA_STAT_CDF            0x08    /* cmd/data out port full */
  78 #define AHA_STAT_DF             0x04    /* Data in port full */
  79 #define AHA_STAT_RSVD           0x02    /* Unused */
  80 #define AHA_STAT_INVDCMD        0x01    /* Invalid command */
  81
  82 /*
  83  * AHA_CMD opcodes
  84  */
  85 #define AHA_NOP                 0x00    /* No operation */
  86 #define AHA_MBX_INIT            0x01    /* Mbx initialization */
  87 #define AHA_START_SCSI          0x02    /* start scsi command */
  88 #define AHA_INQUIRE_REVISION    0x04    /* Adapter Inquiry */
  89 #define AHA_MBO_INTR_EN         0x05    /* Enable MBO available interrupt */
  90 #if 0
  91 #define AHA_SEL_TIMEOUT_SET     0x06    /* set selection time-out */
  92 #define AHA_BUS_ON_TIME_SET     0x07    /* set bus-on time */
  93 #define AHA_BUS_OFF_TIME_SET    0x08    /* set bus-off time */
  94 #define AHA_SPEED_SET           0x09    /* set transfer speed */
  95 #endif
  96 #define AHA_INQUIRE_DEVICES     0x0a    /* return installed devices 0-7 */
  97 #define AHA_INQUIRE_CONFIG      0x0b    /* return configuration data */
  98 #define AHA_TARGET_EN           0x0c    /* enable target mode */
  99 #define AHA_INQUIRE_SETUP       0x0d    /* return setup data */
 100 #define AHA_ECHO                0x1e    /* Echo command data */
 101 #define AHA_INQUIRE_DEVICES_2   0x23    /* return installed devices 8-15 */
 102 #define AHA_EXT_BIOS            0x28    /* return extended bios info */
 103 #define AHA_MBX_ENABLE          0x29    /* enable mail box interface */
 104
 105 /*
 106  * AHA_INTR bits
 107  */
 108 #define AHA_INTR_ANYINTR        0x80    /* Any interrupt */
 109 #define AHA_INTR_RSVD           0x70    /* unused bits */
 110 #define AHA_INTR_SCRD           0x08    /* SCSI reset detected */
 111 #define AHA_INTR_HACC           0x04    /* Command complete */
 112 #define AHA_INTR_MBOA           0x02    /* MBX out empty */
 113 #define AHA_INTR_MBIF           0x01    /* MBX in full */
 114
 115 /*
 116  * AHA Board IDs
 117  */
 118 #define BOARD_1540_16HEAD_BIOS  0x00
 119 #define BOARD_1540_64HEAD_BIOS  0x30
 120 #define BOARD_1540              0x31
 121 #define BOARD_1542              0x41    /* aha-1540/1542 w/64-h bios */
 122 #define BOARD_1640              0x42    /* aha-1640 */
 123 #define BOARD_1740              0x43    /* aha-1740A/1742A/1744 */
 124 #define BOARD_1542C             0x44    /* aha-1542C */
 125 #define BOARD_1542CF            0x45    /* aha-1542CF */
 126 #define BOARD_1542CP            0x46    /* aha-1542CP, plug and play */
 127
 128 struct aha_mbx_out {
 129         u_char cmd;
 130         physaddr ccb_addr;
 131 };
 132
 133 struct aha_mbx_in {
 134         u_char stat;
 135         physaddr ccb_addr;
 136 };
 137
 138 /*
 139  * mbo.cmd values
 140  */
 141 #define AHA_MBO_FREE    0x0     /* MBO entry is free */
 142 #define AHA_MBO_START   0x1     /* MBO activate entry */
 143 #define AHA_MBO_ABORT   0x2     /* MBO abort entry */
 144
 145 /*
 146  * mbi.stat values
 147  */
 148 #define AHA_MBI_FREE    0x0     /* MBI entry is free */
 149 #define AHA_MBI_OK      0x1     /* completed without error */
 150 #define AHA_MBI_ABORT   0x2     /* aborted ccb */
 151 #define AHA_MBI_UNKNOWN 0x3     /* Tried to abort invalid CCB */
 152 #define AHA_MBI_ERROR   0x4     /* Completed with error */
 153
 154 /* FOR OLD VERSIONS OF THE !%$@ this may have to be 16 (yuk) */
 155 #define AHA_NSEG        17      /* Number of scatter gather segments <= 16 */
 156                                 /* allow 64 K i/o (min) */
 157
 158 struct aha_scat_gath {
 159         physlen seg_len;
 160         physaddr seg_addr;
 161 };
 162
 163 struct aha_ccb {
 164         u_char opcode;
 165         u_char lun:3;
 166         u_char data_in:1;       /* must be 0 */
 167         u_char data_out:1;      /* must be 0 */
 168         u_char target:3;
 169         u_char scsi_cmd_length;
 170         u_char req_sense_length;
 171         physlen data_length;
 172         physaddr data_addr;
 173         physaddr link_addr;
 174         u_char link_id;
 175         u_char host_stat;
 176         u_char target_stat;
 177         u_char reserved[2];
 178         u_char scsi_cmd[12];
 179         struct scsi_sense_data scsi_sense;
 180         struct aha_scat_gath scat_gath[AHA_NSEG];
 181         /*----------------------------------------------------------------*/
 182         TAILQ_ENTRY(aha_ccb) chain;
 183         struct aha_ccb *nexthash;
 184         u_long hashkey;
 185         struct scsipi_xfer *xs;         /* the scsipi_xfer for this cmd */
 186         int flags;
 187 #define CCB_ALLOC       0x01
 188 #define CCB_ABORT       0x02
 189 #ifdef AHADIAG
 190 #define CCB_SENDING     0x04
 191 #endif
 192         int timeout;
 193
 194         /*
 195          * This DMA map maps the buffer involved in the transfer.
 196          * Its contents are loaded into "scat_gath" above.
 197          */
 198         bus_dmamap_t    dmamap_xfer;
 199 };
 200
 201 /*
 202  * opcode fields
 203  */
 204 #define AHA_INITIATOR_CCB       0x00    /* SCSI Initiator CCB */
 205 #define AHA_TARGET_CCB          0x01    /* SCSI Target CCB */
 206 #define AHA_INIT_SCAT_GATH_CCB  0x02    /* SCSI Initiator with scatter gather */
 207 #define AHA_RESET_CCB           0x81    /* SCSI Bus reset */
 208
 209 /*
 210  * aha_ccb.host_stat values
 211  */
 212 #define AHA_OK          0x00    /* cmd ok */
 213 #define AHA_LINK_OK     0x0a    /* Link cmd ok */
 214 #define AHA_LINK_IT     0x0b    /* Link cmd ok + int */
 215 #define AHA_SEL_TIMEOUT 0x11    /* Selection time out */
 216 #define AHA_OVER_UNDER  0x12    /* Data over/under run */
 217 #define AHA_BUS_FREE    0x13    /* Bus dropped at unexpected time */
 218 #define AHA_INV_BUS     0x14    /* Invalid bus phase/sequence */
 219 #define AHA_BAD_MBO     0x15    /* Incorrect MBO cmd */
 220 #define AHA_BAD_CCB     0x16    /* Incorrect ccb opcode */
 221 #define AHA_BAD_LINK    0x17    /* Not same values of LUN for links */
 222 #define AHA_INV_TARGET  0x18    /* Invalid target direction */
 223 #define AHA_CCB_DUP     0x19    /* Duplicate CCB received */
 224 #define AHA_INV_CCB     0x1a    /* Invalid CCB or segment list */
 225
 226 struct aha_revision {
 227         struct {
 228                 u_char  opcode;
 229         } cmd;
 230         struct {
 231                 u_char  boardid;        /* type of board */
 232                                         /* 0x31 = AHA-1540 */
 233                                         /* 0x41 = AHA-1540A/1542A/1542B */
 234                                         /* 0x42 = AHA-1640 */
 235                                         /* 0x43 = AHA-1542C */
 236                                         /* 0x44 = AHA-1542CF */
 237                                         /* 0x45 = AHA-1542CF, BIOS v2.01 */
 238                                         /* 0x46 = AHA-1542CP */
 239                 u_char  spec_opts;      /* special options ID */
 240                                         /* 0x41 = Board is standard model */
 241                 u_char  revision_1;     /* firmware revision [0-9A-Z] */
 242                 u_char  revision_2;     /* firmware revision [0-9A-Z] */
 243         } reply;
 244 };
 245
 246 struct aha_extbios {
 247         struct {
 248                 u_char  opcode;
 249         } cmd;
 250         struct {
 251                 u_char  flags;          /* Bit 3 == 1 extended bios enabled */
 252                 u_char  mailboxlock;    /* mail box lock code to unlock it */
 253         } reply;
 254 };
 255
 256 struct aha_toggle {
 257         struct {
 258                 u_char  opcode;
 259                 u_char  enable;
 260         } cmd;
 261 };
 262
 263 struct aha_config {
 264         struct {
 265                 u_char  opcode;
 266         } cmd;
 267         struct {
 268                 u_char  chan;
 269                 u_char  intr;
 270                 u_char  scsi_dev:3;
 271                 u_char  :5;
 272         } reply;
 273 };
 274
 275 struct aha_mailbox {
 276         struct {
 277                 u_char  opcode;
 278                 u_char  nmbx;
 279                 physaddr addr;
 280         } cmd;
 281 };
 282
 283 struct aha_unlock {
 284         struct {
 285                 u_char  opcode;
 286                 u_char  junk;
 287                 u_char  magic;
 288         } cmd;
 289 };
 290
 291 struct aha_devices {
 292         struct {
 293                 u_char  opcode;
 294         } cmd;
 295         struct {
 296                 u_char  lun_map[8];
 297         } reply;
 298 };
 299
 300 struct aha_setup {
 301         struct {
 302                 u_char  opcode;
 303                 u_char  len;
 304         } cmd;
 305         struct {
 306                 u_char  sync_neg:1;
 307                 u_char  parity:1;
 308                 u_char  :6;
 309                 u_char  speed;
 310                 u_char  bus_on;
 311                 u_char  bus_off;
 312                 u_char  num_mbx;
 313                 u_char  mbx[3];
 314                 struct {
 315                         u_char  offset:4;
 316                         u_char  period:3;
 317                         u_char  valid:1;
 318                 } sync[8];
 319                 u_char  disc_sts;
 320         } reply;
 321 };
 322
 323 #define INT9    0x01
 324 #define INT10   0x02
 325 #define INT11   0x04
 326 #define INT12   0x08
 327 #define INT14   0x20
 328 #define INT15   0x40
 329
 330 #define EISADMA 0x00
 331 #define CHAN0   0x01
 332 #define CHAN5   0x20
 333 #define CHAN6   0x40
 334 #define CHAN7   0x80