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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / ic / ahcisata_core.c
blob5129a9da017b8ad81b3a006a3be543a62702c4d8
1 /* $NetBSD: ahcisata_core.c,v 1.21 2009/10/19 18:41:12 bouyer Exp $ */
2
3 /*
4 * Copyright (c) 2006 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.21 2009/10/19 18:41:12 bouyer Exp $");
30
31 #include <sys/types.h>
32 #include <sys/malloc.h>
33 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
36 #include <sys/disklabel.h>
37 #include <sys/proc.h>
38 #include <sys/buf.h>
39
40 #include <uvm/uvm_extern.h>
41
42 #include <dev/ic/wdcreg.h>
43 #include <dev/ata/atareg.h>
44 #include <dev/ata/satavar.h>
45 #include <dev/ata/satareg.h>
46 #include <dev/ata/satafisreg.h>
47 #include <dev/ata/satafisvar.h>
48 #include <dev/ic/ahcisatavar.h>
49
50 #include <dev/scsipi/scsi_all.h> /* for SCSI status */
51
52 #include "atapibus.h"
53
54 #ifdef AHCI_DEBUG
55 int ahcidebug_mask = 0x0;
56 #endif
57
58 void ahci_probe_drive(struct ata_channel *);
59 void ahci_setup_channel(struct ata_channel *);
60
61 int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *);
62 void ahci_reset_drive(struct ata_drive_datas *, int);
63 void ahci_reset_channel(struct ata_channel *, int);
64 int ahci_exec_command(struct ata_drive_datas *, struct ata_command *);
65 int ahci_ata_addref(struct ata_drive_datas *);
66 void ahci_ata_delref(struct ata_drive_datas *);
67 void ahci_killpending(struct ata_drive_datas *);
68
69 void ahci_cmd_start(struct ata_channel *, struct ata_xfer *);
70 int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int);
71 void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int);
72 void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ;
73 void ahci_bio_start(struct ata_channel *, struct ata_xfer *);
74 int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int);
75 void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ;
76 void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int);
77 void ahci_channel_start(struct ahci_softc *, struct ata_channel *);
78 void ahci_timeout(void *);
79 int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int);
80
81 #if NATAPIBUS > 0
82 void ahci_atapibus_attach(struct atabus_softc *);
83 void ahci_atapi_kill_pending(struct scsipi_periph *);
84 void ahci_atapi_minphys(struct buf *);
85 void ahci_atapi_scsipi_request(struct scsipi_channel *,
86 scsipi_adapter_req_t, void *);
87 void ahci_atapi_start(struct ata_channel *, struct ata_xfer *);
88 int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int);
89 void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int);
90 void ahci_atapi_probe_device(struct atapibus_softc *, int);
91
92 static const struct scsipi_bustype ahci_atapi_bustype = {
93 SCSIPI_BUSTYPE_ATAPI,
94 atapi_scsipi_cmd,
95 atapi_interpret_sense,
96 atapi_print_addr,
97 ahci_atapi_kill_pending,
98 };
99 #endif /* NATAPIBUS */
100
101 #define ATA_DELAY 10000 /* 10s for a drive I/O */
102
103 const struct ata_bustype ahci_ata_bustype = {
104 SCSIPI_BUSTYPE_ATA,
105 ahci_ata_bio,
106 ahci_reset_drive,
107 ahci_reset_channel,
108 ahci_exec_command,
109 ata_get_params,
110 ahci_ata_addref,
111 ahci_ata_delref,
112 ahci_killpending
113 };
114
115 void ahci_intr_port(struct ahci_softc *, struct ahci_channel *);
116
117 static void ahci_setup_port(struct ahci_softc *sc, int i);
118
119 int
120 ahci_reset(struct ahci_softc *sc)
121 {
122 int i;
123
124 /* reset controller */
125 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR);
126 /* wait up to 1s for reset to complete */
127 for (i = 0; i < 1000; i++) {
128 delay(1000);
129 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0)
130 break;
131 }
132 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) {
133 aprint_error("%s: reset failed\n", AHCINAME(sc));
134 return -1;
135 }
136 /* enable ahci mode */
137 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE);
138 return 0;
139 }
140
141 void
142 ahci_setup_ports(struct ahci_softc *sc)
143 {
144 u_int32_t ahci_ports;
145 int i, port;
146
147 ahci_ports = AHCI_READ(sc, AHCI_PI);
148 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
149 if ((ahci_ports & (1 << i)) == 0)
150 continue;
151 if (port >= sc->sc_atac.atac_nchannels) {
152 aprint_error("%s: more ports than announced\n",
153 AHCINAME(sc));
154 break;
155 }
156 ahci_setup_port(sc, i);
157 }
158 }
159
160 void
161 ahci_reprobe_drives(struct ahci_softc *sc)
162 {
163 u_int32_t ahci_ports;
164 int i, port;
165 struct ahci_channel *achp;
166 struct ata_channel *chp;
167
168 ahci_ports = AHCI_READ(sc, AHCI_PI);
169 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
170 if ((ahci_ports & (1 << i)) == 0)
171 continue;
172 if (port >= sc->sc_atac.atac_nchannels) {
173 aprint_error("%s: more ports than announced\n",
174 AHCINAME(sc));
175 break;
176 }
177 achp = &sc->sc_channels[i];
178 chp = &achp->ata_channel;
179
180 ahci_probe_drive(chp);
181 }
182 }
183
184 static void
185 ahci_setup_port(struct ahci_softc *sc, int i)
186 {
187 struct ahci_channel *achp;
188
189 achp = &sc->sc_channels[i];
190
191 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh);
192 AHCI_WRITE(sc, AHCI_P_CLBU(i), 0);
193 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis);
194 AHCI_WRITE(sc, AHCI_P_FBU(i), 0);
195 }
196
197 void
198 ahci_enable_intrs(struct ahci_softc *sc)
199 {
200
201 /* clear interrupts */
202 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS));
203 /* enable interrupts */
204 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
205 }
206
207 void
208 ahci_attach(struct ahci_softc *sc)
209 {
210 u_int32_t ahci_cap, ahci_rev, ahci_ports;
211 int i, j, port;
212 struct ahci_channel *achp;
213 struct ata_channel *chp;
214 int error;
215 bus_dma_segment_t seg;
216 int rseg;
217 int dmasize;
218 void *cmdhp;
219 void *cmdtblp;
220
221 if (ahci_reset(sc) != 0)
222 return;
223
224 ahci_cap = AHCI_READ(sc, AHCI_CAP);
225 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1;
226 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1;
227 ahci_rev = AHCI_READ(sc, AHCI_VS);
228 aprint_normal("%s: AHCI revision ", AHCINAME(sc));
229 switch(ahci_rev) {
230 case AHCI_VS_10:
231 aprint_normal("1.0");
232 break;
233 case AHCI_VS_11:
234 aprint_normal("1.1");
235 break;
236 case AHCI_VS_12:
237 aprint_normal("1.2");
238 break;
239 default:
240 aprint_normal("0x%x", ahci_rev);
241 break;
242 }
243
244 aprint_normal(", %d ports, %d command slots, features 0x%x\n",
245 sc->sc_atac.atac_nchannels, sc->sc_ncmds,
246 ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS));
247 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA;
248 sc->sc_atac.atac_cap |= sc->sc_atac_capflags;
249 sc->sc_atac.atac_pio_cap = 4;
250 sc->sc_atac.atac_dma_cap = 2;
251 sc->sc_atac.atac_udma_cap = 6;
252 sc->sc_atac.atac_channels = sc->sc_chanarray;
253 sc->sc_atac.atac_probe = ahci_probe_drive;
254 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype;
255 sc->sc_atac.atac_set_modes = ahci_setup_channel;
256 #if NATAPIBUS > 0
257 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach;
258 #endif
259
260 dmasize =
261 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels;
262 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0,
263 &seg, 1, &rseg, BUS_DMA_NOWAIT);
264 if (error) {
265 aprint_error("%s: unable to allocate command header memory"
266 ", error=%d\n", AHCINAME(sc), error);
267 return;
268 }
269 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize,
270 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
271 if (error) {
272 aprint_error("%s: unable to map command header memory"
273 ", error=%d\n", AHCINAME(sc), error);
274 return;
275 }
276 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0,
277 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd);
278 if (error) {
279 aprint_error("%s: unable to create command header map"
280 ", error=%d\n", AHCINAME(sc), error);
281 return;
282 }
283 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd,
284 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT);
285 if (error) {
286 aprint_error("%s: unable to load command header map"
287 ", error=%d\n", AHCINAME(sc), error);
288 return;
289 }
290 sc->sc_cmd_hdr = cmdhp;
291
292 ahci_enable_intrs(sc);
293
294 ahci_ports = AHCI_READ(sc, AHCI_PI);
295 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) {
296 if ((ahci_ports & (1 << i)) == 0)
297 continue;
298 if (port >= sc->sc_atac.atac_nchannels) {
299 aprint_error("%s: more ports than announced\n",
300 AHCINAME(sc));
301 break;
302 }
303 achp = &sc->sc_channels[i];
304 chp = (struct ata_channel *)achp;
305 sc->sc_chanarray[i] = chp;
306 chp->ch_channel = i;
307 chp->ch_atac = &sc->sc_atac;
308 chp->ch_queue = malloc(sizeof(struct ata_queue),
309 M_DEVBUF, M_NOWAIT);
310 if (chp->ch_queue == NULL) {
311 aprint_error("%s port %d: can't allocate memory for "
312 "command queue", AHCINAME(sc), i);
313 break;
314 }
315 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds;
316 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0,
317 &seg, 1, &rseg, BUS_DMA_NOWAIT);
318 if (error) {
319 aprint_error("%s: unable to allocate command table "
320 "memory, error=%d\n", AHCINAME(sc), error);
321 break;
322 }
323 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize,
324 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
325 if (error) {
326 aprint_error("%s: unable to map command table memory"
327 ", error=%d\n", AHCINAME(sc), error);
328 break;
329 }
330 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0,
331 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld);
332 if (error) {
333 aprint_error("%s: unable to create command table map"
334 ", error=%d\n", AHCINAME(sc), error);
335 break;
336 }
337 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld,
338 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT);
339 if (error) {
340 aprint_error("%s: unable to load command table map"
341 ", error=%d\n", AHCINAME(sc), error);
342 break;
343 }
344 achp->ahcic_cmdh = (struct ahci_cmd_header *)
345 ((char *)cmdhp + AHCI_CMDH_SIZE * port);
346 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr +
347 AHCI_CMDH_SIZE * port;
348 achp->ahcic_rfis = (struct ahci_r_fis *)
349 ((char *)cmdhp +
350 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels +
351 AHCI_RFIS_SIZE * port);
352 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr +
353 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels +
354 AHCI_RFIS_SIZE * port;
355 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%x) rfis %p (0x%x)\n", i,
356 achp->ahcic_cmdh, (u_int)achp->ahcic_bus_cmdh,
357 achp->ahcic_rfis, (u_int)achp->ahcic_bus_rfis),
358 DEBUG_PROBE);
359
360 for (j = 0; j < sc->sc_ncmds; j++) {
361 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *)
362 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j);
363 achp->ahcic_bus_cmd_tbl[j] =
364 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr +
365 AHCI_CMDTBL_SIZE * j;
366 achp->ahcic_cmdh[j].cmdh_cmdtba =
367 htole32(achp->ahcic_bus_cmd_tbl[j]);
368 achp->ahcic_cmdh[j].cmdh_cmdtbau = htole32(0);
369 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%x)\n", i, j,
370 achp->ahcic_cmd_tbl[j],
371 (u_int)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE);
372 /* The xfer DMA map */
373 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS,
374 AHCI_NPRD, 0x400000 /* 4MB */, 0,
375 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
376 &achp->ahcic_datad[j]);
377 if (error) {
378 aprint_error("%s: couldn't alloc xfer DMA map, "
379 "error=%d\n", AHCINAME(sc), error);
380 goto end;
381 }
382 }
383 ahci_setup_port(sc, i);
384 chp->ch_ndrive = 1;
385 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
386 AHCI_P_SSTS(i), 4, &achp->ahcic_sstatus) != 0) {
387 aprint_error("%s: couldn't map channel %d "
388 "sata_status regs\n", AHCINAME(sc), i);
389 break;
390 }
391 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
392 AHCI_P_SCTL(i), 4, &achp->ahcic_scontrol) != 0) {
393 aprint_error("%s: couldn't map channel %d "
394 "sata_control regs\n", AHCINAME(sc), i);
395 break;
396 }
397 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih,
398 AHCI_P_SERR(i), 4, &achp->ahcic_serror) != 0) {
399 aprint_error("%s: couldn't map channel %d "
400 "sata_error regs\n", AHCINAME(sc), i);
401 break;
402 }
403 ata_channel_attach(chp);
404 port++;
405 end:
406 continue;
407 }
408 }
409
410 int
411 ahci_intr(void *v)
412 {
413 struct ahci_softc *sc = v;
414 u_int32_t is;
415 int i, r = 0;
416
417 while ((is = AHCI_READ(sc, AHCI_IS))) {
418 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is),
419 DEBUG_INTR);
420 r = 1;
421 AHCI_WRITE(sc, AHCI_IS, is);
422 for (i = 0; i < AHCI_MAX_PORTS; i++)
423 if (is & (1 << i))
424 ahci_intr_port(sc, &sc->sc_channels[i]);
425 }
426 return r;
427 }
428
429 void
430 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp)
431 {
432 u_int32_t is, tfd;
433 struct ata_channel *chp = &achp->ata_channel;
434 struct ata_xfer *xfer = chp->ch_queue->active_xfer;
435 int slot;
436
437 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel));
438 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is);
439 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc),
440 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
441 DEBUG_INTR);
442
443 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS |
444 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) {
445 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))
446 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT;
447 if ((achp->ahcic_cmds_active & (1 << slot)) == 0)
448 return;
449 /* stop channel */
450 ahci_channel_stop(sc, chp, 0);
451 if (slot != 0) {
452 printf("ahci_intr_port: slot %d\n", slot);
453 panic("ahci_intr_port");
454 }
455 if (is & AHCI_P_IX_TFES) {
456 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
457 chp->ch_error =
458 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT;
459 chp->ch_status = (tfd & 0xff);
460 } else {
461 /* emulate a CRC error */
462 chp->ch_error = WDCE_CRC;
463 chp->ch_status = WDCS_ERR;
464 }
465 xfer->c_intr(chp, xfer, is);
466 /* if channel has not been restarted, do it now */
467 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR)
468 == 0)
469 ahci_channel_start(sc, chp);
470 } else {
471 slot = 0; /* XXX */
472 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel));
473 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n",
474 chp->ch_channel, is, achp->ahcic_cmds_active,
475 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR);
476 if ((achp->ahcic_cmds_active & (1 << slot)) == 0)
477 return;
478 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot))
479 == 0) {
480 xfer->c_intr(chp, xfer, 0);
481 }
482 }
483 }
484
485 void
486 ahci_reset_drive(struct ata_drive_datas *drvp, int flags)
487 {
488 struct ata_channel *chp = drvp->chnl_softc;
489 ata_reset_channel(chp, flags);
490 return;
491 }
492
493 void
494 ahci_reset_channel(struct ata_channel *chp, int flags)
495 {
496 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
497 struct ahci_channel *achp = (struct ahci_channel *)chp;
498 int i, tfd;
499
500 ahci_channel_stop(sc, chp, flags);
501 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol,
502 achp->ahcic_sstatus) != SStatus_DET_DEV) {
503 printf("%s: port reset failed\n", AHCINAME(sc));
504 /* XXX and then ? */
505 }
506 if (chp->ch_queue->active_xfer) {
507 chp->ch_queue->active_xfer->c_kill_xfer(chp,
508 chp->ch_queue->active_xfer, KILL_RESET);
509 }
510 ahci_channel_start(sc, chp);
511 /* wait 31s for BSY to clear */
512 for (i = 0; i <3100; i++) {
513 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
514 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT)
515 & WDCS_BSY) == 0)
516 break;
517 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10));
518 }
519 if (i == 1500)
520 aprint_error("%s: BSY never cleared, TD 0x%x\n",
521 AHCINAME(sc), tfd);
522 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10),
523 DEBUG_PROBE);
524 /* clear port interrupt register */
525 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff);
526
527 return;
528 }
529
530 int
531 ahci_ata_addref(struct ata_drive_datas *drvp)
532 {
533 return 0;
534 }
535
536 void
537 ahci_ata_delref(struct ata_drive_datas *drvp)
538 {
539 return;
540 }
541
542 void
543 ahci_killpending(struct ata_drive_datas *drvp)
544 {
545 return;
546 }
547
548 void
549 ahci_probe_drive(struct ata_channel *chp)
550 {
551 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
552 struct ahci_channel *achp = (struct ahci_channel *)chp;
553 int i, s;
554 u_int32_t sig;
555
556 /* XXX This should be done by other code. */
557 for (i = 0; i < chp->ch_ndrive; i++) {
558 chp->ch_drive[i].chnl_softc = chp;
559 chp->ch_drive[i].drive = i;
560 }
561
562 /* bring interface up, accept FISs, power up and spin up device */
563 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
564 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE |
565 AHCI_P_CMD_POD | AHCI_P_CMD_SUD);
566 /* reset the PHY and bring online */
567 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol,
568 achp->ahcic_sstatus)) {
569 case SStatus_DET_DEV:
570 /* clear SErrors and start operations */
571 ahci_channel_start(sc, chp);
572 /* wait 31s for BSY to clear */
573 for (i = 0; i <3100; i++) {
574 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel));
575 if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT)
576 & WDCS_BSY) == 0)
577 break;
578 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10));
579 }
580 if (i == 1500)
581 aprint_error("%s: BSY never cleared, TD 0x%x\n",
582 AHCINAME(sc), sig);
583 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10),
584 DEBUG_PROBE);
585 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel));
586 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n",
587 AHCINAME(sc), chp->ch_channel, sig,
588 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE);
589 /*
590 * scnt and sn are supposed to be 0x1 for ATAPI, but in some
591 * cases we get wrong values here, so ignore it.
592 */
593 s = splbio();
594 if ((sig & 0xffff0000) == 0xeb140000) {
595 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI;
596 } else
597 chp->ch_drive[0].drive_flags |= DRIVE_ATA;
598 splx(s);
599 /* enable interrupts */
600 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel),
601 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS |
602 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS |
603 AHCI_P_IX_DHRS);
604 /* wait 500ms before actually starting operations */
605 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500));
606 break;
607
608 default:
609 break;
610 }
611 }
612
613 void
614 ahci_setup_channel(struct ata_channel *chp)
615 {
616 return;
617 }
618
619 int
620 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c)
621 {
622 struct ata_channel *chp = drvp->chnl_softc;
623 struct ata_xfer *xfer;
624 int ret;
625 int s;
626
627 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
628 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n",
629 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
630 DEBUG_XFERS);
631 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP :
632 ATAXF_NOSLEEP);
633 if (xfer == NULL) {
634 return ATACMD_TRY_AGAIN;
635 }
636 if (ata_c->flags & AT_POLL)
637 xfer->c_flags |= C_POLL;
638 if (ata_c->flags & AT_WAIT)
639 xfer->c_flags |= C_WAIT;
640 xfer->c_drive = drvp->drive;
641 xfer->c_databuf = ata_c->data;
642 xfer->c_bcount = ata_c->bcount;
643 xfer->c_cmd = ata_c;
644 xfer->c_start = ahci_cmd_start;
645 xfer->c_intr = ahci_cmd_complete;
646 xfer->c_kill_xfer = ahci_cmd_kill_xfer;
647 s = splbio();
648 ata_exec_xfer(chp, xfer);
649 #ifdef DIAGNOSTIC
650 if ((ata_c->flags & AT_POLL) != 0 &&
651 (ata_c->flags & AT_DONE) == 0)
652 panic("ahci_exec_command: polled command not done");
653 #endif
654 if (ata_c->flags & AT_DONE) {
655 ret = ATACMD_COMPLETE;
656 } else {
657 if (ata_c->flags & AT_WAIT) {
658 while ((ata_c->flags & AT_DONE) == 0) {
659 tsleep(ata_c, PRIBIO, "ahcicmd", 0);
660 }
661 ret = ATACMD_COMPLETE;
662 } else {
663 ret = ATACMD_QUEUED;
664 }
665 }
666 splx(s);
667 return ret;
668 }
669
670 void
671 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer)
672 {
673 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
674 struct ahci_channel *achp = (struct ahci_channel *)chp;
675 struct ata_command *ata_c = xfer->c_cmd;
676 int slot = 0 /* XXX slot */;
677 struct ahci_cmd_tbl *cmd_tbl;
678 struct ahci_cmd_header *cmd_h;
679 int i;
680 int channel = chp->ch_channel;
681
682 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n",
683 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS);
684
685 cmd_tbl = achp->ahcic_cmd_tbl[slot];
686 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
687 cmd_tbl), DEBUG_XFERS);
688
689 satafis_rhd_construct_cmd(ata_c, cmd_tbl->cmdt_cfis);
690
691 cmd_h = &achp->ahcic_cmdh[slot];
692 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
693 chp->ch_channel, cmd_h), DEBUG_XFERS);
694 if (ahci_dma_setup(chp, slot,
695 (ata_c->flags & (AT_READ|AT_WRITE)) ? ata_c->data : NULL,
696 ata_c->bcount,
697 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) {
698 ata_c->flags |= AT_DF;
699 ahci_cmd_complete(chp, xfer, slot);
700 return;
701 }
702 cmd_h->cmdh_flags = htole16(
703 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) |
704 RHD_FISLEN / 4);
705 cmd_h->cmdh_prdbc = 0;
706 AHCI_CMDH_SYNC(sc, achp, slot,
707 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
708
709 if (ata_c->flags & AT_POLL) {
710 /* polled command, disable interrupts */
711 AHCI_WRITE(sc, AHCI_GHC,
712 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
713 }
714 chp->ch_flags |= ATACH_IRQ_WAIT;
715 chp->ch_status = 0;
716 /* start command */
717 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot);
718 /* and says we started this command */
719 achp->ahcic_cmds_active |= 1 << slot;
720
721 if ((ata_c->flags & AT_POLL) == 0) {
722 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
723 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout),
724 ahci_timeout, chp);
725 return;
726 }
727 /*
728 * Polled command.
729 */
730 for (i = 0; i < ata_c->timeout / 10; i++) {
731 if (ata_c->flags & AT_DONE)
732 break;
733 ahci_intr_port(sc, achp);
734 if (ata_c->flags & AT_WAIT)
735 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10));
736 else
737 delay(10000);
738 }
739 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel,
740 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
741 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)),
742 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)),
743 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))),
744 DEBUG_XFERS);
745 if ((ata_c->flags & AT_DONE) == 0) {
746 ata_c->flags |= AT_TIMEOU;
747 ahci_cmd_complete(chp, xfer, slot);
748 }
749 /* reenable interrupts */
750 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
751 }
752
753 void
754 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
755 {
756 struct ata_command *ata_c = xfer->c_cmd;
757 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel),
758 DEBUG_FUNCS);
759
760 switch (reason) {
761 case KILL_GONE:
762 ata_c->flags |= AT_GONE;
763 break;
764 case KILL_RESET:
765 ata_c->flags |= AT_RESET;
766 break;
767 default:
768 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason);
769 panic("ahci_cmd_kill_xfer");
770 }
771 ahci_cmd_done(chp, xfer, 0 /* XXX slot */);
772 }
773
774 int
775 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is)
776 {
777 int slot = 0; /* XXX slot */
778 struct ata_command *ata_c = xfer->c_cmd;
779 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
780
781 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n",
782 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)),
783 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
784 DEBUG_FUNCS);
785 chp->ch_flags &= ~ATACH_IRQ_WAIT;
786 if (xfer->c_flags & C_TIMEOU) {
787 ata_c->flags |= AT_TIMEOU;
788 } else
789 callout_stop(&chp->ch_callout);
790
791 chp->ch_queue->active_xfer = NULL;
792
793 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) {
794 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE);
795 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN;
796 wakeup(&chp->ch_queue->active_xfer);
797 return 0;
798 }
799 if (is) {
800 ata_c->r_head = 0;
801 ata_c->r_count = 0;
802 ata_c->r_sector = 0;
803 ata_c->r_cyl = 0;
804 if (chp->ch_status & WDCS_BSY) {
805 ata_c->flags |= AT_TIMEOU;
806 } else if (chp->ch_status & WDCS_ERR) {
807 ata_c->r_error = chp->ch_error;
808 ata_c->flags |= AT_ERROR;
809 }
810 }
811 ahci_cmd_done(chp, xfer, slot);
812 return 0;
813 }
814
815 void
816 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot)
817 {
818 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
819 struct ahci_channel *achp = (struct ahci_channel *)chp;
820 struct ata_command *ata_c = xfer->c_cmd;
821
822 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel),
823 DEBUG_FUNCS);
824
825 /* this comamnd is not active any more */
826 achp->ahcic_cmds_active &= ~(1 << slot);
827
828 if (ata_c->flags & (AT_READ|AT_WRITE)) {
829 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
830 achp->ahcic_datad[slot]->dm_mapsize,
831 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD :
832 BUS_DMASYNC_POSTWRITE);
833 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]);
834 }
835
836 AHCI_CMDH_SYNC(sc, achp, slot,
837 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
838
839 ata_c->flags |= AT_DONE;
840 if (achp->ahcic_cmdh[slot].cmdh_prdbc)
841 ata_c->flags |= AT_XFDONE;
842
843 ata_free_xfer(chp, xfer);
844 if (ata_c->flags & AT_WAIT)
845 wakeup(ata_c);
846 else if (ata_c->callback)
847 ata_c->callback(ata_c->callback_arg);
848 atastart(chp);
849 return;
850 }
851
852 int
853 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio)
854 {
855 struct ata_channel *chp = drvp->chnl_softc;
856 struct ata_xfer *xfer;
857
858 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
859 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n",
860 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))),
861 DEBUG_XFERS);
862 xfer = ata_get_xfer(ATAXF_NOSLEEP);
863 if (xfer == NULL) {
864 return ATACMD_TRY_AGAIN;
865 }
866 if (ata_bio->flags & ATA_POLL)
867 xfer->c_flags |= C_POLL;
868 xfer->c_drive = drvp->drive;
869 xfer->c_cmd = ata_bio;
870 xfer->c_databuf = ata_bio->databuf;
871 xfer->c_bcount = ata_bio->bcount;
872 xfer->c_start = ahci_bio_start;
873 xfer->c_intr = ahci_bio_complete;
874 xfer->c_kill_xfer = ahci_bio_kill_xfer;
875 ata_exec_xfer(chp, xfer);
876 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED;
877 }
878
879 void
880 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer)
881 {
882 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
883 struct ahci_channel *achp = (struct ahci_channel *)chp;
884 struct ata_bio *ata_bio = xfer->c_cmd;
885 int slot = 0 /* XXX slot */;
886 struct ahci_cmd_tbl *cmd_tbl;
887 struct ahci_cmd_header *cmd_h;
888 int i;
889 int channel = chp->ch_channel;
890
891 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n",
892 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS);
893
894 cmd_tbl = achp->ahcic_cmd_tbl[slot];
895 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
896 cmd_tbl), DEBUG_XFERS);
897
898 satafis_rhd_construct_bio(xfer, cmd_tbl->cmdt_cfis);
899
900 cmd_h = &achp->ahcic_cmdh[slot];
901 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
902 chp->ch_channel, cmd_h), DEBUG_XFERS);
903 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount,
904 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) {
905 ata_bio->error = ERR_DMA;
906 ata_bio->r_error = 0;
907 ahci_bio_complete(chp, xfer, slot);
908 return;
909 }
910 cmd_h->cmdh_flags = htole16(
911 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) |
912 RHD_FISLEN / 4);
913 cmd_h->cmdh_prdbc = 0;
914 AHCI_CMDH_SYNC(sc, achp, slot,
915 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
916
917 if (xfer->c_flags & C_POLL) {
918 /* polled command, disable interrupts */
919 AHCI_WRITE(sc, AHCI_GHC,
920 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
921 }
922 chp->ch_flags |= ATACH_IRQ_WAIT;
923 chp->ch_status = 0;
924 /* start command */
925 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot);
926 /* and says we started this command */
927 achp->ahcic_cmds_active |= 1 << slot;
928
929 if ((xfer->c_flags & C_POLL) == 0) {
930 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
931 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY),
932 ahci_timeout, chp);
933 return;
934 }
935 /*
936 * Polled command.
937 */
938 for (i = 0; i < ATA_DELAY / 10; i++) {
939 if (ata_bio->flags & ATA_ITSDONE)
940 break;
941 ahci_intr_port(sc, achp);
942 if (ata_bio->flags & ATA_NOSLEEP)
943 delay(10000);
944 else
945 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10));
946 }
947 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel,
948 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
949 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)),
950 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)),
951 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))),
952 DEBUG_XFERS);
953 if ((ata_bio->flags & ATA_ITSDONE) == 0) {
954 ata_bio->error = TIMEOUT;
955 ahci_bio_complete(chp, xfer, slot);
956 }
957 /* reenable interrupts */
958 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
959 }
960
961 void
962 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
963 {
964 int slot = 0; /* XXX slot */
965 int drive = xfer->c_drive;
966 struct ata_bio *ata_bio = xfer->c_cmd;
967 struct ahci_channel *achp = (struct ahci_channel *)chp;
968 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel),
969 DEBUG_FUNCS);
970
971 achp->ahcic_cmds_active &= ~(1 << slot);
972 ata_free_xfer(chp, xfer);
973 ata_bio->flags |= ATA_ITSDONE;
974 switch (reason) {
975 case KILL_GONE:
976 ata_bio->error = ERR_NODEV;
977 break;
978 case KILL_RESET:
979 ata_bio->error = ERR_RESET;
980 break;
981 default:
982 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason);
983 panic("ahci_bio_kill_xfer");
984 }
985 ata_bio->r_error = WDCE_ABRT;
986 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc);
987 }
988
989 int
990 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is)
991 {
992 int slot = 0; /* XXX slot */
993 struct ata_bio *ata_bio = xfer->c_cmd;
994 int drive = xfer->c_drive;
995 struct ahci_channel *achp = (struct ahci_channel *)chp;
996 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
997
998 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel),
999 DEBUG_FUNCS);
1000
1001 achp->ahcic_cmds_active &= ~(1 << slot);
1002 chp->ch_flags &= ~ATACH_IRQ_WAIT;
1003 if (xfer->c_flags & C_TIMEOU) {
1004 ata_bio->error = TIMEOUT;
1005 } else {
1006 callout_stop(&chp->ch_callout);
1007 ata_bio->error = NOERROR;
1008 }
1009
1010 chp->ch_queue->active_xfer = NULL;
1011 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
1012 achp->ahcic_datad[slot]->dm_mapsize,
1013 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD :
1014 BUS_DMASYNC_POSTWRITE);
1015 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]);
1016
1017 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) {
1018 ahci_bio_kill_xfer(chp, xfer, KILL_GONE);
1019 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN;
1020 wakeup(&chp->ch_queue->active_xfer);
1021 return 0;
1022 }
1023 ata_free_xfer(chp, xfer);
1024 ata_bio->flags |= ATA_ITSDONE;
1025 if (chp->ch_status & WDCS_DWF) {
1026 ata_bio->error = ERR_DF;
1027 } else if (chp->ch_status & WDCS_ERR) {
1028 ata_bio->error = ERROR;
1029 ata_bio->r_error = chp->ch_error;
1030 } else if (chp->ch_status & WDCS_CORR)
1031 ata_bio->flags |= ATA_CORR;
1032
1033 AHCI_CMDH_SYNC(sc, achp, slot,
1034 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1035 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld",
1036 ata_bio->bcount), DEBUG_XFERS);
1037 /*
1038 * if it was a write, complete data buffer may have been transfered
1039 * before error detection; in this case don't use cmdh_prdbc
1040 * as it won't reflect what was written to media. Assume nothing
1041 * was transfered and leave bcount as-is.
1042 */
1043 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR)
1044 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc);
1045 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS);
1046 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc);
1047 atastart(chp);
1048 return 0;
1049 }
1050
1051 void
1052 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags)
1053 {
1054 int i;
1055 /* stop channel */
1056 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
1057 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST);
1058 /* wait 1s for channel to stop */
1059 for (i = 0; i <100; i++) {
1060 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR)
1061 == 0)
1062 break;
1063 if (flags & AT_WAIT)
1064 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10));
1065 else
1066 delay(10000);
1067 }
1068 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) {
1069 printf("%s: channel wouldn't stop\n", AHCINAME(sc));
1070 /* XXX controller reset ? */
1071 return;
1072 }
1073 }
1074
1075 void
1076 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp)
1077 {
1078 /* clear error */
1079 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel),
1080 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel)));
1081
1082 /* and start controller */
1083 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
1084 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
1085 AHCI_P_CMD_FRE | AHCI_P_CMD_ST);
1086 }
1087
1088 void
1089 ahci_timeout(void *v)
1090 {
1091 struct ata_channel *chp = (struct ata_channel *)v;
1092 struct ata_xfer *xfer = chp->ch_queue->active_xfer;
1093 int s = splbio();
1094 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR);
1095 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) {
1096 xfer->c_flags |= C_TIMEOU;
1097 xfer->c_intr(chp, xfer, 0);
1098 }
1099 splx(s);
1100 }
1101
1102 int
1103 ahci_dma_setup(struct ata_channel *chp, int slot, void *data,
1104 size_t count, int op)
1105 {
1106 int error, seg;
1107 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1108 struct ahci_channel *achp = (struct ahci_channel *)chp;
1109 struct ahci_cmd_tbl *cmd_tbl;
1110 struct ahci_cmd_header *cmd_h;
1111
1112 cmd_h = &achp->ahcic_cmdh[slot];
1113 cmd_tbl = achp->ahcic_cmd_tbl[slot];
1114
1115 if (data == NULL) {
1116 cmd_h->cmdh_prdtl = 0;
1117 goto end;
1118 }
1119
1120 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot],
1121 data, count, NULL,
1122 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op);
1123 if (error) {
1124 printf("%s port %d: failed to load xfer: %d\n",
1125 AHCINAME(sc), chp->ch_channel, error);
1126 return error;
1127 }
1128 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
1129 achp->ahcic_datad[slot]->dm_mapsize,
1130 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1131 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) {
1132 cmd_tbl->cmdt_prd[seg].prd_dba = htole32(
1133 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr);
1134 cmd_tbl->cmdt_prd[seg].prd_dbau = 0;
1135 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32(
1136 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1);
1137 }
1138 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC);
1139 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs);
1140 end:
1141 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE);
1142 return 0;
1143 }
1144
1145 #if NATAPIBUS > 0
1146 void
1147 ahci_atapibus_attach(struct atabus_softc * ata_sc)
1148 {
1149 struct ata_channel *chp = ata_sc->sc_chan;
1150 struct atac_softc *atac = chp->ch_atac;
1151 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic;
1152 struct scsipi_channel *chan = &chp->ch_atapi_channel;
1153 /*
1154 * Fill in the scsipi_adapter.
1155 */
1156 adapt->adapt_dev = atac->atac_dev;
1157 adapt->adapt_nchannels = atac->atac_nchannels;
1158 adapt->adapt_request = ahci_atapi_scsipi_request;
1159 adapt->adapt_minphys = ahci_atapi_minphys;
1160 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device;
1161
1162 /*
1163 * Fill in the scsipi_channel.
1164 */
1165 memset(chan, 0, sizeof(*chan));
1166 chan->chan_adapter = adapt;
1167 chan->chan_bustype = &ahci_atapi_bustype;
1168 chan->chan_channel = chp->ch_channel;
1169 chan->chan_flags = SCSIPI_CHAN_OPENINGS;
1170 chan->chan_openings = 1;
1171 chan->chan_max_periph = 1;
1172 chan->chan_ntargets = 1;
1173 chan->chan_nluns = 1;
1174 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan,
1175 atapiprint);
1176 }
1177
1178 void
1179 ahci_atapi_minphys(struct buf *bp)
1180 {
1181 if (bp->b_bcount > MAXPHYS)
1182 bp->b_bcount = MAXPHYS;
1183 minphys(bp);
1184 }
1185
1186 /*
1187 * Kill off all pending xfers for a periph.
1188 *
1189 * Must be called at splbio().
1190 */
1191 void
1192 ahci_atapi_kill_pending(struct scsipi_periph *periph)
1193 {
1194 struct atac_softc *atac =
1195 device_private(periph->periph_channel->chan_adapter->adapt_dev);
1196 struct ata_channel *chp =
1197 atac->atac_channels[periph->periph_channel->chan_channel];
1198
1199 ata_kill_pending(&chp->ch_drive[periph->periph_target]);
1200 }
1201
1202 void
1203 ahci_atapi_scsipi_request(struct scsipi_channel *chan,
1204 scsipi_adapter_req_t req, void *arg)
1205 {
1206 struct scsipi_adapter *adapt = chan->chan_adapter;
1207 struct scsipi_periph *periph;
1208 struct scsipi_xfer *sc_xfer;
1209 struct ahci_softc *sc = device_private(adapt->adapt_dev);
1210 struct atac_softc *atac = &sc->sc_atac;
1211 struct ata_xfer *xfer;
1212 int channel = chan->chan_channel;
1213 int drive, s;
1214
1215 switch (req) {
1216 case ADAPTER_REQ_RUN_XFER:
1217 sc_xfer = arg;
1218 periph = sc_xfer->xs_periph;
1219 drive = periph->periph_target;
1220 if (!device_is_active(atac->atac_dev)) {
1221 sc_xfer->error = XS_DRIVER_STUFFUP;
1222 scsipi_done(sc_xfer);
1223 return;
1224 }
1225 xfer = ata_get_xfer(ATAXF_NOSLEEP);
1226 if (xfer == NULL) {
1227 sc_xfer->error = XS_RESOURCE_SHORTAGE;
1228 scsipi_done(sc_xfer);
1229 return;
1230 }
1231
1232 if (sc_xfer->xs_control & XS_CTL_POLL)
1233 xfer->c_flags |= C_POLL;
1234 xfer->c_drive = drive;
1235 xfer->c_flags |= C_ATAPI;
1236 xfer->c_cmd = sc_xfer;
1237 xfer->c_databuf = sc_xfer->data;
1238 xfer->c_bcount = sc_xfer->datalen;
1239 xfer->c_start = ahci_atapi_start;
1240 xfer->c_intr = ahci_atapi_complete;
1241 xfer->c_kill_xfer = ahci_atapi_kill_xfer;
1242 xfer->c_dscpoll = 0;
1243 s = splbio();
1244 ata_exec_xfer(atac->atac_channels[channel], xfer);
1245 #ifdef DIAGNOSTIC
1246 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 &&
1247 (sc_xfer->xs_status & XS_STS_DONE) == 0)
1248 panic("ahci_atapi_scsipi_request: polled command "
1249 "not done");
1250 #endif
1251 splx(s);
1252 return;
1253 default:
1254 /* Not supported, nothing to do. */
1255 ;
1256 }
1257 }
1258
1259 void
1260 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer)
1261 {
1262 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1263 struct ahci_channel *achp = (struct ahci_channel *)chp;
1264 struct scsipi_xfer *sc_xfer = xfer->c_cmd;
1265 int slot = 0 /* XXX slot */;
1266 struct ahci_cmd_tbl *cmd_tbl;
1267 struct ahci_cmd_header *cmd_h;
1268 int i;
1269 int channel = chp->ch_channel;
1270
1271 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n",
1272 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS);
1273
1274 cmd_tbl = achp->ahcic_cmd_tbl[slot];
1275 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel,
1276 cmd_tbl), DEBUG_XFERS);
1277
1278 satafis_rhd_construct_atapi(xfer, cmd_tbl->cmdt_cfis);
1279 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd));
1280 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen);
1281
1282 cmd_h = &achp->ahcic_cmdh[slot];
1283 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc),
1284 chp->ch_channel, cmd_h), DEBUG_XFERS);
1285 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL,
1286 sc_xfer->datalen,
1287 (sc_xfer->xs_control & XS_CTL_DATA_IN) ?
1288 BUS_DMA_READ : BUS_DMA_WRITE)) {
1289 sc_xfer->error = XS_DRIVER_STUFFUP;
1290 ahci_atapi_complete(chp, xfer, slot);
1291 return;
1292 }
1293 cmd_h->cmdh_flags = htole16(
1294 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) |
1295 RHD_FISLEN / 4 | AHCI_CMDH_F_A);
1296 cmd_h->cmdh_prdbc = 0;
1297 AHCI_CMDH_SYNC(sc, achp, slot,
1298 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1299
1300 if (xfer->c_flags & C_POLL) {
1301 /* polled command, disable interrupts */
1302 AHCI_WRITE(sc, AHCI_GHC,
1303 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE);
1304 }
1305 chp->ch_flags |= ATACH_IRQ_WAIT;
1306 chp->ch_status = 0;
1307 /* start command */
1308 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot);
1309 /* and says we started this command */
1310 achp->ahcic_cmds_active |= 1 << slot;
1311
1312 if ((xfer->c_flags & C_POLL) == 0) {
1313 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */
1314 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout),
1315 ahci_timeout, chp);
1316 return;
1317 }
1318 /*
1319 * Polled command.
1320 */
1321 for (i = 0; i < ATA_DELAY / 10; i++) {
1322 if (sc_xfer->xs_status & XS_STS_DONE)
1323 break;
1324 ahci_intr_port(sc, achp);
1325 delay(10000);
1326 }
1327 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel,
1328 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS),
1329 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)),
1330 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)),
1331 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))),
1332 DEBUG_XFERS);
1333 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) {
1334 sc_xfer->error = XS_TIMEOUT;
1335 ahci_atapi_complete(chp, xfer, slot);
1336 }
1337 /* reenable interrupts */
1338 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE);
1339 }
1340
1341 int
1342 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq)
1343 {
1344 int slot = 0; /* XXX slot */
1345 struct scsipi_xfer *sc_xfer = xfer->c_cmd;
1346 int drive = xfer->c_drive;
1347 struct ahci_channel *achp = (struct ahci_channel *)chp;
1348 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac;
1349
1350 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel),
1351 DEBUG_FUNCS);
1352
1353 achp->ahcic_cmds_active &= ~(1 << slot);
1354 chp->ch_flags &= ~ATACH_IRQ_WAIT;
1355 if (xfer->c_flags & C_TIMEOU) {
1356 sc_xfer->error = XS_TIMEOUT;
1357 } else {
1358 callout_stop(&chp->ch_callout);
1359 sc_xfer->error = 0;
1360 }
1361
1362 chp->ch_queue->active_xfer = NULL;
1363 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0,
1364 achp->ahcic_datad[slot]->dm_mapsize,
1365 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD :
1366 BUS_DMASYNC_POSTWRITE);
1367 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]);
1368
1369 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) {
1370 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE);
1371 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN;
1372 wakeup(&chp->ch_queue->active_xfer);
1373 return 0;
1374 }
1375 ata_free_xfer(chp, xfer);
1376
1377 AHCI_CMDH_SYNC(sc, achp, slot,
1378 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1379 sc_xfer->resid = sc_xfer->datalen;
1380 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc);
1381 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n",
1382 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS);
1383 if (chp->ch_status & WDCS_ERR &&
1384 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 ||
1385 sc_xfer->resid == sc_xfer->datalen)) {
1386 sc_xfer->error = XS_SHORTSENSE;
1387 sc_xfer->sense.atapi_sense = chp->ch_error;
1388 if ((sc_xfer->xs_periph->periph_quirks &
1389 PQUIRK_NOSENSE) == 0) {
1390 /* ask scsipi to send a REQUEST_SENSE */
1391 sc_xfer->error = XS_BUSY;
1392 sc_xfer->status = SCSI_CHECK;
1393 }
1394 }
1395 scsipi_done(sc_xfer);
1396 atastart(chp);
1397 return 0;
1398 }
1399
1400 void
1401 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason)
1402 {
1403 struct scsipi_xfer *sc_xfer = xfer->c_cmd;
1404 struct ahci_channel *achp = (struct ahci_channel *)chp;
1405 int slot = 0; /* XXX slot */
1406
1407 achp->ahcic_cmds_active &= ~(1 << slot);
1408
1409 /* remove this command from xfer queue */
1410 switch (reason) {
1411 case KILL_GONE:
1412 sc_xfer->error = XS_DRIVER_STUFFUP;
1413 break;
1414 case KILL_RESET:
1415 sc_xfer->error = XS_RESET;
1416 break;
1417 default:
1418 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason);
1419 panic("ahci_ata_atapi_kill_xfer");
1420 }
1421 ata_free_xfer(chp, xfer);
1422 scsipi_done(sc_xfer);
1423 }
1424
1425 void
1426 ahci_atapi_probe_device(struct atapibus_softc *sc, int target)
1427 {
1428 struct scsipi_channel *chan = sc->sc_channel;
1429 struct scsipi_periph *periph;
1430 struct ataparams ids;
1431 struct ataparams *id = &ids;
1432 struct ahci_softc *ahcic =
1433 device_private(chan->chan_adapter->adapt_dev);
1434 struct atac_softc *atac = &ahcic->sc_atac;
1435 struct ata_channel *chp = atac->atac_channels[chan->chan_channel];
1436 struct ata_drive_datas *drvp = &chp->ch_drive[target];
1437 struct scsipibus_attach_args sa;
1438 char serial_number[21], model[41], firmware_revision[9];
1439 int s;
1440
1441 /* skip if already attached */
1442 if (scsipi_lookup_periph(chan, target, 0) != NULL)
1443 return;
1444
1445 /* if no ATAPI device detected at attach time, skip */
1446 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) {
1447 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d "
1448 "not present\n", target), DEBUG_PROBE);
1449 return;
1450 }
1451
1452 /* Some ATAPI devices need a bit more time after software reset. */
1453 delay(5000);
1454 if (ata_get_params(drvp, AT_WAIT, id) == 0) {
1455 #ifdef ATAPI_DEBUG_PROBE
1456 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n",
1457 AHCINAME(ahcic), target,
1458 id->atap_config & ATAPI_CFG_CMD_MASK,
1459 id->atap_config & ATAPI_CFG_DRQ_MASK);
1460 #endif
1461 periph = scsipi_alloc_periph(M_NOWAIT);
1462 if (periph == NULL) {
1463 aprint_error_dev(sc->sc_dev,
1464 "unable to allocate periph for drive %d\n",
1465 target);
1466 return;
1467 }
1468 periph->periph_dev = NULL;
1469 periph->periph_channel = chan;
1470 periph->periph_switch = &atapi_probe_periphsw;
1471 periph->periph_target = target;
1472 periph->periph_lun = 0;
1473 periph->periph_quirks = PQUIRK_ONLYBIG;
1474
1475 #ifdef SCSIPI_DEBUG
1476 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI &&
1477 SCSIPI_DEBUG_TARGET == target)
1478 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS;
1479 #endif
1480 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config);
1481 if (id->atap_config & ATAPI_CFG_REMOV)
1482 periph->periph_flags |= PERIPH_REMOVABLE;
1483 if (periph->periph_type == T_SEQUENTIAL) {
1484 s = splbio();
1485 drvp->drive_flags |= DRIVE_ATAPIST;
1486 splx(s);
1487 }
1488
1489 sa.sa_periph = periph;
1490 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config);
1491 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ?
1492 T_REMOV : T_FIXED;
1493 scsipi_strvis((u_char *)model, 40, id->atap_model, 40);
1494 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial,
1495 20);
1496 scsipi_strvis((u_char *)firmware_revision, 8,
1497 id->atap_revision, 8);
1498 sa.sa_inqbuf.vendor = model;
1499 sa.sa_inqbuf.product = serial_number;
1500 sa.sa_inqbuf.revision = firmware_revision;
1501
1502 /*
1503 * Determine the operating mode capabilities of the device.
1504 */
1505 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16)
1506 periph->periph_cap |= PERIPH_CAP_CMD16;
1507 /* XXX This is gross. */
1508 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK);
1509
1510 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa);
1511
1512 if (drvp->drv_softc)
1513 ata_probe_caps(drvp);
1514 else {
1515 s = splbio();
1516 drvp->drive_flags &= ~DRIVE_ATAPI;
1517 splx(s);
1518 }
1519 } else {
1520 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE "
1521 "failed for drive %s:%d:%d: error 0x%x\n",
1522 AHCINAME(ahcic), chp->ch_channel, target,
1523 chp->ch_error), DEBUG_PROBE);
1524 s = splbio();
1525 drvp->drive_flags &= ~DRIVE_ATAPI;
1526 splx(s);
1527 }
1528 }
1529 #endif /* NATAPIBUS */
NetBSD on the FriendlyARM MINI2440