sys/dev/ic/athvar.h

   1 /*      $NetBSD: athvar.h,v 1.28 2009/08/02 13:26:33 jmcneill Exp $     */
   2
   3 /*-
   4  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  15  *    redistribution must be conditioned upon including a substantially
  16  *    similar Disclaimer requirement for further binary redistribution.
  17  * 3. Neither the names of the above-listed copyright holders nor the names
  18  *    of any contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  *
  21  * Alternatively, this software may be distributed under the terms of the
  22  * GNU General Public License ("GPL") version 2 as published by the Free
  23  * Software Foundation.
  24  *
  25  * NO WARRANTY
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  29  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  30  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  31  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  34  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  36  * THE POSSIBILITY OF SUCH DAMAGES.
  37  *
  38  * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.29 2005/08/08 18:46:36 sam Exp $
  39  */
  40
  41 /*
  42  * Defintions for the Atheros Wireless LAN controller driver.
  43  */
  44 #ifndef _DEV_ATH_ATHVAR_H
  45 #define _DEV_ATH_ATHVAR_H
  46
  47 #include <net80211/ieee80211_radiotap.h>
  48
  49 #include <external/isc/atheros_hal/dist/ah.h>
  50
  51 #include <dev/ic/ath_netbsd.h>
  52 #include <dev/ic/athioctl.h>
  53 #include <dev/ic/athrate.h>
  54
  55 #define ATH_TIMEOUT             1000
  56
  57 #ifndef ATH_RXBUF
  58 #define ATH_RXBUF       40              /* number of RX buffers */
  59 #endif
  60 #ifndef ATH_TXBUF
  61 #define ATH_TXBUF       200             /* number of TX buffers */
  62 #endif
  63 #define ATH_TXDESC      10              /* number of descriptors per buffer */
  64 #define ATH_TXMAXTRY    11              /* max number of transmit attempts */
  65 #define ATH_TXMGTTRY    4               /* xmit attempts for mgt/ctl frames */
  66 #define ATH_TXINTR_PERIOD 5             /* max number of batched tx descriptors */
  67
  68 #define ATH_BEACON_AIFS_DEFAULT  0      /* default aifs for ap beacon q */
  69 #define ATH_BEACON_CWMIN_DEFAULT 0      /* default cwmin for ap beacon q */
  70 #define ATH_BEACON_CWMAX_DEFAULT 0      /* default cwmax for ap beacon q */
  71
  72 /*
  73  * The key cache is used for h/w cipher state and also for
  74  * tracking station state such as the current tx antenna.
  75  * We also setup a mapping table between key cache slot indices
  76  * and station state to short-circuit node lookups on rx.
  77  * Different parts have different size key caches.  We handle
  78  * up to ATH_KEYMAX entries (could dynamically allocate state).
  79  */
  80 #define ATH_KEYMAX      128             /* max key cache size we handle */
  81 #define ATH_KEYBYTES    (ATH_KEYMAX/NBBY)       /* storage space in bytes */
  82 /*
  83  * Convert from net80211 layer values to Ath layer values. Hopefully this will
  84  * be optimised away when the two constants are the same.
  85  */
  86 typedef unsigned int ath_keyix_t;
  87 #define ATH_KEY(_keyix) ((_keyix == IEEE80211_KEYIX_NONE) ? HAL_TXKEYIX_INVALID : _keyix)
  88
  89 /* driver-specific node state */
  90 struct ath_node {
  91         struct ieee80211_node an_node;  /* base class */
  92         u_int32_t       an_avgrssi;     /* average rssi over all rx frames */
  93         /* variable-length rate control state follows */
  94 };
  95 #define ATH_NODE(ni)    ((struct ath_node *)(ni))
  96 #define ATH_NODE_CONST(ni)      ((const struct ath_node *)(ni))
  97
  98 #define ATH_RSSI_LPF_LEN        10
  99 #define ATH_RSSI_DUMMY_MARKER   0x127
 100 #define ATH_EP_MUL(x, mul)      ((x) * (mul))
 101 #define ATH_RSSI_IN(x)          (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
 102 #define ATH_LPF_RSSI(x, y, len) \
 103     ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
 104 #define ATH_RSSI_LPF(x, y) do {                                         \
 105     if ((y) >= -20)                                                     \
 106         x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN);      \
 107 } while (0)
 108
 109 struct ath_buf {
 110         STAILQ_ENTRY(ath_buf)   bf_list;
 111 #define bf_nseg         bf_dmamap->dm_nsegs
 112         int                     bf_flags;       /* tx descriptor flags */
 113         struct ath_desc         *bf_desc;       /* virtual addr of desc */
 114         bus_addr_t              bf_daddr;       /* physical addr of desc */
 115         bus_dmamap_t            bf_dmamap;      /* DMA map for mbuf chain */
 116         struct mbuf             *bf_m;          /* mbuf for buf */
 117         struct ieee80211_node   *bf_node;       /* pointer to the node */
 118 #define bf_mapsize      bf_dmamap->dm_mapsize
 119 #define ATH_MAX_SCATTER         ATH_TXDESC      /* max(tx,rx,beacon) desc's */
 120 #define bf_segs         bf_dmamap->dm_segs
 121 };
 122 typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
 123
 124 /*
 125  * DMA state for tx/rx descriptors.
 126  */
 127 struct ath_descdma {
 128         const char*             dd_name;
 129         struct ath_desc         *dd_desc;       /* descriptors */
 130         bus_addr_t              dd_desc_paddr;  /* physical addr of dd_desc */
 131         bus_size_t              dd_desc_len;    /* size of dd_desc */
 132         bus_dma_segment_t       dd_dseg;
 133         int                     dd_dnseg;       /* number of segments */
 134         bus_dma_tag_t           dd_dmat;        /* bus DMA tag */
 135         bus_dmamap_t            dd_dmamap;      /* DMA map for descriptors */
 136         struct ath_buf          *dd_bufptr;     /* associated buffers */
 137 };
 138
 139 /*
 140  * Data transmit queue state.  One of these exists for each
 141  * hardware transmit queue.  Packets sent to us from above
 142  * are assigned to queues based on their priority.  Not all
 143  * devices support a complete set of hardware transmit queues.
 144  * For those devices the array sc_ac2q will map multiple
 145  * priorities to fewer hardware queues (typically all to one
 146  * hardware queue).
 147  */
 148 struct ath_txq {
 149         u_int                   axq_qnum;       /* hardware q number */
 150         u_int                   axq_depth;      /* queue depth (stat only) */
 151         u_int                   axq_intrcnt;    /* interrupt count */
 152         u_int32_t               *axq_link;      /* link ptr in last TX desc */
 153         STAILQ_HEAD(, ath_buf)  axq_q;          /* transmit queue */
 154         ath_txq_lock_t          axq_lock;       /* lock on q and link */
 155         /*
 156          * State for patching up CTS when bursting.
 157          */
 158         struct  ath_buf         *axq_linkbuf;   /* va of last buffer */
 159         u_int                   axq_timer;      /* transmit timeout */
 160 };
 161
 162 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
 163         STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
 164         (_tq)->axq_depth++; \
 165         (_tq)->axq_timer = 5; \
 166 } while (0)
 167 #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
 168         STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
 169         if (--(_tq)->axq_depth == 0) \
 170                 (_tq)->axq_timer = 0; \
 171 } while (0)
 172
 173 struct taskqueue;
 174 struct ath_tx99;
 175
 176 struct ath_softc {
 177         device_t                sc_dev;
 178         struct device_suspensor sc_suspensor;
 179         struct pmf_qual         sc_qual;
 180         struct ethercom         sc_ec;          /* interface common */
 181         struct ath_stats        sc_stats;       /* interface statistics */
 182         struct ieee80211com     sc_ic;          /* IEEE 802.11 common */
 183         void                    (*sc_power)(struct ath_softc *, int);
 184         int                     sc_regdomain;
 185         int                     sc_countrycode;
 186         int                     sc_debug;
 187         struct sysctllog        *sc_sysctllog;
 188         void                    (*sc_recv_mgmt)(struct ieee80211com *,
 189                                         struct mbuf *,
 190                                         struct ieee80211_node *,
 191                                         int, int, u_int32_t);
 192         int                     (*sc_newstate)(struct ieee80211com *,
 193                                         enum ieee80211_state, int);
 194         void                    (*sc_node_free)(struct ieee80211_node *);
 195         HAL_BUS_TAG             sc_st;          /* bus space tag */
 196         HAL_BUS_HANDLE          sc_sh;          /* bus space handle */
 197         bus_dma_tag_t           sc_dmat;        /* bus DMA tag */
 198         ath_lock_t              sc_mtx;         /* master lock (recursive) */
 199         struct ath_hal          *sc_ah;         /* Atheros HAL */
 200         struct ath_ratectrl     *sc_rc;         /* tx rate control support */
 201         struct ath_tx99         *sc_tx99;       /* tx99 adjunct state */
 202         void                    (*sc_setdefantenna)(struct ath_softc *, u_int);
 203         unsigned int            sc_mrretry : 1, /* multi-rate retry support */
 204                                 sc_softled : 1, /* enable LED gpio status */
 205                                 sc_splitmic: 1, /* split TKIP MIC keys */
 206                                 sc_needmib : 1, /* enable MIB stats intr */
 207                                 sc_diversity : 1,/* enable rx diversity */
 208                                 sc_hasveol : 1, /* tx VEOL support */
 209                                 sc_ledstate: 1, /* LED on/off state */
 210                                 sc_blinking: 1, /* LED blink operation active */
 211                                 sc_mcastkey: 1, /* mcast key cache search */
 212                                 sc_syncbeacon:1,/* sync/resync beacon timers */
 213                                 sc_hasclrkey:1; /* CLR key supported */
 214                                                 /* rate tables */
 215         const HAL_RATE_TABLE    *sc_rates[IEEE80211_MODE_MAX];
 216         const HAL_RATE_TABLE    *sc_currates;   /* current rate table */
 217         enum ieee80211_phymode  sc_curmode;     /* current phy mode */
 218         u_int16_t               sc_curtxpow;    /* current tx power limit */
 219         HAL_CHANNEL             sc_curchan;     /* current h/w channel */
 220         u_int8_t                sc_rixmap[256]; /* IEEE to h/w rate table ix */
 221         struct {
 222                 u_int8_t        ieeerate;       /* IEEE rate */
 223                 u_int8_t        rxflags;        /* radiotap rx flags */
 224                 u_int8_t        txflags;        /* radiotap tx flags */
 225                 u_int16_t       ledon;          /* softled on time */
 226                 u_int16_t       ledoff;         /* softled off time */
 227         } sc_hwmap[32];                         /* h/w rate ix mappings */
 228         u_int8_t                sc_minrateix;   /* min h/w rate index */
 229         u_int8_t                sc_mcastrix;    /* mcast h/w rate index */
 230         u_int8_t                sc_protrix;     /* protection rate index */
 231         u_int                   sc_mcastrate;   /* ieee rate for mcastrateix */
 232         u_int                   sc_txantenna;   /* tx antenna (fixed or auto) */
 233         HAL_INT                 sc_imask;       /* interrupt mask copy */
 234         u_int                   sc_keymax;      /* size of key cache */
 235         u_int8_t                sc_keymap[ATH_KEYBYTES];/* key use bit map */
 236
 237         u_int                   sc_ledpin;      /* GPIO pin for driving LED */
 238         u_int                   sc_ledon;       /* pin setting for LED on */
 239         u_int                   sc_ledidle;     /* idle polling interval */
 240         int                     sc_ledevent;    /* time of last LED event */
 241         u_int8_t                sc_rxrate;      /* current rx rate for LED */
 242         u_int8_t                sc_txrate;      /* current tx rate for LED */
 243         u_int16_t               sc_ledoff;      /* off time for current blink */
 244         struct callout          sc_ledtimer;    /* led off timer */
 245
 246         void *                  sc_drvbpf;
 247         union {
 248                 struct ath_tx_radiotap_header th;
 249                 u_int8_t        pad[64];
 250         } u_tx_rt;
 251         int                     sc_tx_th_len;
 252         union {
 253                 struct ath_rx_radiotap_header th;
 254                 u_int8_t        pad[64];
 255         } u_rx_rt;
 256         int                     sc_rx_th_len;
 257
 258         ath_task_t              sc_fataltask;   /* fatal int processing */
 259
 260         struct ath_descdma      sc_rxdma;       /* RX descriptos */
 261         ath_bufhead             sc_rxbuf;       /* receive buffer */
 262         u_int32_t               *sc_rxlink;     /* link ptr in last RX desc */
 263         ath_task_t              sc_rxtask;      /* rx int processing */
 264         ath_task_t              sc_rxorntask;   /* rxorn int processing */
 265         ath_task_t              sc_radartask;   /* radar processing */
 266         u_int8_t                sc_defant;      /* current default antenna */
 267         u_int8_t                sc_rxotherant;  /* rx's on non-default antenna*/
 268         u_int64_t               sc_lastrx;      /* tsf of last rx'd frame */
 269
 270         struct ath_descdma      sc_txdma;       /* TX descriptors */
 271         ath_bufhead             sc_txbuf;       /* transmit buffer */
 272         ath_txbuf_lock_t        sc_txbuflock;   /* txbuf lock */
 273         u_int                   sc_txqsetup;    /* h/w queues setup */
 274         u_int                   sc_txintrperiod;/* tx interrupt batching */
 275         struct ath_txq          sc_txq[HAL_NUM_TX_QUEUES];
 276         struct ath_txq          *sc_ac2q[5];    /* WME AC -> h/w q map */
 277         ath_task_t              sc_txtask;      /* tx int processing */
 278
 279         struct ath_descdma      sc_bdma;        /* beacon descriptors */
 280         ath_bufhead             sc_bbuf;        /* beacon buffers */
 281         u_int                   sc_bhalq;       /* HAL q for outgoing beacons */
 282         u_int                   sc_bmisscount;  /* missed beacon transmits */
 283         u_int32_t               sc_ant_tx[8];   /* recent tx frames/antenna */
 284         struct ath_txq          *sc_cabq;       /* tx q for cab frames */
 285         struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */
 286         ath_task_t              sc_bmisstask;   /* bmiss int processing */
 287         ath_task_t              sc_bstucktask;  /* stuck beacon processing */
 288         enum {
 289                 OK,                             /* no change needed */
 290                 UPDATE,                         /* update pending */
 291                 COMMIT                          /* beacon sent, commit change */
 292         } sc_updateslot;                        /* slot time update fsm */
 293
 294         struct callout          sc_cal_ch;      /* callout handle for cals */
 295         int                     sc_calinterval; /* current polling interval */
 296         int                     sc_caltries;    /* cals at current interval */
 297         HAL_NODE_STATS          sc_halstats;    /* station-mode rssi stats */
 298         struct callout          sc_scan_ch;     /* callout handle for scan */
 299         struct callout          sc_dfs_ch;      /* callout handle for dfs */
 300         u_int                   sc_flags;       /* misc flags */
 301 };
 302 #define sc_if                   sc_ec.ec_if
 303 #define sc_tx_th                u_tx_rt.th
 304 #define sc_rx_th                u_rx_rt.th
 305
 306 #define ATH_ATTACHED            0x0001          /* attach has succeeded */
 307
 308 #define ATH_TXQ_SETUP(sc, i)    ((sc)->sc_txqsetup & (1<<i))
 309
 310 int     ath_attach(u_int16_t, struct ath_softc *);
 311 int     ath_detach(struct ath_softc *);
 312 int     ath_activate(device_t, enum devact);
 313 bool    ath_resume(struct ath_softc *);
 314 void    ath_suspend(struct ath_softc *);
 315 int     ath_intr(void *);
 316 int     ath_reset(struct ifnet *);
 317 void    ath_sysctlattach(struct ath_softc *);
 318
 319 extern int ath_dwelltime;
 320 extern int ath_calinterval;
 321 extern int ath_outdoor;
 322 extern int ath_xchanmode;
 323 extern int ath_countrycode;
 324 extern int ath_regdomain;
 325 extern int ath_debug;
 326 extern int ath_rxbuf;
 327 extern int ath_txbuf;
 328
 329 /*
 330  * HAL definitions to comply with local coding convention.
 331  */
 332 #define ath_hal_detach(_ah) \
 333         ((*(_ah)->ah_detach)((_ah)))
 334 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
 335         ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
 336 #define ath_hal_getratetable(_ah, _mode) \
 337         ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
 338 #define ath_hal_getmac(_ah, _mac) \
 339         ((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
 340 #define ath_hal_setmac(_ah, _mac) \
 341         ((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
 342 #define ath_hal_intrset(_ah, _mask) \
 343         ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
 344 #define ath_hal_intrget(_ah) \
 345         ((*(_ah)->ah_getInterrupts)((_ah)))
 346 #define ath_hal_intrpend(_ah) \
 347         ((*(_ah)->ah_isInterruptPending)((_ah)))
 348 #define ath_hal_getisr(_ah, _pmask) \
 349         ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
 350 #define ath_hal_updatetxtriglevel(_ah, _inc) \
 351         ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
 352 #define ath_hal_setpower(_ah, _mode) \
 353         ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
 354 #define ath_hal_keycachesize(_ah) \
 355         ((*(_ah)->ah_getKeyCacheSize)((_ah)))
 356 #define ath_hal_keyreset(_ah, _ix) \
 357         ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
 358 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \
 359         ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
 360 #define ath_hal_keyisvalid(_ah, _ix) \
 361         (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
 362 #define ath_hal_keysetmac(_ah, _ix, _mac) \
 363         ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
 364 #define ath_hal_getrxfilter(_ah) \
 365         ((*(_ah)->ah_getRxFilter)((_ah)))
 366 #define ath_hal_setrxfilter(_ah, _filter) \
 367         ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
 368 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
 369         ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
 370 #define ath_hal_waitforbeacon(_ah, _bf) \
 371         ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
 372 #define ath_hal_putrxbuf(_ah, _bufaddr) \
 373         ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
 374 #define ath_hal_gettsf32(_ah) \
 375         ((*(_ah)->ah_getTsf32)((_ah)))
 376 #define ath_hal_gettsf64(_ah) \
 377         ((*(_ah)->ah_getTsf64)((_ah)))
 378 #define ath_hal_resettsf(_ah) \
 379         ((*(_ah)->ah_resetTsf)((_ah)))
 380 #define ath_hal_rxena(_ah) \
 381         ((*(_ah)->ah_enableReceive)((_ah)))
 382 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
 383         ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
 384 #define ath_hal_gettxbuf(_ah, _q) \
 385         ((*(_ah)->ah_getTxDP)((_ah), (_q)))
 386 #define ath_hal_numtxpending(_ah, _q) \
 387         ((*(_ah)->ah_numTxPending)((_ah), (_q)))
 388 #define ath_hal_getrxbuf(_ah) \
 389         ((*(_ah)->ah_getRxDP)((_ah)))
 390 #define ath_hal_txstart(_ah, _q) \
 391         ((*(_ah)->ah_startTxDma)((_ah), (_q)))
 392 #define ath_hal_setchannel(_ah, _chan) \
 393         ((*(_ah)->ah_setChannel)((_ah), (_chan)))
 394 #define ath_hal_calibrate(_ah, _chan, _iqcal) \
 395         ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
 396 #define ath_hal_setledstate(_ah, _state) \
 397         ((*(_ah)->ah_setLedState)((_ah), (_state)))
 398 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \
 399         ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
 400 #define ath_hal_beaconreset(_ah) \
 401         ((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
 402 #define ath_hal_beacontimers(_ah, _bs) \
 403         ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
 404 #define ath_hal_setassocid(_ah, _bss, _associd) \
 405         ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
 406 #define ath_hal_phydisable(_ah) \
 407         ((*(_ah)->ah_phyDisable)((_ah)))
 408 #define ath_hal_setopmode(_ah) \
 409         ((*(_ah)->ah_setPCUConfig)((_ah)))
 410 #define ath_hal_stoptxdma(_ah, _qnum) \
 411         ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
 412 #define ath_hal_stoppcurecv(_ah) \
 413         ((*(_ah)->ah_stopPcuReceive)((_ah)))
 414 #define ath_hal_startpcurecv(_ah) \
 415         ((*(_ah)->ah_startPcuReceive)((_ah)))
 416 #define ath_hal_stopdmarecv(_ah) \
 417         ((*(_ah)->ah_stopDmaReceive)((_ah)))
 418 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
 419         ((*(_ah)->ah_getDiagState)((_ah), (_id), \
 420                 (_indata), (_insize), (_outdata), (_outsize)))
 421 #define ath_hal_setuptxqueue(_ah, _type, _irq) \
 422         ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
 423 #define ath_hal_resettxqueue(_ah, _q) \
 424         ((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
 425 #define ath_hal_releasetxqueue(_ah, _q) \
 426         ((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
 427 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \
 428         ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
 429 #define ath_hal_settxqueueprops(_ah, _q, _qi) \
 430         ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
 431 #define ath_hal_getrfgain(_ah) \
 432         ((*(_ah)->ah_getRfGain)((_ah)))
 433 #define ath_hal_getdefantenna(_ah) \
 434         ((*(_ah)->ah_getDefAntenna)((_ah)))
 435 #define ath_hal_setdefantenna(_ah, _ant) \
 436         ((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
 437 #define ath_hal_rxmonitor(_ah, _arg, _chan) \
 438         ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
 439 #define ath_hal_mibevent(_ah, _stats) \
 440         ((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
 441 #define ath_hal_setslottime(_ah, _us) \
 442         ((*(_ah)->ah_setSlotTime)((_ah), (_us)))
 443 #define ath_hal_getslottime(_ah) \
 444         ((*(_ah)->ah_getSlotTime)((_ah)))
 445 #define ath_hal_setacktimeout(_ah, _us) \
 446         ((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
 447 #define ath_hal_getacktimeout(_ah) \
 448         ((*(_ah)->ah_getAckTimeout)((_ah)))
 449 #define ath_hal_setctstimeout(_ah, _us) \
 450         ((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
 451 #define ath_hal_getctstimeout(_ah) \
 452         ((*(_ah)->ah_getCTSTimeout)((_ah)))
 453 #define ath_hal_getcapability(_ah, _cap, _param, _result) \
 454         ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
 455 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
 456         ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
 457 #define ath_hal_ciphersupported(_ah, _cipher) \
 458         (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
 459 #define ath_hal_getregdomain(_ah, _prd) \
 460         (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
 461 #define ath_hal_setregdomain(_ah, _rd) \
 462         ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL)
 463 #define ath_hal_getcountrycode(_ah, _pcc) \
 464         (*(_pcc) = (_ah)->ah_countryCode)
 465 #define ath_hal_gettkipmic(_ah) \
 466         (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK)
 467 #define ath_hal_settkipmic(_ah, _v) \
 468         ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL)
 469 #define ath_hal_hastkipsplit(_ah) \
 470         (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
 471 #define ath_hal_gettkipsplit(_ah) \
 472         (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
 473 #define ath_hal_settkipsplit(_ah, _v) \
 474         ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)
 475 #define ath_hal_haswmetkipmic(_ah) \
 476         (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK)
 477 #define ath_hal_hwphycounters(_ah) \
 478         (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
 479 #define ath_hal_hasdiversity(_ah) \
 480         (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
 481 #define ath_hal_getdiversity(_ah) \
 482         (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
 483 #define ath_hal_setdiversity(_ah, _v) \
 484         ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
 485 #define ath_hal_getdiag(_ah, _pv) \
 486         (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
 487 #define ath_hal_setdiag(_ah, _v) \
 488         ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
 489 #define ath_hal_getnumtxqueues(_ah, _pv) \
 490         (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
 491 #define ath_hal_hasveol(_ah) \
 492         (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
 493 #define ath_hal_hastxpowlimit(_ah) \
 494         (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
 495 #define ath_hal_settxpowlimit(_ah, _pow) \
 496         ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
 497 #define ath_hal_gettxpowlimit(_ah, _ppow) \
 498         (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
 499 #define ath_hal_getmaxtxpow(_ah, _ppow) \
 500         (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
 501 #define ath_hal_gettpscale(_ah, _scale) \
 502         (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
 503 #define ath_hal_settpscale(_ah, _v) \
 504         ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
 505 #define ath_hal_hastpc(_ah) \
 506         (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
 507 #define ath_hal_gettpc(_ah) \
 508         (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
 509 #define ath_hal_settpc(_ah, _v) \
 510         ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
 511 #define ath_hal_hasbursting(_ah) \
 512         (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
 513 #ifdef notyet
 514 #define ath_hal_hasmcastkeysearch(_ah) \
 515         (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
 516 #define ath_hal_getmcastkeysearch(_ah) \
 517         (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
 518 #else
 519 #define ath_hal_getmcastkeysearch(_ah)  0
 520 #endif
 521 #define ath_hal_hasrfsilent(_ah) \
 522         (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
 523 #define ath_hal_getrfkill(_ah) \
 524         (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
 525 #define ath_hal_setrfkill(_ah, _onoff) \
 526         ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
 527 #define ath_hal_getrfsilent(_ah, _prfsilent) \
 528         (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
 529 #define ath_hal_setrfsilent(_ah, _rfsilent) \
 530         ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
 531 #define ath_hal_gettpack(_ah, _ptpack) \
 532         (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
 533 #define ath_hal_settpack(_ah, _tpack) \
 534         ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
 535 #define ath_hal_gettpcts(_ah, _ptpcts) \
 536         (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
 537 #define ath_hal_settpcts(_ah, _tpcts) \
 538         ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
 539 #define ath_hal_getchannoise(_ah, _c) \
 540         ((*(_ah)->ah_getChanNoise)((_ah), (_c)))
 541
 542 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
 543         ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
 544 #if 0
 545 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, tsf, a5) \
 546         ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), (tsf), (a5)))
 547 #else
 548 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \
 549         ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
 550 #endif
 551 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
 552                 _txr0, _txtr0, _keyix, _ant, _flags, \
 553                 _rtsrate, _rtsdura) \
 554         ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
 555                 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
 556                 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
 557 #define ath_hal_setupxtxdesc(_ah, _ds, \
 558                 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
 559         ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
 560                 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
 561 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
 562         ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
 563 #define ath_hal_txprocdesc(_ah, _ds, _ts) \
 564         ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
 565 #define ath_hal_gettxintrtxqs(_ah, _txqs) \
 566         ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
 567
 568 #define ath_hal_gpioCfgOutput(_ah, _gpio) \
 569         ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio)))
 570 #define ath_hal_gpioset(_ah, _gpio, _b) \
 571         ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
 572
 573 #define ath_hal_radar_event(_ah) \
 574         ((*(_ah)->ah_radarHaveEvent)((_ah)))
 575 #define ath_hal_procdfs(_ah, _chan) \
 576         ((*(_ah)->ah_processDfs)((_ah), (_chan)))
 577 #define ath_hal_checknol(_ah, _chan, _nchans) \
 578         ((*(_ah)->ah_dfsNolCheck)((_ah), (_chan), (_nchans)))
 579
 580 #endif /* _DEV_ATH_ATHVAR_H */