sys/dev/ic/cd1190reg.h

   1 /*      $NetBSD: cd1190reg.h,v 1.4 2005/12/11 12:21:26 christos Exp $   */
   2
   3 /*-
   4  * Copyright (c) 1998 Iain Hibbert.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 /*
  29  * Definitions for Cirrus Logic CD1190 parallel chips.
  30  */
  31
  32 /* ACK Width Register */
  33 #define CD1190_AWR              0x03
  34
  35 /* Controller Command Register */
  36 #define CD1190_CCR              0x0b
  37 #define CD1190_CCR_CGC          (1<<7)  /* Change Global Config Command */
  38 #define CD1190_CCR_CGC_RESET    (1<<0) /* CGC Reset Command */
  39 #define CD1190_CCR_PAR          (1<<6)  /* Parallel Command */
  40 #define CD1190_CCR_PAR_DISABLE  (1<<2) /* PAR Parallel Disable */
  41 #define CD1190_CCR_PAR_FLUSH    (1<<1) /* PAR Flush FIFO */
  42 #define CD1190_CCR_PAR_ENABLE   (1<<0) /* PAR Parallel Enable */
  43 #define CD1190_CCR_SIG          (1<<5)  /* Signal Command */
  44 #define CD1190_CCR_SIG_SET_BUSY (1<<2) /* SIG Set Busy Output */
  45 #define CD1190_CCR_SIG_ACK      (1<<1) /* SIG Pulse ACK Output */
  46 #define CD1190_CCR_SIG_CLR_BUSY (1<<0) /* SIG Clear Busy Output */
  47 #define CD1190_CCR_TIM          (1<<4)  /* Timer Command */
  48 #define CD1190_CCR_TIM_ENABLE   (1<<3) /* Timer Enabled */
  49
  50 /* Data Time-0ut Register */
  51 #define CD1190_DTR              0x09
  52
  53 /* End Of Service Request Register */
  54 #define CD1190_ESR              0x10
  55
  56 /* FIFO Count Register */
  57 #define CD1190_FCR              0x0e
  58
  59 /* FIFO Data Register */
  60 #define CD1190_FDR              0x12
  61
  62 /* Firmware Revision Register */
  63 #define CD1190_FRR              0x0f
  64
  65 /* FIFO Threshold Register */
  66 #define CD1190_FTR              0x08
  67
  68 /* Global Config Register */
  69 #define CD1190_GCR              0x0a
  70 #define CD1190_GCR_NOACK        (1<<2) /* NO-ACK handshaking */
  71 #define CD1190_GCR_MODE         (1<<1) /* Peripheral/Controller Mode */
  72 #define CD1190_GCR_DIR          (1<<0) /* Input/Output Direction */
  73
  74 /* defines for variable CD1190_IO */
  75 #define CD1190_CO               0x00
  76 #define CD1190_CI               0x01
  77 #define CD1190_PO               0x02
  78 #define CD1190_PI               0x03
  79
  80 /* Interrupt Config Register */
  81 #define CD1190_ICR              0x01
  82 #define CD1190_ICR_ENABLE       (1<<7) /* Enable Interrupts */
  83 #define CD1190_ICR_ACK          (1<<3) /* Enable: Unsolicited ACK */
  84 #define CD1190_ICR_FIFO         (1<<2) /* Enable: FIFO Thresh/Time */
  85 #define CD1190_ICR_SIGNAL       (1<<1) /* Enable: Signal Status */
  86 #define CD1190_ICR_TIMER        (1<<0) /* Enable: Timer Expired */
  87
  88 /* Interrupt Status Register */
  89 #define CD1190_ISR              0x0c
  90 #define CD1190_ISR_INTERRUPT    (1<<7) /* Interrupt Has Occurred */
  91 #define CD1190_ISR_ACK          (1<<3) /* Unsolicited ACK */
  92 #define CD1190_ISR_FIFO         (1<<2) /* FIFO Thresh/Time */
  93 #define CD1190_ISR_SIGNAL       (1<<1) /* Signal Status */
  94 #define CD1190_ISR_TIMER        (1<<0) /* Timer Expired */
  95
  96 /* Interrupt Vector Register */
  97 #define CD1190_IVR              0x00
  98
  99 /* Parallel Status Register */
 100 #define CD1190_PSR              0x1c
 101 #define CD1190_PSR_ENP          (1<<7) /* Parallel Enabled */
 102 #define CD1190_PSR_BUSY         (1<<6) /* Parallel Busy */
 103 #define CD1190_PSR_ACK          (1<<5) /* Parallel Acknowledge */
 104 #define CD1190_PSR_STATUS       (CD1190_PSR_ENP | CD1190_PSR_BUSY)
 105 #define CD1190_PSR_NORMAL       CD1190_PSR_ENP
 106
 107 /* Signal Control Register */
 108 #define CD1190_SCR              0x1e
 109 #define CD1190_SCR_WRRD         (1<<7) /* Read Only: Write/Read */
 110 #define CD1190_SCR_IP3          (1<<6) /* Read Only: Input Line 3 */
 111 #define CD1190_SCR_IP2          (1<<5) /* Read Only: Input Line 2 */
 112 #define CD1190_SCR_IP1          (1<<4) /* Read Only: Input Line 1 */
 113 #define CD1190_SCR_WR_WRRD      (1<<3) /* Write/Read */
 114 #define CD1190_SCR_OP3          (1<<2) /* Output Line 3 */
 115 #define CD1190_SCR_OP2          (1<<1) /* Output Line 2 */
 116 #define CD1190_SCR_OP1          (1<<0) /* Output Line 1 */
 117
 118 /* Input signals
 119  *
 120  *      IP3     -       *ERROR
 121  *      IP2     -       PAPER EMPTY / FAULT
 122  *      IP1     -       SELECT
 123  *      WRRD    -       AFD
 124  *      OP3     -       SLIN
 125  *      OP2     -       *INIT / *RESET
 126  *      OP1     -       N/A
 127  */
 128 #define CD1190_SCR_NOERROR      CD1190_SCR_IP3 /* Printer Error (active low) */
 129 #define CD1190_SCR_PE           CD1190_SCR_IP2 /* Paper Empty */
 130 #define CD1190_SCR_SELECT       CD1190_SCR_IP1 /* Printer Select */
 131
 132 #define CD1190_SCR_STATUS       (CD1190_SCR_IP3 | CD1190_SCR_IP2 | CD1190_SCR_IP1)
 133
 134 /* Outout signals - Active High?
 135  *
 136  *      IP3     -       SLIN
 137  *      IP2     -       *INIT / *RESET
 138  *      IP1     -       N/A
 139  *      WRRD    -       AFD
 140  *      OP3     -       *ERROR
 141  *      OP2     -       SELECT
 142  *      OP1     -       PAPER EMPTY / FAULT
 143  */
 144 #define CD1190_SCR_RESET        CD1190_SCR_OP2
 145 #define CD1190_SCR_SEL_IN       CD1190_SCR_OP3
 146
 147 /* Specification Register ZEROes */
 148 #define CD1190_SR0              0x06
 149 #define CD1190_SR0_WRRD         (1<<7) /* WR/RD 1 to 0 Change */
 150 #define CD1190_SR0_IP3          (1<<6) /* IP3 1 to 0 Change */
 151 #define CD1190_SR0_IP2          (1<<5) /* IP2 1 to 0 Change */
 152 #define CD1190_SR0_IP1          (1<<4) /* IP1 1 to 0 Change */
 153
 154 /* Specification Register ONEs */
 155 #define CD1190_SR1              0x07
 156 #define CD1190_SR1_WRRD         (1<<7) /* WR/RD 0 to 1 Change */
 157 #define CD1190_SR1_IP3          (1<<6) /* IP3 0 to 1 Change */
 158 #define CD1190_SR1_IP2          (1<<5) /* IP2 0 to 1 Change */
 159 #define CD1190_SR1_IP1          (1<<4) /* IP1 0 to 1 Change */
 160
 161 /* Signal Status Register */
 162 #define CD1190_SSR              0x0d
 163 #define CD1190_SSR_WRRD         (1<<7) /* WR/RD Change */
 164 #define CD1190_SSR_IP3          (1<<6) /* IP3 Change */
 165 #define CD1190_SSR_IP2          (1<<5) /* IP2 Change */
 166 #define CD1190_SSR_IP1          (1<<4) /* IP1 Change */
 167
 168 /* Strobe Width Register */
 169 #define CD1190_SWR              0x02
 170
 171 /* Timer Multipler Register */
 172 #define CD1190_TMR              0x05
 173
 174 /* Timer Prescale Register */
 175 #define CD1190_TPR              0x04