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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / ic / cs89x0.c
blob3a51fb16c6eb633f8222b9e0ea6843a2432590ad
1 /* $NetBSD: cs89x0.c,v 1.28 2009/09/22 16:44:08 tsutsui Exp $ */
2
3 /*
4 * Copyright (c) 2004 Christopher Gilbert
5 * All rights reserved.
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the company nor the name of the author may be used to
13 * endorse or promote products derived from this software without specific
14 * prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * Copyright 1997
31 * Digital Equipment Corporation. All rights reserved.
32 *
33 * This software is furnished under license and may be used and
34 * copied only in accordance with the following terms and conditions.
35 * Subject to these conditions, you may download, copy, install,
36 * use, modify and distribute this software in source and/or binary
37 * form. No title or ownership is transferred hereby.
38 *
39 * 1) Any source code used, modified or distributed must reproduce
40 * and retain this copyright notice and list of conditions as
41 * they appear in the source file.
42 *
43 * 2) No right is granted to use any trade name, trademark, or logo of
44 * Digital Equipment Corporation. Neither the "Digital Equipment
45 * Corporation" name nor any trademark or logo of Digital Equipment
46 * Corporation may be used to endorse or promote products derived
47 * from this software without the prior written permission of
48 * Digital Equipment Corporation.
49 *
50 * 3) This software is provided "AS-IS" and any express or implied
51 * warranties, including but not limited to, any implied warranties
52 * of merchantability, fitness for a particular purpose, or
53 * non-infringement are disclaimed. In no event shall DIGITAL be
54 * liable for any damages whatsoever, and in particular, DIGITAL
55 * shall not be liable for special, indirect, consequential, or
56 * incidental damages or damages for lost profits, loss of
57 * revenue or loss of use, whether such damages arise in contract,
58 * negligence, tort, under statute, in equity, at law or otherwise,
59 * even if advised of the possibility of such damage.
60 */
61
62 /*
63 **++
64 ** FACILITY
65 **
66 ** Device Driver for the Crystal CS8900 ISA Ethernet Controller.
67 **
68 ** ABSTRACT
69 **
70 ** This module provides standard ethernet access for INET protocols
71 ** only.
72 **
73 ** AUTHORS
74 **
75 ** Peter Dettori SEA - Software Engineering.
76 **
77 ** CREATION DATE:
78 **
79 ** 13-Feb-1997.
80 **
81 ** MODIFICATION HISTORY (Digital):
82 **
83 ** Revision 1.27 1998/01/20 17:59:40 cgd
84 ** update for moved headers
85 **
86 ** Revision 1.26 1998/01/12 19:29:36 cgd
87 ** use arm32/isa versions of isadma code.
88 **
89 ** Revision 1.25 1997/12/12 01:35:27 cgd
90 ** convert to use new arp code (from Brini)
91 **
92 ** Revision 1.24 1997/12/10 22:31:56 cgd
93 ** trim some fat (get rid of ability to explicitly supply enet addr, since
94 ** it was never used and added a bunch of code which really doesn't belong in
95 ** an enet driver), and clean up slightly.
96 **
97 ** Revision 1.23 1997/10/06 16:42:12 cgd
98 ** copyright notices
99 **
100 ** Revision 1.22 1997/06/20 19:38:01 chaiken
101 ** fixes some smartcard problems
102 **
103 ** Revision 1.21 1997/06/10 02:56:20 grohn
104 ** Added call to ledNetActive
105 **
106 ** Revision 1.20 1997/06/05 00:47:06 dettori
107 ** Changed cs_process_rx_dma to reset and re-initialise the
108 ** ethernet chip when DMA gets out of sync, or mbufs
109 ** can't be allocated.
110 **
111 ** Revision 1.19 1997/06/03 03:09:58 dettori
112 ** Turn off sc_txbusy flag when a transmit underrun
113 ** occurs.
114 **
115 ** Revision 1.18 1997/06/02 00:04:35 dettori
116 ** redefined the transmit table to get around the nfs_timer bug while we are
117 ** looking into it further.
118 **
119 ** Also changed interrupts from EDGE to LEVEL.
120 **
121 ** Revision 1.17 1997/05/27 23:31:01 dettori
122 ** Pulled out changes to DMAMODE defines.
123 **
124 ** Revision 1.16 1997/05/23 04:25:16 cgd
125 ** reformat log so it fits in 80cols
126 **
127 ** Revision 1.15 1997/05/23 04:22:18 cgd
128 ** remove the existing copyright notice (which Peter Dettori indicated
129 ** was incorrect, copied from an existing NetBSD file only so that the
130 ** file would have a copyright notice on it, and which he'd intended to
131 ** replace). Replace it with a Digital copyright notice, cloned from
132 ** ess.c. It's not really correct either (it indicates that the source
133 ** is Digital confidential!), but is better than nothing and more
134 ** correct than what was there before.
135 **
136 ** Revision 1.14 1997/05/23 04:12:50 cgd
137 ** use an adaptive transmit start algorithm: start by telling the chip
138 ** to start transmitting after 381 bytes have been fed to it. if that
139 ** gets transmit underruns, ramp down to 1021 bytes then "whole
140 ** packet." If successful at a given level for a while, try the next
141 ** more agressive level. This code doesn't ever try to start
142 ** transmitting after 5 bytes have been sent to the NIC, because
143 ** that underruns rather regularly. The back-off and ramp-up mechanism
144 ** could probably be tuned a little bit, but this works well enough to
145 ** support > 1MB/s transmit rates on a clear ethernet (which is about
146 ** 20-25% better than the driver had previously been getting).
147 **
148 ** Revision 1.13 1997/05/22 21:06:54 cgd
149 ** redo cs_copy_tx_frame() from scratch. It had a fatal flaw: it was blindly
150 ** casting from u_int8_t * to u_int16_t * without worrying about alignment
151 ** issues. This would cause bogus data to be spit out for mbufs with
152 ** misaligned data. For instance, it caused the following bits to appear
153 ** on the wire:
154 ** ... etBND 1S2C .SHA(K) R ...
155 ** 11112222333344445555
156 ** which should have appeared as:
157 ** ... NetBSD 1.2C (SHARK) ...
158 ** 11112222333344445555
159 ** Note the apparent 'rotate' of the bytes in the word, which was due to
160 ** incorrect unaligned accesses. This data corruption was the cause of
161 ** incoming telnet/rlogin hangs.
162 **
163 ** Revision 1.12 1997/05/22 01:55:32 cgd
164 ** reformat log so it fits in 80cols
165 **
166 ** Revision 1.11 1997/05/22 01:50:27 cgd
167 ** * enable input packet address checking in the BPF+IFF_PROMISCUOUS case,
168 ** so packets aimed at other hosts don't get sent to ether_input().
169 ** * Add a static const char *rcsid initialized with an RCS Id tag, so that
170 ** you can easily tell (`strings`) what version of the driver is in your
171 ** kernel binary.
172 ** * get rid of ether_cmp(). It was inconsistently used, not necessarily
173 ** safe, and not really a performance win anyway. (It was only used when
174 ** setting up the multicast logical address filter, which is an
175 ** infrequent event. It could have been used in the IFF_PROMISCUOUS
176 ** address check above, but the benefit of it vs. memcmp would be
177 ** inconsequential, there.) Use memcmp() instead.
178 ** * restructure csStartOuput to avoid the following bugs in the case where
179 ** txWait was being set:
180 ** * it would accidentally drop the outgoing packet if told to wait
181 ** but the outgoing packet queue was empty.
182 ** * it would bpf_mtap() the outgoing packet multiple times (once for
183 ** each time it was told to wait), and would also recalculate
184 ** the length of the outgoing packet each time it was told to
185 ** wait.
186 ** While there, rename txWait to txLoop, since with the new structure of
187 ** the code, the latter name makes more sense.
188 **
189 ** Revision 1.10 1997/05/19 02:03:20 cgd
190 ** Set RX_CTL in cs_set_ladr_filt(), rather than cs_initChip(). cs_initChip()
191 ** is the only caller of cs_set_ladr_filt(), and always calls it, so this
192 ** ends up being logically the same. In cs_set_ladr_filt(), if IFF_PROMISC
193 ** is set, enable promiscuous mode (and set IFF_ALLMULTI), otherwise behave
194 ** as before.
195 **
196 ** Revision 1.9 1997/05/19 01:45:37 cgd
197 ** create a new function, cs_ether_input(), which does received-packet
198 ** BPF and ether_input processing. This code used to be in three places,
199 ** and centralizing it will make adding IFF_PROMISC support much easier.
200 ** Also, in cs_copy_tx_frame(), put it some (currently disabled) code to
201 ** do copies with bus_space_write_region_2(). It's more correct, and
202 ** potentially more efficient. That function needs to be gutted (to
203 ** deal properly with alignment issues, which it currently does wrong),
204 ** however, and the change doesn't gain much, so there's no point in
205 ** enabling it now.
206 **
207 ** Revision 1.8 1997/05/19 01:17:10 cgd
208 ** fix a comment re: the setting of the TxConfig register. Clean up
209 ** interface counter maintenance (make it use standard idiom).
210 **
211 **--
212 */
213
214 #include <sys/cdefs.h>
215 __KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.28 2009/09/22 16:44:08 tsutsui Exp $");
216
217 #include "opt_inet.h"
218
219 #include <sys/param.h>
220 #include <sys/systm.h>
221 #include <sys/mbuf.h>
222 #include <sys/syslog.h>
223 #include <sys/socket.h>
224 #include <sys/device.h>
225 #include <sys/malloc.h>
226 #include <sys/ioctl.h>
227 #include <sys/errno.h>
228
229 #include "rnd.h"
230 #if NRND > 0
231 #include <sys/rnd.h>
232 #endif
233
234 #include <net/if.h>
235 #include <net/if_ether.h>
236 #include <net/if_media.h>
237 #ifdef INET
238 #include <netinet/in.h>
239 #include <netinet/if_inarp.h>
240 #endif
241
242 #include "bpfilter.h"
243 #if NBPFILTER > 0
244 #include <net/bpf.h>
245 #include <net/bpfdesc.h>
246 #endif
247
248 #include <uvm/uvm_extern.h>
249
250 #include <sys/bus.h>
251 #include <sys/intr.h>
252
253 #include <dev/ic/cs89x0reg.h>
254 #include <dev/ic/cs89x0var.h>
255
256 #ifdef SHARK
257 #include <shark/shark/sequoia.h>
258 #endif
259
260 /*
261 * MACRO DEFINITIONS
262 */
263 #define CS_OUTPUT_LOOP_MAX 100 /* max times round notorious tx loop */
264
265 /*
266 * FUNCTION PROTOTYPES
267 */
268 static void cs_get_default_media(struct cs_softc *);
269 static int cs_get_params(struct cs_softc *);
270 static int cs_get_enaddr(struct cs_softc *);
271 static int cs_reset_chip(struct cs_softc *);
272 static void cs_reset(struct cs_softc *);
273 static int cs_ioctl(struct ifnet *, u_long, void *);
274 static void cs_initChip(struct cs_softc *);
275 static void cs_buffer_event(struct cs_softc *, u_int16_t);
276 static void cs_transmit_event(struct cs_softc *, u_int16_t);
277 static void cs_receive_event(struct cs_softc *, u_int16_t);
278 static void cs_process_receive(struct cs_softc *);
279 static void cs_process_rx_early(struct cs_softc *);
280 static void cs_start_output(struct ifnet *);
281 static void cs_copy_tx_frame(struct cs_softc *, struct mbuf *);
282 static void cs_set_ladr_filt(struct cs_softc *, struct ethercom *);
283 static u_int16_t cs_hash_index(char *);
284 static void cs_counter_event(struct cs_softc *, u_int16_t);
285
286 static int cs_mediachange(struct ifnet *);
287 static void cs_mediastatus(struct ifnet *, struct ifmediareq *);
288
289 static bool cs_shutdown(device_t, int);
290 static int cs_enable(struct cs_softc *);
291 static void cs_disable(struct cs_softc *);
292 static void cs_stop(struct ifnet *, int);
293 static int cs_scan_eeprom(struct cs_softc *);
294 static int cs_read_pktpg_from_eeprom(struct cs_softc *, int, u_int16_t *);
295
296
297 /*
298 * GLOBAL DECLARATIONS
299 */
300
301 /*
302 * Xmit-early table.
303 *
304 * To get better performance, we tell the chip to start packet
305 * transmission before the whole packet is copied to the chip.
306 * However, this can fail under load. When it fails, we back off
307 * to a safer setting for a little while.
308 *
309 * txcmd is the value of txcmd used to indicate when to start transmission.
310 * better is the next 'better' state in the table.
311 * better_count is the number of output packets before transition to the
312 * better state.
313 * worse is the next 'worse' state in the table.
314 *
315 * Transition to the next worse state happens automatically when a
316 * transmittion underrun occurs.
317 */
318 struct cs_xmit_early {
319 u_int16_t txcmd;
320 int better;
321 int better_count;
322 int worse;
323 } cs_xmit_early_table[3] = {
324 { TX_CMD_START_381, 0, INT_MAX, 1, },
325 { TX_CMD_START_1021, 0, 50000, 2, },
326 { TX_CMD_START_ALL, 1, 5000, 2, },
327 };
328
329 int cs_default_media[] = {
330 IFM_ETHER|IFM_10_2,
331 IFM_ETHER|IFM_10_5,
332 IFM_ETHER|IFM_10_T,
333 IFM_ETHER|IFM_10_T|IFM_FDX,
334 };
335 int cs_default_nmedia = sizeof(cs_default_media) / sizeof(cs_default_media[0]);
336
337 int
338 cs_attach(struct cs_softc *sc, u_int8_t *enaddr, int *media,
339 int nmedia, int defmedia)
340 {
341 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
342 const char *chipname, *medname;
343 u_int16_t reg;
344 int i;
345
346 /* Start out in IO mode */
347 sc->sc_memorymode = FALSE;
348
349 /* make sure we're right */
350 for (i = 0; i < 10000; i++) {
351 reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM);
352 if (reg == EISA_NUM_CRYSTAL) {
353 break;
354 }
355 }
356 if (i == 10000) {
357 aprint_error_dev(sc->sc_dev, "wrong id(0x%x)\n", reg);
358 return 1; /* XXX should panic? */
359 }
360
361 reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID);
362 sc->sc_prodid = reg & PROD_ID_MASK;
363 sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8;
364
365 switch (sc->sc_prodid) {
366 case PROD_ID_CS8900:
367 chipname = "CS8900";
368 break;
369 case PROD_ID_CS8920:
370 chipname = "CS8920";
371 break;
372 case PROD_ID_CS8920M:
373 chipname = "CS8920M";
374 break;
375 default:
376 panic("cs_attach: impossible");
377 }
378
379 /*
380 * the first thing to do is check that the mbuf cluster size is
381 * greater than the MTU for an ethernet frame. The code depends on
382 * this and to port this to a OS where this was not the case would
383 * not be straightforward.
384 *
385 * we need 1 byte spare because our
386 * packet read loop can overrun.
387 * and we may need pad bytes to align ip header.
388 */
389 if (MCLBYTES < ETHER_MAX_LEN + 1 +
390 ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header)) {
391 printf("%s: MCLBYTES too small for Ethernet frame\n",
392 device_xname(sc->sc_dev));
393 return 1;
394 }
395
396 /* Start out not transmitting */
397 sc->sc_txbusy = FALSE;
398
399 /* Set up early transmit threshhold */
400 sc->sc_xe_ent = 0;
401 sc->sc_xe_togo = cs_xmit_early_table[sc->sc_xe_ent].better_count;
402
403 /* Initialize ifnet structure. */
404 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
405 ifp->if_softc = sc;
406 ifp->if_start = cs_start_output;
407 ifp->if_init = cs_init;
408 ifp->if_ioctl = cs_ioctl;
409 ifp->if_stop = cs_stop;
410 ifp->if_watchdog = NULL; /* no watchdog at this stage */
411 ifp->if_flags = IFF_SIMPLEX | IFF_NOTRAILERS |
412 IFF_BROADCAST | IFF_MULTICAST;
413 IFQ_SET_READY(&ifp->if_snd);
414
415 /* Initialize ifmedia structures. */
416 ifmedia_init(&sc->sc_media, 0, cs_mediachange, cs_mediastatus);
417
418 if (media != NULL) {
419 for (i = 0; i < nmedia; i++)
420 ifmedia_add(&sc->sc_media, media[i], 0, NULL);
421 ifmedia_set(&sc->sc_media, defmedia);
422 } else {
423 for (i = 0; i < cs_default_nmedia; i++)
424 ifmedia_add(&sc->sc_media, cs_default_media[i],
425 0, NULL);
426 cs_get_default_media(sc);
427 }
428
429 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) {
430 if (cs_scan_eeprom(sc) == CS_ERROR) {
431 /* failed to scan the eeprom, pretend there isn't an eeprom */
432 aprint_error_dev(sc->sc_dev, "unable to scan EEPROM\n");
433 sc->sc_cfgflags |= CFGFLG_NOT_EEPROM;
434 }
435 }
436
437 if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) {
438 /* Get parameters from the EEPROM */
439 if (cs_get_params(sc) == CS_ERROR) {
440 aprint_error_dev(sc->sc_dev,
441 "unable to get settings from EEPROM\n");
442 return 1;
443 }
444 }
445
446 if (enaddr != NULL)
447 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr));
448 else if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) {
449 /* Get and store the Ethernet address */
450 if (cs_get_enaddr(sc) == CS_ERROR) {
451 aprint_error_dev(sc->sc_dev,
452 "unable to read Ethernet address\n");
453 return 1;
454 }
455 } else {
456 #if 1
457 int j;
458 uint v;
459
460 for (j = 0; j < 6; j += 2) {
461 v = CS_READ_PACKET_PAGE(sc, PKTPG_IND_ADDR + j);
462 sc->sc_enaddr[j + 0] = v;
463 sc->sc_enaddr[j + 1] = v >> 8;
464 }
465 #else
466 printf("%s: no Ethernet address!\n", device_xname(sc->sc_dev));
467 return 1;
468 #endif
469 }
470
471 switch (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media)) {
472 case IFM_10_2:
473 medname = "BNC";
474 break;
475 case IFM_10_5:
476 medname = "AUI";
477 break;
478 case IFM_10_T:
479 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX)
480 medname = "UTP <full-duplex>";
481 else
482 medname = "UTP";
483 break;
484 default:
485 panic("cs_attach: impossible");
486 }
487 printf("%s: %s rev. %c, address %s, media %s\n",
488 device_xname(sc->sc_dev),
489 chipname, sc->sc_prodrev + 'A', ether_sprintf(sc->sc_enaddr),
490 medname);
491
492 if (sc->sc_dma_attach)
493 (*sc->sc_dma_attach)(sc);
494
495 /* Attach the interface. */
496 if_attach(ifp);
497 ether_ifattach(ifp, sc->sc_enaddr);
498
499 #if NRND > 0
500 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
501 RND_TYPE_NET, 0);
502 #endif
503 sc->sc_cfgflags |= CFGFLG_ATTACHED;
504
505 if (pmf_device_register1(sc->sc_dev, NULL, NULL, cs_shutdown))
506 pmf_class_network_register(sc->sc_dev, ifp);
507 else
508 aprint_error_dev(sc->sc_dev,
509 "couldn't establish power handler\n");
510
511 /* Reset the chip */
512 if (cs_reset_chip(sc) == CS_ERROR) {
513 aprint_error_dev(sc->sc_dev, "reset failed\n");
514 cs_detach(sc);
515 return 1;
516 }
517
518 return 0;
519 }
520
521 int
522 cs_detach(struct cs_softc *sc)
523 {
524 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
525
526 if (sc->sc_cfgflags & CFGFLG_ATTACHED) {
527 #if NRND > 0
528 rnd_detach_source(&sc->rnd_source);
529 #endif
530 ether_ifdetach(ifp);
531 if_detach(ifp);
532 sc->sc_cfgflags &= ~CFGFLG_ATTACHED;
533 }
534
535 #if 0
536 /*
537 * XXX not necessary
538 */
539 if (sc->sc_cfgflags & CFGFLG_DMA_MODE) {
540 isa_dmamem_unmap(sc->sc_ic, sc->sc_drq, sc->sc_dmabase, sc->sc_dmasize);
541 isa_dmamem_free(sc->sc_ic, sc->sc_drq, sc->sc_dmaaddr, sc->sc_dmasize);
542 isa_dmamap_destroy(sc->sc_ic, sc->sc_drq);
543 sc->sc_cfgflags &= ~CFGFLG_DMA_MODE;
544 }
545 #endif
546
547 pmf_device_deregister(sc->sc_dev);
548
549 return 0;
550 }
551
552 bool
553 cs_shutdown(device_t self, int howto)
554 {
555 struct cs_softc *sc;
556
557 sc = device_private(self);
558 cs_reset(sc);
559
560 return true;
561 }
562
563 void
564 cs_get_default_media(struct cs_softc *sc)
565 {
566 u_int16_t adp_cfg, xmit_ctl;
567
568 if (cs_verify_eeprom(sc) == CS_ERROR) {
569 aprint_error_dev(sc->sc_dev,
570 "cs_get_default_media: EEPROM missing or bad\n");
571 goto fakeit;
572 }
573
574 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adp_cfg) == CS_ERROR) {
575 aprint_error_dev(sc->sc_dev,
576 "unable to read adapter config from EEPROM\n");
577 goto fakeit;
578 }
579
580 if (cs_read_eeprom(sc, EEPROM_XMIT_CTL, &xmit_ctl) == CS_ERROR) {
581 aprint_error_dev(sc->sc_dev,
582 "unable to read transmit control from EEPROM\n");
583 goto fakeit;
584 }
585
586 switch (adp_cfg & ADPTR_CFG_MEDIA) {
587 case ADPTR_CFG_AUI:
588 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_5);
589 break;
590 case ADPTR_CFG_10BASE2:
591 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_2);
592 break;
593 case ADPTR_CFG_10BASET:
594 default:
595 if (xmit_ctl & XMIT_CTL_FDX)
596 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX);
597 else
598 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T);
599 break;
600 }
601 return;
602
603 fakeit:
604 aprint_error_dev(sc->sc_dev,
605 "WARNING: default media setting may be inaccurate\n");
606 /* XXX Arbitrary... */
607 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T);
608 }
609
610 /*
611 * cs_scan_eeprom
612 *
613 * Attempt to take a complete copy of the eeprom into main memory.
614 * this will allow faster parsing of the eeprom data.
615 *
616 * Only tested against a 8920M's eeprom, but the data sheet for the
617 * 8920A indicates that is uses the same layout.
618 */
619 int
620 cs_scan_eeprom(struct cs_softc *sc)
621 {
622 u_int16_t result;
623 int i;
624 int eeprom_size;
625 u_int8_t checksum = 0;
626
627 if (cs_verify_eeprom(sc) == CS_ERROR) {
628 aprint_error_dev(sc->sc_dev,
629 "cs_scan_params: EEPROM missing or bad\n");
630 return (CS_ERROR);
631 }
632
633 /*
634 * read the 0th word from the eeprom, it will tell us the length
635 * and if the eeprom is valid
636 */
637 cs_read_eeprom(sc, 0, &result);
638
639 /* check the eeprom signature */
640 if ((result & 0xE000) != 0xA000) {
641 /* empty eeprom */
642 return (CS_ERROR);
643 }
644
645 /*
646 * take the eeprom size (note the read value doesn't include the header
647 * word)
648 */
649 eeprom_size = (result & 0xff) + 2;
650
651 sc->eeprom_data = malloc(eeprom_size, M_DEVBUF, M_WAITOK);
652 if (sc->eeprom_data == NULL) {
653 /* no memory, treat this as if there's no eeprom */
654 return (CS_ERROR);
655 }
656
657 sc->eeprom_size = eeprom_size;
658
659 /* read the eeprom into the buffer, also calculate the checksum */
660 for (i = 0; i < (eeprom_size >> 1); i++) {
661 cs_read_eeprom(sc, i, &(sc->eeprom_data[i]));
662 checksum += (sc->eeprom_data[i] & 0xff00) >> 8;
663 checksum += (sc->eeprom_data[i] & 0x00ff);
664 }
665
666 /*
667 * validate checksum calculation, the sum of all the bytes should be 0,
668 * as the high byte of the last word is the 2's complement of the
669 * sum to that point.
670 */
671 if (checksum != 0) {
672 aprint_error_dev(sc->sc_dev, "eeprom checksum failure\n");
673 return (CS_ERROR);
674 }
675
676 return (CS_OK);
677 }
678
679 static int
680 cs_read_pktpg_from_eeprom(struct cs_softc *sc, int pktpg, u_int16_t *pValue)
681 {
682 int x, maxword;
683
684 /* Check that we have eeprom data */
685 if ((sc->eeprom_data == NULL) || (sc->eeprom_size < 2))
686 return (CS_ERROR);
687
688 /*
689 * We only want to read the data words, the last word contains the
690 * checksum
691 */
692 maxword = (sc->eeprom_size - 2) >> 1;
693
694 /* start 1 word in, as the first word is the length and signature */
695 x = 1;
696
697 while ( x < (maxword)) {
698 u_int16_t header;
699 int group_size;
700 int offset;
701 int offset_max;
702
703 /* read in the group header word */
704 header = sc->eeprom_data[x];
705 x++; /* skip group header */
706
707 /*
708 * size of group in words is in the top 4 bits, note that it
709 * is one less than the number of words
710 */
711 group_size = header & 0xF000;
712
713 /*
714 * CS8900 Data sheet says this should be 0x01ff,
715 * but my cs8920 eeprom has higher offsets,
716 * perhaps the 8920 allows higher offsets, otherwise
717 * it's writing to places that it shouldn't
718 */
719 /* work out the offsets this group covers */
720 offset = header & 0x0FFF;
721 offset_max = offset + (group_size << 1);
722
723 /* check if the pkgpg we're after is in this group */
724 if ((offset <= pktpg) && (pktpg <= offset_max)) {
725 /* the pkgpg value we want is in here */
726 int eeprom_location;
727
728 eeprom_location = ((pktpg - offset) >> 1) ;
729
730 *pValue = sc->eeprom_data[x + eeprom_location];
731 return (CS_OK);
732 } else {
733 /* skip this group (+ 1 for first entry) */
734 x += group_size + 1;
735 }
736 }
737
738 /*
739 * if we've fallen out here then we don't have a value in the EEPROM
740 * for this pktpg so return an error
741 */
742 return (CS_ERROR);
743 }
744
745 int
746 cs_get_params(struct cs_softc *sc)
747 {
748 u_int16_t isaConfig;
749 u_int16_t adapterConfig;
750
751 if (cs_verify_eeprom(sc) == CS_ERROR) {
752 aprint_error_dev(sc->sc_dev,
753 "cs_get_params: EEPROM missing or bad\n");
754 return (CS_ERROR);
755 }
756
757 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) {
758 /* Get ISA configuration from the EEPROM */
759 if (cs_read_pktpg_from_eeprom(sc, PKTPG_BUS_CTL, &isaConfig)
760 == CS_ERROR) {
761 /* eeprom doesn't have this value, use data sheet default */
762 isaConfig = 0x0017;
763 }
764
765 /* Get adapter configuration from the EEPROM */
766 if (cs_read_pktpg_from_eeprom(sc, PKTPG_SELF_CTL, &adapterConfig)
767 == CS_ERROR) {
768 /* eeprom doesn't have this value, use data sheet default */
769 adapterConfig = 0x0015;
770 }
771
772 /* Copy the USE_SA flag */
773 if (isaConfig & BUS_CTL_USE_SA)
774 sc->sc_cfgflags |= CFGFLG_USE_SA;
775
776 /* Copy the IO Channel Ready flag */
777 if (isaConfig & BUS_CTL_IOCHRDY)
778 sc->sc_cfgflags |= CFGFLG_IOCHRDY;
779
780 /* Copy the DC/DC Polarity flag */
781 if (adapterConfig & SELF_CTL_HCB1)
782 sc->sc_cfgflags |= CFGFLG_DCDC_POL;
783 } else {
784 /* Get ISA configuration from the EEPROM */
785 if (cs_read_eeprom(sc, EEPROM_ISA_CFG, &isaConfig) == CS_ERROR)
786 goto eeprom_bad;
787
788 /* Get adapter configuration from the EEPROM */
789 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adapterConfig) == CS_ERROR)
790 goto eeprom_bad;
791
792 /* Copy the USE_SA flag */
793 if (isaConfig & ISA_CFG_USE_SA)
794 sc->sc_cfgflags |= CFGFLG_USE_SA;
795
796 /* Copy the IO Channel Ready flag */
797 if (isaConfig & ISA_CFG_IOCHRDY)
798 sc->sc_cfgflags |= CFGFLG_IOCHRDY;
799
800 /* Copy the DC/DC Polarity flag */
801 if (adapterConfig & ADPTR_CFG_DCDC_POL)
802 sc->sc_cfgflags |= CFGFLG_DCDC_POL;
803 }
804
805 return (CS_OK);
806 eeprom_bad:
807 aprint_error_dev(sc->sc_dev,
808 "cs_get_params: unable to read from EEPROM\n");
809 return (CS_ERROR);
810 }
811
812 int
813 cs_get_enaddr(struct cs_softc *sc)
814 {
815 uint16_t myea[ETHER_ADDR_LEN / sizeof(uint16_t)];
816 int i;
817
818 if (cs_verify_eeprom(sc) == CS_ERROR) {
819 aprint_error_dev(sc->sc_dev,
820 "cs_get_enaddr: EEPROM missing or bad\n");
821 return (CS_ERROR);
822 }
823
824 /* Get Ethernet address from the EEPROM */
825 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) {
826 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR, &myea[0])
827 == CS_ERROR)
828 goto eeprom_bad;
829 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 2, &myea[1])
830 == CS_ERROR)
831 goto eeprom_bad;
832 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 4, &myea[2])
833 == CS_ERROR)
834 goto eeprom_bad;
835 } else {
836 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_H, &myea[0]) == CS_ERROR)
837 goto eeprom_bad;
838 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_M, &myea[1]) == CS_ERROR)
839 goto eeprom_bad;
840 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_L, &myea[2]) == CS_ERROR)
841 goto eeprom_bad;
842 }
843
844 for (i = 0; i < __arraycount(myea); i++) {
845 sc->sc_enaddr[i * 2 + 0] = myea[i];
846 sc->sc_enaddr[i * 2 + 1] = myea[i] >> 8;
847 }
848
849 return (CS_OK);
850
851 eeprom_bad:
852 aprint_error_dev(sc->sc_dev,
853 "cs_get_enaddr: unable to read from EEPROM\n");
854 return (CS_ERROR);
855 }
856
857 int
858 cs_reset_chip(struct cs_softc *sc)
859 {
860 int intState;
861 int x;
862
863 /* Disable interrupts at the CPU so reset command is atomic */
864 intState = splnet();
865
866 /*
867 * We are now resetting the chip
868 *
869 * A spurious interrupt is generated by the chip when it is reset. This
870 * variable informs the interrupt handler to ignore this interrupt.
871 */
872 sc->sc_resetting = TRUE;
873
874 /* Issue a reset command to the chip */
875 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, SELF_CTL_RESET);
876
877 /* Re-enable interrupts at the CPU */
878 splx(intState);
879
880 /* The chip is always in IO mode after a reset */
881 sc->sc_memorymode = FALSE;
882
883 /* If transmission was in progress, it is not now */
884 sc->sc_txbusy = FALSE;
885
886 /*
887 * there was a delay(125); here, but it seems uneccesary 125 usec is
888 * 1/8000 of a second, not 1/8 of a second. the data sheet advises
889 * 1/10 of a second here, but the SI_BUSY and INIT_DONE loops below
890 * should be sufficient.
891 */
892
893 /* Transition SBHE to switch chip from 8-bit to 16-bit */
894 IO_READ_1(sc, PORT_PKTPG_PTR + 0);
895 IO_READ_1(sc, PORT_PKTPG_PTR + 1);
896 IO_READ_1(sc, PORT_PKTPG_PTR + 0);
897 IO_READ_1(sc, PORT_PKTPG_PTR + 1);
898
899 /* Wait until the EEPROM is not busy */
900 for (x = 0; x < MAXLOOP; x++) {
901 if (!(CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY))
902 break;
903 }
904
905 if (x == MAXLOOP)
906 return CS_ERROR;
907
908 /* Wait until initialization is done */
909 for (x = 0; x < MAXLOOP; x++) {
910 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_INIT_DONE)
911 break;
912 }
913
914 if (x == MAXLOOP)
915 return CS_ERROR;
916
917 /* Reset is no longer in progress */
918 sc->sc_resetting = FALSE;
919
920 return CS_OK;
921 }
922
923 int
924 cs_verify_eeprom(struct cs_softc *sc)
925 {
926 u_int16_t self_status;
927
928 /* Verify that the EEPROM is present and OK */
929 self_status = CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST);
930 if (((self_status & SELF_ST_EEP_PRES) &&
931 (self_status & SELF_ST_EEP_OK)) == 0)
932 return (CS_ERROR);
933
934 return (CS_OK);
935 }
936
937 int
938 cs_read_eeprom(struct cs_softc *sc, int offset, u_int16_t *pValue)
939 {
940 int x;
941
942 /* Ensure that the EEPROM is not busy */
943 for (x = 0; x < MAXLOOP; x++) {
944 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) &
945 SELF_ST_SI_BUSY))
946 break;
947 }
948
949 if (x == MAXLOOP)
950 return (CS_ERROR);
951
952 /* Issue the command to read the offset within the EEPROM */
953 CS_WRITE_PACKET_PAGE_IO(sc, PKTPG_EEPROM_CMD,
954 offset | EEPROM_CMD_READ);
955
956 /* Wait until the command is completed */
957 for (x = 0; x < MAXLOOP; x++) {
958 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) &
959 SELF_ST_SI_BUSY))
960 break;
961 }
962
963 if (x == MAXLOOP)
964 return (CS_ERROR);
965
966 /* Get the EEPROM data from the EEPROM Data register */
967 *pValue = CS_READ_PACKET_PAGE_IO(sc, PKTPG_EEPROM_DATA);
968
969 return (CS_OK);
970 }
971
972 void
973 cs_initChip(struct cs_softc *sc)
974 {
975 u_int16_t busCtl;
976 u_int16_t selfCtl;
977 u_int16_t v;
978 u_int16_t isaId;
979 int i;
980 int media = IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media);
981
982 /* Disable reception and transmission of frames */
983 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL,
984 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) &
985 ~LINE_CTL_RX_ON & ~LINE_CTL_TX_ON);
986
987 /* Disable interrupt at the chip */
988 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
989 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & ~BUS_CTL_INT_ENBL);
990
991 /* If IOCHRDY is enabled then clear the bit in the busCtl register */
992 busCtl = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL);
993 if (sc->sc_cfgflags & CFGFLG_IOCHRDY) {
994 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
995 busCtl & ~BUS_CTL_IOCHRDY);
996 } else {
997 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
998 busCtl | BUS_CTL_IOCHRDY);
999 }
1000
1001 /* Set the Line Control register to match the media type */
1002 if (media == IFM_10_T)
1003 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_10BASET);
1004 else
1005 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY);
1006
1007 /*
1008 * Set the BSTATUS/HC1 pin to be used as HC1. HC1 is used to
1009 * enable the DC/DC converter
1010 */
1011 selfCtl = SELF_CTL_HC1E;
1012
1013 /* If the media type is 10Base2 */
1014 if (media == IFM_10_2) {
1015 /*
1016 * Enable the DC/DC converter if it has a low enable.
1017 */
1018 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) == 0)
1019 /*
1020 * Set the HCB1 bit, which causes the HC1 pin to go
1021 * low.
1022 */
1023 selfCtl |= SELF_CTL_HCB1;
1024 } else { /* Media type is 10BaseT or AUI */
1025 /*
1026 * Disable the DC/DC converter if it has a high enable.
1027 */
1028 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) != 0) {
1029 /*
1030 * Set the HCB1 bit, which causes the HC1 pin to go
1031 * low.
1032 */
1033 selfCtl |= SELF_CTL_HCB1;
1034 }
1035 }
1036 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, selfCtl);
1037
1038 /* enable normal link pulse */
1039 if (sc->sc_prodid == PROD_ID_CS8920 || sc->sc_prodid == PROD_ID_CS8920M)
1040 CS_WRITE_PACKET_PAGE(sc, PKTPG_AUTONEG_CTL, AUTOCTL_NLP_ENABLE);
1041
1042 /* Enable full-duplex, if appropriate */
1043 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX)
1044 CS_WRITE_PACKET_PAGE(sc, PKTPG_TEST_CTL, TEST_CTL_FDX);
1045
1046 /* RX_CTL set in cs_set_ladr_filt(), below */
1047
1048 /* enable all transmission interrupts */
1049 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, TX_CFG_ALL_IE);
1050
1051 /* Accept all receive interrupts */
1052 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, RX_CFG_ALL_IE);
1053
1054 /*
1055 * Configure Operational Modes
1056 *
1057 * I have turned off the BUF_CFG_RX_MISS_IE, to speed things up, this is
1058 * a better way to do it because the card has a counter which can be
1059 * read to update the RX_MISS counter. This saves many interrupts.
1060 *
1061 * I have turned on the tx and rx overflow interrupts to counter using
1062 * the receive miss interrupt. This is a better estimate of errors
1063 * and requires lower system overhead.
1064 */
1065 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, BUF_CFG_TX_UNDR_IE |
1066 BUF_CFG_RX_DMA_IE);
1067
1068 if (sc->sc_dma_chipinit)
1069 (*sc->sc_dma_chipinit)(sc);
1070
1071 /* If memory mode is enabled */
1072 if (sc->sc_cfgflags & CFGFLG_MEM_MODE) {
1073 /* If external logic is present for address decoding */
1074 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_EL_PRES) {
1075 /*
1076 * Program the external logic to decode address bits
1077 * SA20-SA23
1078 */
1079 CS_WRITE_PACKET_PAGE(sc, PKTPG_EEPROM_CMD,
1080 ((sc->sc_pktpgaddr & 0xffffff) >> 20) |
1081 EEPROM_CMD_ELSEL);
1082 }
1083
1084 /*
1085 * Write the packet page base physical address to the memory
1086 * base register.
1087 */
1088 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 0,
1089 sc->sc_pktpgaddr & 0xFFFF);
1090 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 2,
1091 sc->sc_pktpgaddr >> 16);
1092 busCtl = BUS_CTL_MEM_MODE;
1093
1094 /* tell the chip to read the addresses off the SA pins */
1095 if (sc->sc_cfgflags & CFGFLG_USE_SA) {
1096 busCtl |= BUS_CTL_USE_SA;
1097 }
1098 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
1099 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | busCtl);
1100
1101 /* We are in memory mode now! */
1102 sc->sc_memorymode = TRUE;
1103
1104 /*
1105 * wait here (10ms) for the chip to swap over. this is the
1106 * maximum time that this could take.
1107 */
1108 delay(10000);
1109
1110 /* Verify that we can read from the chip */
1111 isaId = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM);
1112
1113 /*
1114 * As a last minute sanity check before actually using mapped
1115 * memory we verify that we can read the isa number from the
1116 * chip in memory mode.
1117 */
1118 if (isaId != EISA_NUM_CRYSTAL) {
1119 aprint_error_dev(sc->sc_dev,
1120 "failed to enable memory mode\n");
1121 sc->sc_memorymode = FALSE;
1122 } else {
1123 /*
1124 * we are in memory mode so if we aren't using DMA,
1125 * then program the chip to interrupt early.
1126 */
1127 if ((sc->sc_cfgflags & CFGFLG_DMA_MODE) == 0) {
1128 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG,
1129 BUF_CFG_RX_DEST_IE |
1130 BUF_CFG_RX_MISS_OVER_IE |
1131 BUF_CFG_TX_COL_OVER_IE);
1132 }
1133 }
1134
1135 }
1136
1137 /* Put Ethernet address into the Individual Address register */
1138 for (i = 0; i < 6; i += 2) {
1139 v = sc->sc_enaddr[i + 0] | (sc->sc_enaddr[i + 1]) << 8;
1140 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + i, v);
1141 }
1142
1143 if (sc->sc_irq != -1) {
1144 /* Set the interrupt level in the chip */
1145 if (sc->sc_prodid == PROD_ID_CS8900) {
1146 if (sc->sc_irq == 5) {
1147 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 3);
1148 } else {
1149 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, (sc->sc_irq) - 10);
1150 }
1151 }
1152 else { /* CS8920 */
1153 CS_WRITE_PACKET_PAGE(sc, PKTPG_8920_INT_NUM, sc->sc_irq);
1154 }
1155 }
1156
1157 /* write the multicast mask to the address filter register */
1158 cs_set_ladr_filt(sc, &sc->sc_ethercom);
1159
1160 /* Enable reception and transmission of frames */
1161 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL,
1162 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) |
1163 LINE_CTL_RX_ON | LINE_CTL_TX_ON);
1164
1165 /* Enable interrupt at the chip */
1166 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
1167 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | BUS_CTL_INT_ENBL);
1168 }
1169
1170 int
1171 cs_init(struct ifnet *ifp)
1172 {
1173 int intState;
1174 int error = CS_OK;
1175 struct cs_softc *sc = ifp->if_softc;
1176
1177 if (cs_enable(sc))
1178 goto out;
1179
1180 cs_stop(ifp, 0);
1181
1182 intState = splnet();
1183
1184 #if 0
1185 /* Mark the interface as down */
1186 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_UP | IFF_RUNNING);
1187 #endif
1188
1189 #ifdef CS_DEBUG
1190 /* Enable debugging */
1191 sc->sc_ethercom.ec_if.if_flags |= IFF_DEBUG;
1192 #endif
1193
1194 /* Reset the chip */
1195 if ((error = cs_reset_chip(sc)) == CS_OK) {
1196 /* Initialize the chip */
1197 cs_initChip(sc);
1198
1199 /* Mark the interface as running */
1200 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING;
1201 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE;
1202 sc->sc_ethercom.ec_if.if_timer = 0;
1203
1204 /* Assume we have carrier until we are told otherwise. */
1205 sc->sc_carrier = 1;
1206 } else {
1207 aprint_error_dev(sc->sc_dev, "unable to reset chip\n");
1208 }
1209
1210 splx(intState);
1211 out:
1212 if (error == CS_OK)
1213 return 0;
1214 return EIO;
1215 }
1216
1217 void
1218 cs_set_ladr_filt(struct cs_softc *sc, struct ethercom *ec)
1219 {
1220 struct ifnet *ifp = &ec->ec_if;
1221 struct ether_multi *enm;
1222 struct ether_multistep step;
1223 u_int16_t af[4];
1224 u_int16_t port, mask, index;
1225
1226 /*
1227 * Set up multicast address filter by passing all multicast addresses
1228 * through a crc generator, and then using the high order 6 bits as an
1229 * index into the 64 bit logical address filter. The high order bit
1230 * selects the word, while the rest of the bits select the bit within
1231 * the word.
1232 */
1233 if (ifp->if_flags & IFF_PROMISC) {
1234 /* accept all valid frames. */
1235 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL,
1236 RX_CTL_PROMISC_A | RX_CTL_RX_OK_A |
1237 RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A);
1238 ifp->if_flags |= IFF_ALLMULTI;
1239 return;
1240 }
1241
1242 /*
1243 * accept frames if a. crc valid, b. individual address match c.
1244 * broadcast address,and d. multicast addresses matched in the hash
1245 * filter
1246 */
1247 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL,
1248 RX_CTL_RX_OK_A | RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A);
1249
1250
1251 /*
1252 * start off with all multicast flag clear, set it if we need to
1253 * later, otherwise we will leave it.
1254 */
1255 ifp->if_flags &= ~IFF_ALLMULTI;
1256 af[0] = af[1] = af[2] = af[3] = 0x0000;
1257
1258 /*
1259 * Loop through all the multicast addresses unless we get a range of
1260 * addresses, in which case we will just accept all packets.
1261 * Justification for this is given in the next comment.
1262 */
1263 ETHER_FIRST_MULTI(step, ec, enm);
1264 while (enm != NULL) {
1265 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1266 sizeof enm->enm_addrlo)) {
1267 /*
1268 * We must listen to a range of multicast addresses.
1269 * For now, just accept all multicasts, rather than
1270 * trying to set only those filter bits needed to match
1271 * the range. (At this time, the only use of address
1272 * ranges is for IP multicast routing, for which the
1273 * range is big enough to require all bits set.)
1274 */
1275 ifp->if_flags |= IFF_ALLMULTI;
1276 af[0] = af[1] = af[2] = af[3] = 0xffff;
1277 break;
1278 } else {
1279 /*
1280 * we have got an individual address so just set that
1281 * bit.
1282 */
1283 index = cs_hash_index(enm->enm_addrlo);
1284
1285 /* Set the bit the Logical address filter. */
1286 port = (u_int16_t) (index >> 4);
1287 mask = (u_int16_t) (1 << (index & 0xf));
1288 af[port] |= mask;
1289
1290 ETHER_NEXT_MULTI(step, enm);
1291 }
1292 }
1293
1294 /* now program the chip with the addresses */
1295 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 0, af[0]);
1296 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 2, af[1]);
1297 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 4, af[2]);
1298 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 6, af[3]);
1299 return;
1300 }
1301
1302 u_int16_t
1303 cs_hash_index(char *addr)
1304 {
1305 uint32_t crc;
1306 uint16_t hash_code;
1307
1308 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
1309
1310 hash_code = crc >> 26;
1311 return (hash_code);
1312 }
1313
1314 void
1315 cs_reset(struct cs_softc *sc)
1316 {
1317
1318 /* Mark the interface as down */
1319 sc->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING;
1320
1321 /* Reset the chip */
1322 cs_reset_chip(sc);
1323 }
1324
1325 int
1326 cs_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1327 {
1328 struct cs_softc *sc = ifp->if_softc;
1329 struct ifreq *ifr = data;
1330 int state;
1331 int result;
1332
1333 state = splnet();
1334
1335 result = 0; /* only set if something goes wrong */
1336
1337 switch (cmd) {
1338 case SIOCGIFMEDIA:
1339 case SIOCSIFMEDIA:
1340 result = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
1341 break;
1342
1343 default:
1344 result = ether_ioctl(ifp, cmd, data);
1345 if (result == ENETRESET) {
1346 if (ifp->if_flags & IFF_RUNNING) {
1347 /*
1348 * Multicast list has changed. Set the
1349 * hardware filter accordingly.
1350 */
1351 cs_set_ladr_filt(sc, &sc->sc_ethercom);
1352 }
1353 result = 0;
1354 }
1355 break;
1356 }
1357
1358 splx(state);
1359
1360 return result;
1361 }
1362
1363 int
1364 cs_mediachange(struct ifnet *ifp)
1365 {
1366
1367 /*
1368 * Current media is already set up. Just reset the interface
1369 * to let the new value take hold.
1370 */
1371 cs_init(ifp);
1372 return (0);
1373 }
1374
1375 void
1376 cs_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
1377 {
1378 struct cs_softc *sc = ifp->if_softc;
1379
1380 /*
1381 * The currently selected media is always the active media.
1382 */
1383 ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media;
1384
1385 if (ifp->if_flags & IFF_UP) {
1386 /* Interface up, status is valid. */
1387 ifmr->ifm_status = IFM_AVALID |
1388 (sc->sc_carrier ? IFM_ACTIVE : 0);
1389 }
1390 else ifmr->ifm_status = 0;
1391 }
1392
1393 int
1394 cs_intr(void *arg)
1395 {
1396 struct cs_softc *sc = arg;
1397 u_int16_t Event;
1398 #if NRND > 0
1399 u_int16_t rndEvent;
1400 #endif
1401
1402 /*printf("cs_intr %p\n", sc);*/
1403 /* Ignore any interrupts that happen while the chip is being reset */
1404 if (sc->sc_resetting) {
1405 printf("%s: cs_intr: reset in progress\n",
1406 device_xname(sc->sc_dev));
1407 return 1;
1408 }
1409
1410 /* Read an event from the Interrupt Status Queue */
1411 if (sc->sc_memorymode)
1412 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ);
1413 else
1414 Event = CS_READ_PORT(sc, PORT_ISQ);
1415
1416 if ((Event & REG_NUM_MASK) == 0 || Event == 0xffff)
1417 return 0; /* not ours */
1418
1419 #if NRND > 0
1420 rndEvent = Event;
1421 #endif
1422
1423 /* Process all the events in the Interrupt Status Queue */
1424 while ((Event & REG_NUM_MASK) != 0 && Event != 0xffff) {
1425 /* Dispatch to an event handler based on the register number */
1426 switch (Event & REG_NUM_MASK) {
1427 case REG_NUM_RX_EVENT:
1428 cs_receive_event(sc, Event);
1429 break;
1430 case REG_NUM_TX_EVENT:
1431 cs_transmit_event(sc, Event);
1432 break;
1433 case REG_NUM_BUF_EVENT:
1434 cs_buffer_event(sc, Event);
1435 break;
1436 case REG_NUM_TX_COL:
1437 case REG_NUM_RX_MISS:
1438 cs_counter_event(sc, Event);
1439 break;
1440 default:
1441 printf("%s: unknown interrupt event 0x%x\n",
1442 device_xname(sc->sc_dev), Event);
1443 break;
1444 }
1445
1446 /* Read another event from the Interrupt Status Queue */
1447 if (sc->sc_memorymode)
1448 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ);
1449 else
1450 Event = CS_READ_PORT(sc, PORT_ISQ);
1451 }
1452
1453 /* have handled the interrupt */
1454 #if NRND > 0
1455 rnd_add_uint32(&sc->rnd_source, rndEvent);
1456 #endif
1457 return 1;
1458 }
1459
1460 void
1461 cs_counter_event(struct cs_softc *sc, u_int16_t cntEvent)
1462 {
1463 struct ifnet *ifp;
1464 u_int16_t errorCount;
1465
1466 ifp = &sc->sc_ethercom.ec_if;
1467
1468 switch (cntEvent & REG_NUM_MASK) {
1469 case REG_NUM_TX_COL:
1470 /*
1471 * the count should be read before an overflow occurs.
1472 */
1473 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_TX_COL);
1474 /*
1475 * the tramsit event routine always checks the number of
1476 * collisions for any packet so we don't increment any
1477 * counters here, as they should already have been
1478 * considered.
1479 */
1480 break;
1481 case REG_NUM_RX_MISS:
1482 /*
1483 * the count should be read before an overflow occurs.
1484 */
1485 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_RX_MISS);
1486 /*
1487 * Increment the input error count, the first 6bits are the
1488 * register id.
1489 */
1490 ifp->if_ierrors += ((errorCount & 0xffC0) >> 6);
1491 break;
1492 default:
1493 /* do nothing */
1494 break;
1495 }
1496 }
1497
1498 void
1499 cs_buffer_event(struct cs_softc *sc, u_int16_t bufEvent)
1500 {
1501
1502 /*
1503 * multiple events can be in the buffer event register at one time so
1504 * a standard switch statement will not suffice, here every event
1505 * must be checked.
1506 */
1507
1508 /*
1509 * if 128 bits have been rxed by the time we get here, the dest event
1510 * will be cleared and 128 event will be set.
1511 */
1512 if ((bufEvent & (BUF_EVENT_RX_DEST | BUF_EVENT_RX_128)) != 0) {
1513 cs_process_rx_early(sc);
1514 }
1515
1516 if (bufEvent & BUF_EVENT_RX_DMA) {
1517 /* process the receive data */
1518 if (sc->sc_dma_process_rx)
1519 (*sc->sc_dma_process_rx)(sc);
1520 else
1521 /* should panic? */
1522 aprint_error_dev(sc->sc_dev, "unexpected DMA event\n");
1523 }
1524
1525 if (bufEvent & BUF_EVENT_TX_UNDR) {
1526 #if 0
1527 /*
1528 * This can happen occasionally, and it's not worth worrying
1529 * about.
1530 */
1531 printf("%s: transmit underrun (%d -> %d)\n",
1532 device_xname(sc->sc_dev), sc->sc_xe_ent,
1533 cs_xmit_early_table[sc->sc_xe_ent].worse);
1534 #endif
1535 sc->sc_xe_ent = cs_xmit_early_table[sc->sc_xe_ent].worse;
1536 sc->sc_xe_togo =
1537 cs_xmit_early_table[sc->sc_xe_ent].better_count;
1538
1539 /* had an underrun, transmit is finished */
1540 sc->sc_txbusy = FALSE;
1541 }
1542
1543 if (bufEvent & BUF_EVENT_SW_INT) {
1544 printf("%s: software initiated interrupt\n",
1545 device_xname(sc->sc_dev));
1546 }
1547 }
1548
1549 void
1550 cs_transmit_event(struct cs_softc *sc, u_int16_t txEvent)
1551 {
1552 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1553
1554 /* If there were any errors transmitting this frame */
1555 if (txEvent & (TX_EVENT_LOSS_CRS | TX_EVENT_SQE_ERR | TX_EVENT_OUT_WIN |
1556 TX_EVENT_JABBER | TX_EVENT_16_COLL)) {
1557 /* Increment the output error count */
1558 ifp->if_oerrors++;
1559
1560 /* Note carrier loss. */
1561 if (txEvent & TX_EVENT_LOSS_CRS)
1562 sc->sc_carrier = 0;
1563
1564 /* If debugging is enabled then log error messages */
1565 if (ifp->if_flags & IFF_DEBUG) {
1566 if (txEvent & TX_EVENT_LOSS_CRS) {
1567 aprint_error_dev(sc->sc_dev, "lost carrier\n");
1568 }
1569 if (txEvent & TX_EVENT_SQE_ERR) {
1570 aprint_error_dev(sc->sc_dev, "SQE error\n");
1571 }
1572 if (txEvent & TX_EVENT_OUT_WIN) {
1573 aprint_error_dev(sc->sc_dev,
1574 "out-of-window collision\n");
1575 }
1576 if (txEvent & TX_EVENT_JABBER) {
1577 aprint_error_dev(sc->sc_dev, "jabber\n");
1578 }
1579 if (txEvent & TX_EVENT_16_COLL) {
1580 aprint_error_dev(sc->sc_dev, "16 collisions\n");
1581 }
1582 }
1583 }
1584 else {
1585 /* Transmission successful, carrier is up. */
1586 sc->sc_carrier = 1;
1587 #ifdef SHARK
1588 ledNetActive();
1589 #endif
1590 }
1591
1592 /* Add the number of collisions for this frame */
1593 if (txEvent & TX_EVENT_16_COLL) {
1594 ifp->if_collisions += 16;
1595 } else {
1596 ifp->if_collisions += ((txEvent & TX_EVENT_COLL_MASK) >> 11);
1597 }
1598
1599 ifp->if_opackets++;
1600
1601 /* Transmission is no longer in progress */
1602 sc->sc_txbusy = FALSE;
1603
1604 /* If there is more to transmit */
1605 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) {
1606 /* Start the next transmission */
1607 cs_start_output(ifp);
1608 }
1609 }
1610
1611 void
1612 cs_print_rx_errors(struct cs_softc *sc, u_int16_t rxEvent)
1613 {
1614
1615 if (rxEvent & RX_EVENT_RUNT)
1616 aprint_error_dev(sc->sc_dev, "runt\n");
1617
1618 if (rxEvent & RX_EVENT_X_DATA)
1619 aprint_error_dev(sc->sc_dev, "extra data\n");
1620
1621 if (rxEvent & RX_EVENT_CRC_ERR) {
1622 if (rxEvent & RX_EVENT_DRIBBLE)
1623 aprint_error_dev(sc->sc_dev, "alignment error\n");
1624 else
1625 aprint_error_dev(sc->sc_dev, "CRC error\n");
1626 } else {
1627 if (rxEvent & RX_EVENT_DRIBBLE)
1628 aprint_error_dev(sc->sc_dev, "dribble bits\n");
1629 }
1630 }
1631
1632 void
1633 cs_receive_event(struct cs_softc *sc, u_int16_t rxEvent)
1634 {
1635 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1636
1637 /* If the frame was not received OK */
1638 if (!(rxEvent & RX_EVENT_RX_OK)) {
1639 /* Increment the input error count */
1640 ifp->if_ierrors++;
1641
1642 /*
1643 * If debugging is enabled then log error messages.
1644 */
1645 if (ifp->if_flags & IFF_DEBUG) {
1646 if (rxEvent != REG_NUM_RX_EVENT) {
1647 cs_print_rx_errors(sc, rxEvent);
1648
1649 /*
1650 * Must read the length of all received
1651 * frames
1652 */
1653 CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH);
1654
1655 /* Skip the received frame */
1656 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1657 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) |
1658 RX_CFG_SKIP);
1659 } else {
1660 aprint_error_dev(sc->sc_dev, "implied skip\n");
1661 }
1662 }
1663 } else {
1664 /*
1665 * process the received frame and pass it up to the upper
1666 * layers.
1667 */
1668 cs_process_receive(sc);
1669 }
1670 }
1671
1672 void
1673 cs_ether_input(struct cs_softc *sc, struct mbuf *m)
1674 {
1675 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1676
1677 ifp->if_ipackets++;
1678
1679 #if NBPFILTER > 0
1680 /*
1681 * Check if there's a BPF listener on this interface.
1682 * If so, hand off the raw packet to BPF.
1683 */
1684 if (ifp->if_bpf)
1685 bpf_mtap(ifp->if_bpf, m);
1686 #endif
1687
1688 /* Pass the packet up. */
1689 (*ifp->if_input)(ifp, m);
1690 }
1691
1692 void
1693 cs_process_receive(struct cs_softc *sc)
1694 {
1695 struct ifnet *ifp;
1696 struct mbuf *m;
1697 int totlen;
1698 u_int16_t *pBuff, *pBuffLimit;
1699 int pad;
1700 unsigned int frameOffset = 0; /* XXX: gcc */
1701
1702 #ifdef SHARK
1703 ledNetActive();
1704 #endif
1705
1706 ifp = &sc->sc_ethercom.ec_if;
1707
1708 /* Received a packet; carrier is up. */
1709 sc->sc_carrier = 1;
1710
1711 if (sc->sc_memorymode) {
1712 /* Initialize the frame offset */
1713 frameOffset = PKTPG_RX_LENGTH;
1714
1715 /* Get the length of the received frame */
1716 totlen = CS_READ_PACKET_PAGE(sc, frameOffset);
1717 frameOffset += 2;
1718 }
1719 else {
1720 /* drop status */
1721 CS_READ_PORT(sc, PORT_RXTX_DATA);
1722
1723 /* Get the length of the received frame */
1724 totlen = CS_READ_PORT(sc, PORT_RXTX_DATA);
1725 }
1726
1727 if (totlen > ETHER_MAX_LEN) {
1728 aprint_error_dev(sc->sc_dev, "invalid packet length %d\n",
1729 totlen);
1730
1731 /* skip the received frame */
1732 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1733 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
1734 return;
1735 }
1736
1737 MGETHDR(m, M_DONTWAIT, MT_DATA);
1738 if (m == 0) {
1739 aprint_error_dev(sc->sc_dev,
1740 "cs_process_receive: unable to allocate mbuf\n");
1741 ifp->if_ierrors++;
1742 /*
1743 * couldn't allocate an mbuf so things are not good, may as
1744 * well drop the packet I think.
1745 *
1746 * have already read the length so we should be right to skip
1747 * the packet.
1748 */
1749 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1750 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
1751 return;
1752 }
1753 m->m_pkthdr.rcvif = ifp;
1754 m->m_pkthdr.len = totlen;
1755
1756 /* number of bytes to align ip header on word boundary for ipintr */
1757 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
1758
1759 /*
1760 * alloc mbuf cluster if we need.
1761 * we need 1 byte spare because following
1762 * packet read loop can overrun.
1763 */
1764 if (totlen + pad + 1 > MHLEN) {
1765 MCLGET(m, M_DONTWAIT);
1766 if ((m->m_flags & M_EXT) == 0) {
1767 /* couldn't allocate an mbuf cluster */
1768 aprint_error_dev(sc->sc_dev,
1769 "cs_process_receive: "
1770 "unable to allocate a cluster\n");
1771 m_freem(m);
1772
1773 /* skip the received frame */
1774 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1775 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
1776 return;
1777 }
1778 }
1779
1780 /* align ip header on word boundary for ipintr */
1781 m->m_data += pad;
1782
1783 m->m_len = totlen;
1784 pBuff = mtod(m, u_int16_t *);
1785
1786 /* now read the data from the chip */
1787 if (sc->sc_memorymode) {
1788 pBuffLimit = pBuff + (totlen + 1) / 2; /* don't want to go over */
1789 while (pBuff < pBuffLimit) {
1790 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset);
1791 frameOffset += 2;
1792 }
1793 }
1794 else {
1795 IO_READ_MULTI_2(sc, PORT_RXTX_DATA, pBuff, (totlen + 1)>>1);
1796 }
1797
1798 cs_ether_input(sc, m);
1799 }
1800
1801 void
1802 cs_process_rx_early(struct cs_softc *sc)
1803 {
1804 struct ifnet *ifp;
1805 struct mbuf *m;
1806 u_int16_t frameCount, oldFrameCount;
1807 u_int16_t rxEvent;
1808 u_int16_t *pBuff;
1809 int pad;
1810 unsigned int frameOffset;
1811
1812
1813 ifp = &sc->sc_ethercom.ec_if;
1814
1815 /* Initialize the frame offset */
1816 frameOffset = PKTPG_RX_FRAME;
1817 frameCount = 0;
1818
1819 MGETHDR(m, M_DONTWAIT, MT_DATA);
1820 if (m == 0) {
1821 aprint_error_dev(sc->sc_dev,
1822 "cs_process_rx_early: unable to allocate mbuf\n");
1823 ifp->if_ierrors++;
1824 /*
1825 * couldn't allocate an mbuf so things are not good, may as
1826 * well drop the packet I think.
1827 *
1828 * have already read the length so we should be right to skip
1829 * the packet.
1830 */
1831 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1832 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
1833 return;
1834 }
1835 m->m_pkthdr.rcvif = ifp;
1836 /*
1837 * save processing by always using a mbuf cluster, guaranteed to fit
1838 * packet
1839 */
1840 MCLGET(m, M_DONTWAIT);
1841 if ((m->m_flags & M_EXT) == 0) {
1842 /* couldn't allocate an mbuf cluster */
1843 aprint_error_dev(sc->sc_dev,
1844 "cs_process_rx_early: unable to allocate a cluster\n");
1845 m_freem(m);
1846 /* skip the frame */
1847 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1848 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
1849 return;
1850 }
1851
1852 /* align ip header on word boundary for ipintr */
1853 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
1854 m->m_data += pad;
1855
1856 /* set up the buffer pointer to point to the data area */
1857 pBuff = mtod(m, u_int16_t *);
1858
1859 /*
1860 * now read the frame byte counter until we have finished reading the
1861 * frame
1862 */
1863 oldFrameCount = 0;
1864 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT);
1865 while ((frameCount != 0) && (frameCount < MCLBYTES)) {
1866 for (; oldFrameCount < frameCount; oldFrameCount += 2) {
1867 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset);
1868 frameOffset += 2;
1869 }
1870
1871 /* read the new count from the chip */
1872 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT);
1873 }
1874
1875 /* update the mbuf counts */
1876 m->m_len = oldFrameCount;
1877 m->m_pkthdr.len = oldFrameCount;
1878
1879 /* now check the Rx Event register */
1880 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT);
1881
1882 if ((rxEvent & RX_EVENT_RX_OK) != 0) {
1883 /*
1884 * do an implied skip, it seems to be more reliable than a
1885 * forced skip.
1886 */
1887 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_STATUS);
1888 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH);
1889
1890 /*
1891 * now read the RX_EVENT register to perform an implied skip.
1892 */
1893 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT);
1894
1895 cs_ether_input(sc, m);
1896 } else {
1897 m_freem(m);
1898 ifp->if_ierrors++;
1899 }
1900 }
1901
1902 void
1903 cs_start_output(struct ifnet *ifp)
1904 {
1905 struct cs_softc *sc;
1906 struct mbuf *pMbuf;
1907 struct mbuf *pMbufChain;
1908 u_int16_t BusStatus;
1909 u_int16_t Length;
1910 int txLoop = 0;
1911 int dropout = 0;
1912
1913 sc = ifp->if_softc;
1914
1915 /* check that the interface is up and running */
1916 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) {
1917 return;
1918 }
1919
1920 /* Don't interrupt a transmission in progress */
1921 if (sc->sc_txbusy) {
1922 return;
1923 }
1924
1925 /* this loop will only run through once if transmission is successful */
1926 /*
1927 * While there are packets to transmit and a transmit is not in
1928 * progress
1929 */
1930 while (sc->sc_txbusy == 0 && dropout == 0) {
1931 IFQ_DEQUEUE(&ifp->if_snd, pMbufChain);
1932 if (pMbufChain == NULL)
1933 break;
1934
1935 #if NBPFILTER > 0
1936 /*
1937 * If BPF is listening on this interface, let it see the packet
1938 * before we commit it to the wire.
1939 */
1940 if (ifp->if_bpf)
1941 bpf_mtap(ifp->if_bpf, pMbufChain);
1942 #endif
1943
1944 /* Find the total length of the data to transmit */
1945 Length = 0;
1946 for (pMbuf = pMbufChain; pMbuf != NULL; pMbuf = pMbuf->m_next)
1947 Length += pMbuf->m_len;
1948
1949 do {
1950 /*
1951 * Request that the transmit be started after all
1952 * data has been copied
1953 *
1954 * In IO mode must write to the IO port not the packet
1955 * page address
1956 *
1957 * If this is changed to start transmission after a
1958 * small amount of data has been copied you tend to
1959 * get packet missed errors i think because the ISA
1960 * bus is too slow. Or possibly the copy routine is
1961 * not streamlined enough.
1962 */
1963 if (sc->sc_memorymode) {
1964 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CMD,
1965 cs_xmit_early_table[sc->sc_xe_ent].txcmd);
1966 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_LENGTH, Length);
1967 }
1968 else {
1969 CS_WRITE_PORT(sc, PORT_TX_CMD,
1970 cs_xmit_early_table[sc->sc_xe_ent].txcmd);
1971 CS_WRITE_PORT(sc, PORT_TX_LENGTH, Length);
1972 }
1973
1974 /*
1975 * Adjust early-transmit machinery.
1976 */
1977 if (--sc->sc_xe_togo == 0) {
1978 sc->sc_xe_ent =
1979 cs_xmit_early_table[sc->sc_xe_ent].better;
1980 sc->sc_xe_togo =
1981 cs_xmit_early_table[sc->sc_xe_ent].better_count;
1982 }
1983 /*
1984 * Read the BusStatus register which indicates
1985 * success of the request
1986 */
1987 BusStatus = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_ST);
1988
1989 /*
1990 * If there was an error in the transmit bid free the
1991 * mbuf and go on. This is presuming that mbuf is
1992 * corrupt.
1993 */
1994 if (BusStatus & BUS_ST_TX_BID_ERR) {
1995 aprint_error_dev(sc->sc_dev,
1996 "transmit bid error (too big)");
1997
1998 /* Discard the bad mbuf chain */
1999 m_freem(pMbufChain);
2000 sc->sc_ethercom.ec_if.if_oerrors++;
2001
2002 /* Loop up to transmit the next chain */
2003 txLoop = 0;
2004 } else {
2005 if (BusStatus & BUS_ST_RDY4TXNOW) {
2006 /*
2007 * The chip is ready for transmission
2008 * now
2009 */
2010 /*
2011 * Copy the frame to the chip to
2012 * start transmission
2013 */
2014 cs_copy_tx_frame(sc, pMbufChain);
2015
2016 /* Free the mbuf chain */
2017 m_freem(pMbufChain);
2018
2019 /* Transmission is now in progress */
2020 sc->sc_txbusy = TRUE;
2021 txLoop = 0;
2022 } else {
2023 /*
2024 * if we get here we want to try
2025 * again with the same mbuf, until
2026 * the chip lets us transmit.
2027 */
2028 txLoop++;
2029 if (txLoop > CS_OUTPUT_LOOP_MAX) {
2030 /* Free the mbuf chain */
2031 m_freem(pMbufChain);
2032 /*
2033 * Transmission is not in
2034 * progress
2035 */
2036 sc->sc_txbusy = FALSE;
2037 /*
2038 * Increment the output error
2039 * count
2040 */
2041 ifp->if_oerrors++;
2042 /*
2043 * exit the routine and drop
2044 * the packet.
2045 */
2046 txLoop = 0;
2047 dropout = 1;
2048 }
2049 }
2050 }
2051 } while (txLoop);
2052 }
2053 }
2054
2055 void
2056 cs_copy_tx_frame(struct cs_softc *sc, struct mbuf *m0)
2057 {
2058 struct mbuf *m;
2059 int len, leftover, frameoff;
2060 u_int16_t dbuf;
2061 u_int8_t *p;
2062 #ifdef DIAGNOSTIC
2063 u_int8_t *lim;
2064 #endif
2065
2066 /* Initialize frame pointer and data port address */
2067 frameoff = PKTPG_TX_FRAME;
2068
2069 /* start out with no leftover data */
2070 leftover = 0;
2071 dbuf = 0;
2072
2073 /* Process the chain of mbufs */
2074 for (m = m0; m != NULL; m = m->m_next) {
2075 /*
2076 * Process all of the data in a single mbuf.
2077 */
2078 p = mtod(m, u_int8_t *);
2079 len = m->m_len;
2080 #ifdef DIAGNOSTIC
2081 lim = p + len;
2082 #endif
2083
2084 while (len > 0) {
2085 if (leftover) {
2086 /*
2087 * Data left over (from mbuf or realignment).
2088 * Buffer the next byte, and write it and
2089 * the leftover data out.
2090 */
2091 dbuf |= *p++ << 8;
2092 len--;
2093 if (sc->sc_memorymode) {
2094 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf);
2095 frameoff += 2;
2096 }
2097 else {
2098 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf);
2099 }
2100 leftover = 0;
2101 } else if ((long) p & 1) {
2102 /*
2103 * Misaligned data. Buffer the next byte.
2104 */
2105 dbuf = *p++;
2106 len--;
2107 leftover = 1;
2108 } else {
2109 /*
2110 * Aligned data. This is the case we like.
2111 *
2112 * Write-region out as much as we can, then
2113 * buffer the remaining byte (if any).
2114 */
2115 leftover = len & 1;
2116 len &= ~1;
2117 if (sc->sc_memorymode) {
2118 MEM_WRITE_REGION_2(sc, frameoff,
2119 (u_int16_t *) p, len >> 1);
2120 frameoff += len;
2121 }
2122 else {
2123 IO_WRITE_MULTI_2(sc,
2124 PORT_RXTX_DATA, (u_int16_t *)p, len >> 1);
2125 }
2126 p += len;
2127
2128 if (leftover)
2129 dbuf = *p++;
2130 len = 0;
2131 }
2132 }
2133 if (len < 0)
2134 panic("cs_copy_tx_frame: negative len");
2135 #ifdef DIAGNOSTIC
2136 if (p != lim)
2137 panic("cs_copy_tx_frame: p != lim");
2138 #endif
2139 }
2140 if (leftover) {
2141 if (sc->sc_memorymode) {
2142 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf);
2143 }
2144 else {
2145 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf);
2146 }
2147 }
2148 }
2149
2150 static int
2151 cs_enable(struct cs_softc *sc)
2152 {
2153
2154 if (CS_IS_ENABLED(sc) == 0) {
2155 if (sc->sc_enable != NULL) {
2156 int error;
2157
2158 error = (*sc->sc_enable)(sc);
2159 if (error)
2160 return (error);
2161 }
2162 sc->sc_cfgflags |= CFGFLG_ENABLED;
2163 }
2164
2165 return (0);
2166 }
2167
2168 static void
2169 cs_disable(struct cs_softc *sc)
2170 {
2171
2172 if (CS_IS_ENABLED(sc)) {
2173 if (sc->sc_disable != NULL)
2174 (*sc->sc_disable)(sc);
2175
2176 sc->sc_cfgflags &= ~CFGFLG_ENABLED;
2177 }
2178 }
2179
2180 static void
2181 cs_stop(struct ifnet *ifp, int disable)
2182 {
2183 struct cs_softc *sc = ifp->if_softc;
2184
2185 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 0);
2186 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, 0);
2187 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 0);
2188 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 0);
2189
2190 if (disable) {
2191 cs_disable(sc);
2192 }
2193
2194 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2195 }
2196
2197 int
2198 cs_activate(device_t self, enum devact act)
2199 {
2200 struct cs_softc *sc = device_private(self);
2201
2202 switch (act) {
2203 case DVACT_DEACTIVATE:
2204 if_deactivate(&sc->sc_ethercom.ec_if);
2205 return 0;
2206 default:
2207 return EOPNOTSUPP;
2208 }
2209 }
NetBSD on the FriendlyARM MINI2440