sys/dev/ic/dp83905reg.h

   1 /*      $NetBSD$        */
   2
   3 /*
   4  * Ben Harris, 2001
   5  *
   6  * This file is in the public domain.
   7  */
   8
   9 /* dp83905reg.h - NatSemi DP83905 registers */
  10
  11 /*
  12  * This file describes the special registers in the National
  13  * Semiconductor DP83905 AT/LANTIC AT Local Area Network Twisted-Pair
  14  * Interface Controller.  The Macronix MX98905 is a clone of this chip.
  15  *
  16  * The DP83905 is a DP8390 with added glue logic to enable it to
  17  * emulate both an NE2000 and a WD 8319.  It and its clones are
  18  * commonly used on podulebus Ethernet cards.
  19  */
  20
  21 /* Extra registers (in page 0) */
  22 #define DP83905_MCRA    0x0a
  23 #define DP83905_MCRB    0x0b
  24
  25 #define DP83905_MCRA_IOADDR_MASK        0x07 /* I/O Address */
  26 #define DP83905_MCRA_IOADDR_300         0x00
  27 #define DP83905_MCRA_IOADDR_SOFT        0x01
  28 #define DP83905_MCRA_IOADDR_240         0x02
  29 #define DP83905_MCRA_IOADDR_280         0x03
  30 #define DP83905_MCRA_IOADDR_2C0         0x04
  31 #define DP83905_MCRA_IOADDR_320         0x05
  32 #define DP83905_MCRA_IOADDR_340         0x06
  33 #define DP83905_MCRA_IOADDR_360         0x07
  34 #define DP83905_MCRA_INT_MASK           0x38 /* Interrupt line used */
  35 #define DP83905_MCRA_INT0               0x00
  36 #define DP83905_MCRA_INT1               0x08
  37 #define DP83905_MCRA_INT2               0x10
  38 #define DP83905_MCRA_INT3               0x18
  39 #define DP83905_MCRA_FREAD              0x40 /* Fast read */
  40 #define DP83905_MCRA_MEMIO              0x80 /* Memory or I/O mode (1=>mem) */
  41
  42 #define DP83905_MCRB_PHY_MASK           0x03 /* Physical layer interface */
  43 #define DP83905_MCRB_PHY_10_T           0x00 /* TPI (10BASE-T squelch) */
  44 #define DP83905_MCRB_PHY_10_2           0x01 /* Thin Ethernet (10BASE2) */
  45 #define DP83905_MCRB_PHY_AUI            0x02 /* Thick Ethernet (10BASE5/AUI) */
  46 #define DP83905_MCRB_PHY_TPI_NONSPEC    0x03 /* TPI (Reduced squelch) */
  47 #define DP83905_MCRB_GDLNK              0x04 /* Good link */
  48 #define DP83905_MCRB_IO16CON            0x08 /* IO16* control */
  49 #define DP83905_MCRB_CHRDY              0x10 /* CHRDY from IORD/WR* or BALE */
  50 #define DP83905_MCRB_BE                 0x20 /* Bus error */
  51 #define DP83905_MCRB_BPWR               0x40 /* Boot PROM write */
  52 #define DP83905_MCRB_EELOAD             0x80 /* EEPROM load */