sys/dev/ic/siisatareg.h

   1 /* $NetBSD: siisatareg.h,v 1.4 2009/07/04 20:57:15 jakllsch Exp $ */
   2
   3 /*-
   4  * Copyright (c) 2007, 2008, 2009 Jonathan A. Kollasch.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  */
  28
  29 /* Silicon Image SATA 2 controller register defines */
  30
  31 #include <sys/cdefs.h>
  32
  33 /* the SiI3124 has 4 ports, all others so far have less */
  34 #define SIISATA_MAX_PORTS 4
  35 /* all parts have a full complement of slots (so far) */
  36 #define SIISATA_MAX_SLOTS 31
  37
  38 /* structures */
  39
  40 /* Scatter/Gather Entry */
  41 struct siisata_sge {
  42 #if 0
  43         uint32_t sge_dal; /* data address low */
  44         uint32_t sge_dah; /* "          " high */
  45 #else
  46         uint64_t sge_da;
  47 #endif
  48         uint32_t sge_dc;  /* data count (bytes) */
  49         uint32_t sge_flags; /* */
  50 #define SGE_FLAG_TRM __BIT(31)
  51 #define SGE_FLAG_LNK __BIT(30)
  52 #define SGE_FLAG_DRD __BIT(29)
  53 #define SGE_FLAG_XCF __BIT(28)
  54 } __packed;
  55
  56 /* Scatter/Gather Table */
  57 /* must be aligned to 64-bit boundary */
  58 struct siisata_sgt {
  59         struct siisata_sge sgt_sge[4];
  60 } __packed;
  61
  62 /* Port Request Block */
  63 struct siisata_prb {
  64         uint16_t prb_control; /* Control Field */
  65 #define PRB_CF_PROTOCOL_OVERRIDE __BIT(0)
  66 #define PRB_CF_RETRANSMIT        __BIT(1)
  67 #define PRB_CF_EXTERNAL_COMMAND  __BIT(2)
  68 #define PRB_CF_RECEIVE           __BIT(3)
  69 #define PRB_CF_PACKET_READ       __BIT(4)
  70 #define PRB_CF_PACKET_WRITE      __BIT(5)
  71 #define PRB_CF_INTERRUPT_MASK    __BIT(6)
  72 #define PRB_CF_SOFT_RESET        __BIT(7)
  73         uint16_t prb_protocol_override;
  74 #define PRB_PO_PACKET      __BIT(0)
  75 #define PRB_PO_LCQ         __BIT(1)
  76 #define PRB_PO_NCQ         __BIT(2)
  77 #define PRB_PO_READ        __BIT(3)
  78 #define PRB_PO_WRITE       __BIT(4)
  79 #define PRB_PO_TRANSPARENT __BIT(5)
  80         uint32_t prb_transfer_count;
  81         uint8_t prb_fis[20];
  82         uint32_t prb_reserved_0x1C; /* "must be zero" */
  83 /* First SGE in PRB is always reserved for ATAPI in this implementation. */
  84         uint8_t prb_atapi[16]; /* zero for non-ATAPI */
  85         struct siisata_sge prb_sge[1]; /* extended to NSGE */
  86 } __packed;
  87
  88
  89 #define SIISATA_NSGE ((MAXPHYS/PAGE_SIZE) + 1)
  90 #define SIISATA_CMD_ALIGN 0x7f
  91 #define SIISATA_CMD_SIZE \
  92 ( ( sizeof(struct siisata_prb) + (SIISATA_NSGE - 1) * sizeof(struct siisata_sge) + SIISATA_CMD_ALIGN ) & ~SIISATA_CMD_ALIGN )
  93
  94 /* PCI stuff */
  95 #define SIISATA_PCI_BAR0 0x10
  96 #define SIISATA_PCI_BAR1 0x18
  97 #define SIISATA_PCI_BAR2 0x20
  98
  99 /* Cardbus stuff */
 100 #define SIISATA_CARDBUS_BAR0 SIISATA_PCI_BAR0
 101 #define SIISATA_CARDBUS_BAR1 SIISATA_PCI_BAR1
 102 #define SIISATA_CARDBUS_BAR2 SIISATA_PCI_BAR2
 103
 104 /* BAR 0 */
 105
 106 /* port n slot status */
 107 #define GR_PXSS(n) (n*4)
 108 /* global control */
 109 #define GR_GC           0x40
 110 /* global interrupt status */
 111 #define GR_GIS          0x44
 112 /* phy config - don't touch */
 113 #define GR_PHYC         0x48
 114 /* BIST */
 115 #define GR_BIST_CONTROL 0x50
 116 #define GR_BIST_PATTERN 0x54
 117 #define GR_BIST_STATUS  0x58
 118 /* I2C SiI3132 */
 119 #define GR_SII3132_IICCONTROL   0x60
 120 #define GR_SII3132_IICSTATUS    0x64
 121 #define GR_SII3132_IICSLAVEADDR 0x68
 122 #define GR_SII3132_IICDATA      0x6c
 123 /* Flash */
 124 #define GR_FLSHADDR     0x70
 125 #define GR_FLSHDATA     0x74
 126 /* I2C SiI3124 */
 127 #define GR_SII3124_IICADDR      0x78
 128 #define GR_SII3124_IICDATA      0x7c
 129
 130
 131 /* GR_GC bits */
 132 #define GR_GC_GLBLRST           __BIT(31)
 133 #define GR_GC_MSIACK            __BIT(30)
 134 #define GR_GC_I2CINTEN          __BIT(29)
 135 #define GR_GC_PERRRPTDSBL       __BIT(28)
 136 #define GR_GC_3GBPS             __BIT(24)
 137 #define GR_GC_REQ64             __BIT(20)
 138 #define GR_GC_DEVSEL            __BIT(19)
 139 #define GR_GC_STOP              __BIT(18)
 140 #define GR_GC_TRDY              __BIT(17)
 141 #define GR_GC_M66EN             __BIT(16)
 142 #define GR_GC_PXIE_MASK         __BITS(SIISATA_MAX_PORTS - 1, 0)
 143 #define GR_GC_PXIE(n)           __SHIFTIN(__BIT(n), GR_GC_PXIE_MASK)
 144
 145 /* GR_GIS bits */
 146 #define GR_GIS_I2C              __BIT(29)
 147 #define GR_GIS_PXIS_MASK        __BITS(SIISATA_MAX_PORTS - 1, 0)
 148 #define GR_GIS_PXIS(n)          __SHIFTIN(__BIT(n), GR_GIS_PXIS_MASK)
 149
 150
 151 /* BAR 1 */
 152
 153 /* hmm, this could use a better name */
 154 #define PR_PORT_SIZE    0x2000
 155 #define PR_SLOT_SIZE    0x80
 156 /* get the register by port number and offset */
 157 #define PRO(p) (PR_PORT_SIZE * p)
 158 #define PRX(p,r) (PRO(p) + r)
 159 #define PRSX(p,s,o) (PRX(p, PR_SLOT_SIZE * s + o))
 160
 161 #define PRSO_RTC        0x04            /* recieved transfer count */
 162 #define PRSO_FIS        0x08            /* base of FIS */
 163
 164 #define PRO_PCS         0x1000          /* (write) port control set */
 165 #define PRO_PS          PRO_PCS         /* (read) port status */
 166 #define PRO_PCC         0x1004          /* port control clear */
 167 #define PRO_PIS         0x1008          /* port interrupt status */
 168 #define PRO_PIES        0x1010          /* port interrupt enable set */
 169 #define PRO_PIEC        0x1014          /* port interrupt enable clear */
 170 #define PRO_32BAUA      0x101c          /* 32-bit activation upper address */
 171 #define PRO_PCEF        0x1020          /* port command execution fifo */
 172 #define PRO_PCE         0x1024          /* port command error */
 173 #define PRO_PFISC       0x1028          /* port FIS config */
 174 #define PRO_PCIRFIFOT   0x102c          /* pci request fifo threshhold */
 175 #define PRO_P8B10BDEC   0x1040          /* port 8B/10B decode error counter */
 176 #define PRO_PCRCEC      0x1044          /* port crc error count */
 177 #define PRO_PHEC        0x1048          /* port handshake error count */
 178 #define PRO_PPHYC       0x1050          /* phy config */
 179 #define PRO_PSS         0x1800          /* port slot status */
 180 /* technically this is a shadow of the CAR */
 181 #define PRO_CAR         0x1c00
 182
 183 #define PRO_CARX(p,s)     (PRX(p, PRO_CAR) + s * sizeof(uint64_t))
 184
 185 #define PRO_PCR         0x1e04          /* port context register */
 186 #define PRO_SCONTROL    0x1f00          /* SControl */
 187 #define PRO_SSTATUS     0x1f04          /* SStatus */
 188 #define PRO_SERROR      0x1f08          /* SError */
 189 #define PRO_SACTIVE     0x1f0c          /* SActive */
 190
 191
 192 /* Port Command Error */
 193 #define PR_PCE_DEVICEERROR              1
 194 #define PR_PCE_SDBERROR                 2
 195 #define PR_PCE_DATAFISERROR             3
 196 #define PR_PCE_SENDFISERROR             4
 197 #define PR_PCE_INCONSISTENTSTATE        5
 198 #define PR_PCE_DIRECTIONERROR           6
 199 #define PR_PCE_UNDERRUNERROR            7
 200 #define PR_PCE_OVERRUNERROR             8
 201 #define PR_PCE_LINKFIFOOVERRUN          9
 202 #define PR_PCE_PACKETPROTOCOLERROR      11
 203 #define PR_PCE_PLDSGTERRORBOUNDARY      16
 204 #define PR_PCE_PLDSGTERRORTARGETABORT   17
 205 #define PR_PCE_PLDSGTERRORMASTERABORT   18
 206 #define PR_PCE_PLDSGTERRORPCIPERR       19
 207 #define PR_PCE_PLDCMDERRORBOUNDARY      24
 208 #define PR_PCE_PLDCMDERRORTARGETABORT   25
 209 #define PR_PCE_PLDCMDERRORMASTERABORT   26
 210 #define PR_PCE_PLDCMDERRORPCIPERR       27
 211 #define PR_PCE_PSDERRORTARGETABORT      33
 212 #define PR_PCE_PSDERRORMASTERABORT      34
 213 #define PR_PCE_PSDERRORPCIPERR          35
 214 #define PR_PCE_SENDSERVICEERROROR       36
 215
 216
 217 #define PR_PIS_UNMASKED_SHIFT   16
 218 #define PR_PIS_CMDCMPL          __BIT(0)        /* command completion */
 219 #define PR_PIS_CMDERRR          __BIT(1)        /* command error */
 220 #define PR_PIS_PRTRDY           __BIT(2)  /* port ready */
 221 #define PR_PIS_PMCHNG           __BIT(3)  /* power management state change */
 222 #define PR_PIS_PHYRDYCHG        __BIT(4)
 223 #define PR_PIS_COMWAKE          __BIT(5)
 224 #define PR_PIS_UNRECFIS         __BIT(6)
 225 #define PR_PIS_DEVEXCHG         __BIT(7)
 226 #define PR_PIS_8B10BDET         __BIT(8)
 227 #define PR_PIS_CRCET            __BIT(9)
 228 #define PR_PIS_HET              __BIT(10)
 229 #define PR_PIS_SDBN             __BIT(11)
 230
 231 #define PR_PC_PORT_RESET        __BIT(0)
 232 #define PR_PC_DEVICE_RESET      __BIT(1)
 233 #define PR_PC_PORT_INITIALIZE   __BIT(2)
 234 #define PR_PC_INCOR             __BIT(3)
 235 #define PR_PC_LED_DISABLE       __BIT(4)
 236 #define PR_PC_PACKET_LENGTH     __BIT(5)
 237 #define PR_PC_RESUME            __BIT(6)
 238 #define PR_PC_TXBIST            __BIT(7)
 239 #define PR_PC_CONT_DISABLE      __BIT(8)
 240 #define PR_PC_SCRAMBLER_DISABLE __BIT(9)
 241 #define PR_PC_32BA              __BIT(10)
 242 #define PR_PC_INTERLOCK_REJECT  __BIT(11)
 243 #define PR_PC_INTERLOCK_ACCEPT  __BIT(12)
 244 #define PR_PC_PMP_ENABLE        __BIT(13)
 245 #define PR_PC_AIA               __BIT(14)
 246 #define PR_PC_LED_ON            __BIT(15)
 247 #define PR_PC_OOB_BYPASS        __BIT(25)
 248 #define PR_PS_PORT_READY        __BIT(31)
 249
 250 #define PR_PSS_ATTENTION        __BIT(31)
 251 #define PR_PSS_SLOT_MASK        __BITS(30, 0)
 252 #define PR_PXSS(n)              __SHIFTIN(__BIT(n), PR_PSS_SLOT_MASK)