sys/dev/mii/dmphyreg.h

   1 /*      $NetBSD: dmphyreg.h,v 1.1 2000/02/02 04:29:49 thorpej Exp $     */
   2
   3 /*-
   4  * Copyright (c) 2000 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
   9  * NASA Ames Research Center.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30  * POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #ifndef _DEV_MII_DMPHYREG_H_
  34 #define _DEV_MII_DMPHYREG_H_
  35
  36 /*
  37  * Davicom DM9101 registers.
  38  */
  39
  40 #define MII_DMPHY_DSCR          0x10    /* DAVICOM Specified Config Reg */
  41 #define DSCR_BP_4B5B            0x8000  /* bypass 4b5b encoding/decoding */
  42 #define DSCR_SCR                0x4000  /* bypass scrambler/descrambler */
  43 #define DSCR_ALIGN              0x2000  /* bypass symbol alignment */
  44 #define DSCR_REPEATER           0x0800  /* repeater mode */
  45 #define DSCR_TX                 0x0400  /* 1 == 100baseTX, 0 == 100baseFX */
  46 #define DSCR_UTP                0x0200  /* 1 == UTP, 0 == STP */
  47 #define DSCR_CLK25MDIS          0x0100  /* CLK25M disable */
  48 #define DSCR_F_LINK_100         0x0080  /* force good link in 100Mb/s mode */
  49 #define DSCR_LINKLED_CTL        0x0020  /* 1 == link only, 0 == link+traffic */
  50 #define DSCR_FDXLEN_MODE        0x0010  /* 1 == 10baseT polarity, 0 == FDX */
  51 #define DSCR_SMRST              0x0008  /* reset state machine */
  52 #define DSCR_MFPSC              0x0004  /* MF preamble suppression */
  53 #define DSCR_SLEEP              0x0002  /* sleep mode */
  54 #define DSCR_RLOUT              0x0001  /* remote loop-out control */
  55
  56 #define MII_DMPHY_DSCSR         0x11    /* DAVICOM Spec'd Conf/Stat Reg */
  57 #define DSCSR_100FDX            0x8000  /* 100Mb/s FDX */
  58 #define DSCSR_100HDX            0x4000  /* 100Mb/s HDX */
  59 #define DSCSR_10FDX             0x2000  /* 10Mb/s FDX */
  60 #define DSCSR_10HDX             0x1000  /* 10Mb/s HDX */
  61 #define DSCSR_PHYAD             0x01f0  /* PHY address */
  62 #define DSCSR_ANMB              0x000f  /* Autonegotiation monitor */
  63
  64 #define ANMB_IDLE               0x0000  /* idle */
  65 #define ANMB_AB_MATCH           0x0001  /* ability match */
  66 #define ANMB_ACK_MATCH          0x0002  /* acknowledge match */
  67 #define ANMB_ACK_MATCH_FAIL     0x0003  /* acknowledge match fail */
  68 #define ANMB_CON_MATCH          0x0004  /* consistency match */
  69 #define ANMB_CON_MATCH_FAIL     0x0005  /* consistency match fail */
  70 #define ANMB_PAR_LINK           0x0006  /* par detect signal link ready */
  71 #define ANMB_PAR_LINK_FAIL      0x0007  /* par detect signal link ready fail */
  72 #define ANMB_ANEG_OK            0x0008  /* autonegotiation completed ok */
  73
  74 #define MII_DMPHY_BTCSR         0x12    /* 10baseT Configuration/Status */
  75 #define BTCSR_LP_EN             0x4000  /* link pulse enable */
  76 #define BTCSR_HBE               0x2000  /* heartbeat enable */
  77 #define BTCSR_JABEN             0x0800  /* jabber enable */
  78 #define BTCSR_10BT_SER          0x0400  /* 10baseT serial mode */
  79 #define BTCSR_POLR              0x0001  /* polarity reversed */
  80
  81 #endif /* _DEV_MII_DMPHYREG_H_ */