sys/dev/mii/mii.h

   1 /*      $NetBSD: mii.h,v 1.13 2005/12/11 12:22:42 christos Exp $        */
   2
   3 /*
   4  * Copyright (c) 1997 Manuel Bouyer.  All rights reserved.
   5  *
   6  * Modification to match BSD/OS 3.0 MII interface by Jason R. Thorpe,
   7  * Numerical Aerospace Simulation Facility, NASA Ames Research Center.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #ifndef _DEV_MII_MII_H_
  31 #define _DEV_MII_MII_H_
  32
  33 /*
  34  * Registers common to all PHYs.
  35  */
  36
  37 #define MII_NPHY        32      /* max # of PHYs per MII */
  38
  39 /*
  40  * MII commands, used if a device must drive the MII lines
  41  * manually.
  42  */
  43 #define MII_COMMAND_START       0x01
  44 #define MII_COMMAND_READ        0x02
  45 #define MII_COMMAND_WRITE       0x01
  46 #define MII_COMMAND_ACK         0x02
  47
  48 #define MII_BMCR        0x00    /* Basic mode control register (rw) */
  49 #define BMCR_RESET      0x8000  /* reset */
  50 #define BMCR_LOOP       0x4000  /* loopback */
  51 #define BMCR_SPEED0     0x2000  /* speed selection (LSB) */
  52 #define BMCR_AUTOEN     0x1000  /* autonegotiation enable */
  53 #define BMCR_PDOWN      0x0800  /* power down */
  54 #define BMCR_ISO        0x0400  /* isolate */
  55 #define BMCR_STARTNEG   0x0200  /* restart autonegotiation */
  56 #define BMCR_FDX        0x0100  /* Set duplex mode */
  57 #define BMCR_CTEST      0x0080  /* collision test */
  58 #define BMCR_SPEED1     0x0040  /* speed selection (MSB) */
  59
  60 #define BMCR_S10        0x0000          /* 10 Mb/s */
  61 #define BMCR_S100       BMCR_SPEED0     /* 100 Mb/s */
  62 #define BMCR_S1000      BMCR_SPEED1     /* 1000 Mb/s */
  63
  64 #define BMCR_SPEED(x)   ((x) & (BMCR_SPEED0|BMCR_SPEED1))
  65
  66 #define MII_BMSR        0x01    /* Basic mode status register (ro) */
  67 #define BMSR_100T4      0x8000  /* 100 base T4 capable */
  68 #define BMSR_100TXFDX   0x4000  /* 100 base Tx full duplex capable */
  69 #define BMSR_100TXHDX   0x2000  /* 100 base Tx half duplex capable */
  70 #define BMSR_10TFDX     0x1000  /* 10 base T full duplex capable */
  71 #define BMSR_10THDX     0x0800  /* 10 base T half duplex capable */
  72 #define BMSR_100T2FDX   0x0400  /* 100 base T2 full duplex capable */
  73 #define BMSR_100T2HDX   0x0200  /* 100 base T2 half duplex capable */
  74 #define BMSR_EXTSTAT    0x0100  /* Extended status in register 15 */
  75 #define BMSR_MFPS       0x0040  /* MII Frame Preamble Suppression */
  76 #define BMSR_ACOMP      0x0020  /* Autonegotiation complete */
  77 #define BMSR_RFAULT     0x0010  /* Link partner fault */
  78 #define BMSR_ANEG       0x0008  /* Autonegotiation capable */
  79 #define BMSR_LINK       0x0004  /* Link status */
  80 #define BMSR_JABBER     0x0002  /* Jabber detected */
  81 #define BMSR_EXTCAP     0x0001  /* Extended capability */
  82
  83 /*
  84  * Note that the EXTSTAT bit indicates that there is extended status
  85  * info available in register 15, but 802.3 section 22.2.4.3 also
  86  * states that that all 1000 Mb/s capable PHYs will set this bit to 1.
  87  */
  88
  89 #define BMSR_MEDIAMASK  (BMSR_100T4|BMSR_100TXFDX|BMSR_100TXHDX| \
  90                          BMSR_10TFDX|BMSR_10THDX|BMSR_100T2FDX|BMSR_100T2HDX)
  91
  92 /*
  93  * Convert BMSR media capabilities to ANAR bits for autonegotiation.
  94  * Note the shift chopps off the BMSR_ANEG bit.
  95  */
  96 #define BMSR_MEDIA_TO_ANAR(x)   (((x) & BMSR_MEDIAMASK) >> 6)
  97
  98 #define MII_PHYIDR1     0x02    /* ID register 1 (ro) */
  99
 100 #define MII_PHYIDR2     0x03    /* ID register 2 (ro) */
 101 #define IDR2_OUILSB     0xfc00  /* OUI LSB */
 102 #define IDR2_MODEL      0x03f0  /* vendor model */
 103 #define IDR2_REV        0x000f  /* vendor revision */
 104
 105 #define MII_ANAR        0x04    /* Autonegotiation advertisement (rw) */
 106                 /* section 28.2.4.1 and 37.2.6.1 */
 107 #define ANAR_NP         0x8000  /* Next page (ro) */
 108 #define ANAR_ACK        0x4000  /* link partner abilities acknowledged (ro) */
 109 #define ANAR_RF         0x2000  /* remote fault (ro) */
 110 #define ANAR_FC         0x0400  /* local device supports PAUSE */
 111 #define ANAR_T4         0x0200  /* local device supports 100bT4 */
 112 #define ANAR_TX_FD      0x0100  /* local device supports 100bTx FD */
 113 #define ANAR_TX         0x0080  /* local device supports 100bTx */
 114 #define ANAR_10_FD      0x0040  /* local device supports 10bT FD */
 115 #define ANAR_10         0x0020  /* local device supports 10bT */
 116 #define ANAR_CSMA       0x0001  /* protocol selector CSMA/CD */
 117
 118 #define ANAR_X_FD       0x0020  /* local device supports 1000BASE-X FD */
 119 #define ANAR_X_HD       0x0040  /* local device supports 1000BASE-X HD */
 120 #define ANAR_X_PAUSE_NONE       (0 << 10)
 121 #define ANAR_X_PAUSE_SYM        (1 << 10)
 122 #define ANAR_X_PAUSE_ASYM       (2 << 10)
 123 #define ANAR_X_PAUSE_TOWARDS    (3 << 10)
 124
 125 #define MII_ANLPAR      0x05    /* Autonegotiation lnk partner abilities (rw) */
 126                 /* section 28.2.4.1 and 37.2.6.1 */
 127 #define ANLPAR_NP       0x8000  /* Next page (ro) */
 128 #define ANLPAR_ACK      0x4000  /* link partner accepted ACK (ro) */
 129 #define ANLPAR_RF       0x2000  /* remote fault (ro) */
 130 #define ANLPAR_FC       0x0400  /* link partner supports PAUSE */
 131 #define ANLPAR_T4       0x0200  /* link partner supports 100bT4 */
 132 #define ANLPAR_TX_FD    0x0100  /* link partner supports 100bTx FD */
 133 #define ANLPAR_TX       0x0080  /* link partner supports 100bTx */
 134 #define ANLPAR_10_FD    0x0040  /* link partner supports 10bT FD */
 135 #define ANLPAR_10       0x0020  /* link partner supports 10bT */
 136 #define ANLPAR_CSMA     0x0001  /* protocol selector CSMA/CD */
 137
 138 #define ANLPAR_X_FD     0x0020  /* local device supports 1000BASE-X FD */
 139 #define ANLPAR_X_HD     0x0040  /* local device supports 1000BASE-X HD */
 140 #define ANLPAR_X_PAUSE_MASK     (3 << 10)
 141 #define ANLPAR_X_PAUSE_NONE     (0 << 10)
 142 #define ANLPAR_X_PAUSE_SYM      (1 << 10)
 143 #define ANLPAR_X_PAUSE_ASYM     (2 << 10)
 144 #define ANLPAR_X_PAUSE_TOWARDS  (3 << 10)
 145
 146 #define MII_ANER        0x06    /* Autonegotiation expansion (ro) */
 147                 /* section 28.2.4.1 and 37.2.6.1 */
 148 #define ANER_MLF        0x0010  /* multiple link detection fault */
 149 #define ANER_LPNP       0x0008  /* link parter next page-able */
 150 #define ANER_NP         0x0004  /* next page-able */
 151 #define ANER_PAGE_RX    0x0002  /* Page received */
 152 #define ANER_LPAN       0x0001  /* link parter autoneg-able */
 153
 154 #define MII_ANNP        0x07    /* Autonegotiation next page */
 155                 /* section 28.2.4.1 and 37.2.6.1 */
 156
 157 #define MII_ANLPRNP     0x08    /* Autonegotiation link partner rx next page */
 158                 /* section 32.5.1 and 37.2.6.1 */
 159
 160                         /* This is also the 1000baseT control register */
 161 #define MII_100T2CR     0x09    /* 100base-T2 control register */
 162 #define GTCR_TEST_MASK  0xe000  /* see 802.3ab ss. 40.6.1.1.2 */
 163 #define GTCR_MAN_MS     0x1000  /* enable manual master/slave control */
 164 #define GTCR_ADV_MS     0x0800  /* 1 = adv. master, 0 = adv. slave */
 165 #define GTCR_PORT_TYPE  0x0400  /* 1 = DCE, 0 = DTE (NIC) */
 166 #define GTCR_ADV_1000TFDX 0x0200 /* adv. 1000baseT FDX */
 167 #define GTCR_ADV_1000THDX 0x0100 /* adv. 1000baseT HDX */
 168
 169                         /* This is also the 1000baseT status register */
 170 #define MII_100T2SR     0x0a    /* 100base-T2 status register */
 171 #define GTSR_MAN_MS_FLT 0x8000  /* master/slave config fault */
 172 #define GTSR_MS_RES     0x4000  /* result: 1 = master, 0 = slave */
 173 #define GTSR_LRS        0x2000  /* local rx status, 1 = ok */
 174 #define GTSR_RRS        0x1000  /* remove rx status, 1 = ok */
 175 #define GTSR_LP_1000TFDX 0x0800 /* link partner 1000baseT FDX capable */
 176 #define GTSR_LP_1000THDX 0x0400 /* link partner 1000baseT HDX capable */
 177 #define GTSR_LP_ASM_DIR 0x0200  /* link partner asym. pause dir. capable */
 178 #define GTSR_IDLE_ERR   0x00ff  /* IDLE error count */
 179
 180 #define MII_EXTSR       0x0f    /* Extended status register */
 181 #define EXTSR_1000XFDX  0x8000  /* 1000X full-duplex capable */
 182 #define EXTSR_1000XHDX  0x4000  /* 1000X half-duplex capable */
 183 #define EXTSR_1000TFDX  0x2000  /* 1000T full-duplex capable */
 184 #define EXTSR_1000THDX  0x1000  /* 1000T half-duplex capable */
 185
 186 #define EXTSR_MEDIAMASK (EXTSR_1000XFDX|EXTSR_1000XHDX| \
 187                          EXTSR_1000TFDX|EXTSR_1000THDX)
 188
 189 #endif /* _DEV_MII_MII_H_ */