1 /* $NetBSD: nsphyterreg.h,v 1.4 2005/12/11 12:22:42 christos Exp $ */
4 * Copyright (c) 1999, 2001 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
33 #ifndef _DEV_MII_NSPHYTERREG_H_
34 #define _DEV_MII_NSPHYTERREG_H_
37 * DP83843 registers. We also have the MacPHYTER (DP83815) internal
38 * PHY register definitions here, since the two are, for our purposes,
42 #define MII_NSPHYTER_PHYSTS 0x10 /* PHY status */
43 #define PHYSTS_REL 0x8000 /* receive error latch */
44 #define PHYSTS_CIML 0x4000 /* CIM latch */
45 #define PHYSTS_FCSL 0x2000 /* false carrier sense latch */
46 #define PHYSTS_DEVRDY 0x0800 /* device ready */
47 #define PHYSTS_PGRX 0x0400 /* page received */
48 #define PHYSTS_ANEGEN 0x0200 /* autoneg. enabled */
49 #define PHYSTS_MIIINTR 0x0100 /* MII interrupt */
50 #define PHYSTS_REMFAULT 0x0080 /* remote fault */
51 #define PHYSTS_JABBER 0x0040 /* jabber detect */
52 #define PHYSTS_NWAYCOMP 0x0020 /* NWAY complete */
53 #define PHYSTS_RESETSTAT 0x0010 /* reset status */
54 #define PHYSTS_LOOPBACK 0x0008 /* loopback status */
55 #define PHYSTS_DUPLEX 0x0004 /* full duplex */
56 #define PHYSTS_SPEED10 0x0002 /* speed == 10Mb/s */
57 #define PHYSTS_LINK 0x0001 /* link up */
58 /* below are the MacPHYTER bits that are different */
59 #define PHYSTS_MP_REL 0x2000 /* receive error latch */
60 #define PHYSTS_MP_POLARITY 0x1000 /* polarity inverted */
61 #define PHYSTS_MP_FCSL 0x0800 /* false carrier sense latch */
62 #define PHYSTS_MP_SIGNAL 0x0400 /* signal detect */
63 #define PHYSTS_MP_DESCRLK 0x0200 /* de-scrambler lock */
64 #define PHYSTS_MP_PGRX 0x0100 /* page received */
65 #define PHYSTS_MP_MIIINTR 0x0080 /* MII interrupt */
66 #define PHYSTS_MP_REMFAULT 0x0040 /* remote fault */
67 #define PHYSTS_MP_JABBER 0x0020 /* jabber detect */
68 #define PHYSTS_MP_NWAYCOMP 0x0010 /* NWAY complete */
71 #define MII_NSPHYTER_MIPSCR 0x11 /* MII interrupt PHY specific
74 #define MIPSCR_INTEN 0x0002 /* interrupt enable */
75 #define MIPSCR_TINT 0x0001 /* test interrupt */
78 #define MII_NSPHYTER_MIPGSR 0x12 /* MII interrupt PHY generic
80 #define MIPGSR_MINT 0x8000 /* MII interrupt pending */
81 /* below are MacPHYTER only */
82 #define MIPGSR_MSK_LINK 0x4000 /* mask link status event */
83 #define MIPGSR_MSK_JAB 0x2000 /* mask jabber event */
84 #define MIPGSR_MSK_RF 0x1000 /* mask remote fault event */
85 #define MIPGSR_MSK_ANC 0x0800 /* mask auto-neg complete event */
86 #define MIPGSR_MSK_FHF 0x0400 /* mask false carrier half full event */
87 #define MIPGSR_MSK_RHF 0x0200 /* mask rx error half full event */
89 #define MII_NSPHYTER_DCR 0x13 /* Disconnect counter */
91 #define MII_NSPHYTER_FCSCR 0x14 /* False carrier sense counter */
93 #define MII_NSPHYTER_RECR 0x15 /* Receive error counter */
96 #define MII_NSPHYTER_PCSR 0x16 /* PCS configuration and status */
97 #define PCSR_SINGLE_SD 0x8000 /* single-ended SD mode */
98 #define PCSR_FEFI_EN 0x4000 /* far end fault indication mode */
99 #define PCSR_DESCR_TO_RST 0x2000 /* reset descrambler timeout counter */
100 #define PCSR_DESCR_TO_SEL 0x1000 /* descrambler timer mode */
101 #define PCSR_DESCR_TO_DIS 0x0800 /* descrambler timer disable */
102 #define PCSR_LD_SCR_SD 0x0400 /* load scrambler seed */
103 #define PCSR_TX_QUIET 0x0200 /* 100Mb/s transmit true quiet mode */
104 #define PCSR_TX_PATTERN 0x0180 /* 100Mb/s transmit test pattern */
105 #define PCSR_F_LINK_100 0x0040 /* force good link in 100Mb/s */
106 #define PCSR_CIM_DIS 0x0020 /* carrier integrity monitor disable */
107 #define PCSR_CIM_STATUS 0x0010 /* carrier integrity monitor status */
108 #define PCSR_CODE_ERR 0x0008 /* code errors */
109 #define PCSR_PME_ERR 0x0004 /* premature end errors */
110 #define PCSR_LINK_ERR 0x0002 /* link errors */
111 #define PCSR_PKT_ERR 0x0001 /* packet errors */
112 /* below are the MacPHYTER bits that are different */
113 #define PCSR_MP_BYP_4B5B 0x1000 /* bypass encoder */
114 #define PCSR_MP_FREE_CLK 0x0800 /* free funning rx clock */
115 #define PCSR_MP_TQ_EN 0x0400 /* enable True Quiet mode */
116 #define PCSR_MP_SD_FORCE_B 0x0200 /* force signal detection */
117 #define PCSR_MP_SD_OPTION 0x0100 /* enhanced signal detection alg. */
118 #define PCSR_MP_NRZI_BYPASS 0x0004 /* NRZI bypass enabled */
121 /* Not on MacPHYTER */
122 #define MII_NSPHYTER_LBR 0x17 /* loopback and bypass */
123 #define LBR_BP_STRETCH 0x4000 /* bypass LED stretching */
124 #define LBR_BP_4B5B 0x2000 /* bypass encoding/decoding */
125 #define LBR_BP_SCR 0x1000 /* bypass scrambler/descrambler */
126 #define LBR_BP_RX 0x0800 /* bypass receive function */
127 #define LBR_BP_TX 0x0400 /* bypass transmit function */
128 #define LBR_100_DP_CTL 0x0380 /* 100Mb/s data patch control */
129 #define LBR_TW_LBEN 0x0020 /* TWISTER loopback enable */
130 #define LBR_10_ENDEC_LB 0x0010 /* 10Mb/s ENDEC loopback */
133 /* Not on MacPHYTER */
134 #define MII_NSPHYTER_10BTSCR 0x18 /* 10baseT status and control */
135 #define BTSCR_AUI_TPI 0x2000 /* TREX operating mode */
136 #define BTSCR_RX_SERIAL 0x1000 /* 10baseT RX serial mode */
137 #define BTSCR_TX_SERIAL 0x0800 /* 10baseT TX serial mode */
138 #define BTSCR_POL_DS 0x0400 /* polarity detection and correction
140 #define BTSCR_AUTOSW_EN 0x0200 /* AUI/TPI autoswitch */
141 #define BTSCR_LP_DS 0x0100 /* link pulse disable */
142 #define BTSCR_HB_DS 0x0080 /* heartbeat disabled */
143 #define BTSCR_LS_SEL 0x0040 /* low squelch select */
144 #define BTSCR_AUI_SEL 0x0020 /* AUI select */
145 #define BTSCR_JAB_DS 0x0010 /* jabber disable */
146 #define BTSCR_THIN_SEL 0x0008 /* thin ethernet select */
147 #define BTSCR_TX_FILT_DS 0x0004 /* TPI receive filter disable */
150 #define MII_NSPHYTER_PHYCTRL 0x19 /* PHY control */
151 #define PHYCTRL_TW_EQSEL 0x3000 /* TWISTER e.q. select */
152 #define PHYCTRL_BLW_DS 0x0800 /* TWISTER base line wander disable */
153 #define PHYCTRL_REPEATER 0x0200 /* repeater mode */
154 #define PHYCTRL_LED_TXRX_MODE 0x0180 /* LED TX/RX mode */
155 #define PHYCTRL_LED_DUP_MODE 0x0040 /* LED DUP mode */
156 #define PHYCTRL_FX_EN 0x0020 /* Fiber mode enable */
157 #define PHYCTRL_PHYADDR 0x001f /* PHY address */
158 /* below are the MacPHYTER bits that are different */
159 #define PHYCRTL_MP_PSR_15 0x0800 /* BIST sequence select */
160 #define PHYCTRL_MP_BIST_STAT 0x0400 /* BIST passed */
161 #define PHYCTRL_MP_BIST_START 0x0200 /* start BIST */
162 #define PHYCTRL_MP_BP_STRETCH 0x0100 /* bypass LED stretching */
163 #define PHYCTRL_MP_PAUSE_STS 0x0080 /* pause status */
167 #define MII_MACPHYTER_TBTCTL 0x1a /* 10baseT Control */
168 #define TBTCTL_LOOPBACK_10_DIS 0x0100 /* loopback 10Mb/s disable */
169 #define TBTCTL_LP_DIS 0x0080 /* link pulse disable */
170 #define TBTCTL_FORCE_LINK_10 0x0040 /* force 10Mb/s link good */
171 #define TBTCTL_FORCE_POL_COR 0x0020 /* force polarity correction */
172 #define TBTCTL_INV_POLARITY 0x0010 /* inverted polarity */
173 #define TBTCTL_AUTOPOL_DIS 0x0008 /* auto-polarity disable */
174 #define TBTCTL_HEARTBEAT_DIS 0x0002 /* heartbeat disable */
175 #define TBTCTL_JABBER_DIS 0x0001 /* jabber disable */
177 #endif /* _DEV_MII_NSPHYTERREG_H_ */
