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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / pci / agp_amd64.c
blobb36820bcd8433d021404ffea6ddbb634c5a3c829
1 /*-
2 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: agp_amd64.c,v 1.4 2008/03/27 10:47:49 kiyohara Exp $");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/malloc.h>
33 #include <sys/kernel.h>
34 #include <sys/proc.h>
35 #include <sys/conf.h>
36 #include <sys/device.h>
37 #include <sys/agpio.h>
38
39 #include <uvm/uvm_extern.h>
40
41 #include <dev/pci/pcivar.h>
42 #include <dev/pci/pcireg.h>
43 #include <dev/pci/agpvar.h>
44 #include <dev/pci/agpreg.h>
45
46 #include <dev/pci/pcidevs.h>
47
48 #include <sys/bus.h>
49
50
51 #define AMD64_MAX_MCTRL 8
52
53 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
54 #define AGP_AMD64_NVIDIA_PCITAG(pc) pci_make_tag(pc, 0, 11, 0)
55 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
56 #define AGP_AMD64_VIA_PCITAG(pc) pci_make_tag(pc, 0, 1, 0)
57
58
59 static uint32_t agp_amd64_get_aperture(struct agp_softc *);
60 static int agp_amd64_set_aperture(struct agp_softc *, uint32_t);
61 static int agp_amd64_bind_page(struct agp_softc *, off_t, bus_addr_t);
62 static int agp_amd64_unbind_page(struct agp_softc *, off_t);
63 static void agp_amd64_flush_tlb(struct agp_softc *);
64
65 static void agp_amd64_apbase_fixup(struct agp_softc *);
66
67 static void agp_amd64_uli_init(struct agp_softc *);
68 static int agp_amd64_uli_set_aperture(struct agp_softc *, uint32_t);
69
70 static int agp_amd64_nvidia_match(const struct pci_attach_args *, uint16_t);
71 static void agp_amd64_nvidia_init(struct agp_softc *);
72 static int agp_amd64_nvidia_set_aperture(struct agp_softc *, uint32_t);
73
74 static int agp_amd64_via_match(const struct pci_attach_args *);
75 static void agp_amd64_via_init(struct agp_softc *);
76 static int agp_amd64_via_set_aperture(struct agp_softc *, uint32_t);
77
78
79 struct agp_amd64_softc {
80 uint32_t initial_aperture;
81 struct agp_gatt *gatt;
82 uint32_t apbase;
83 pcitag_t ctrl_tag; /* use NVIDIA and VIA */
84 pcitag_t mctrl_tag[AMD64_MAX_MCTRL];
85 int n_mctrl;
86 int via_agp;
87 };
88
89 static struct agp_methods agp_amd64_methods = {
90 agp_amd64_get_aperture,
91 agp_amd64_set_aperture,
92 agp_amd64_bind_page,
93 agp_amd64_unbind_page,
94 agp_amd64_flush_tlb,
95 agp_generic_enable,
96 agp_generic_alloc_memory,
97 agp_generic_free_memory,
98 agp_generic_bind_memory,
99 agp_generic_unbind_memory,
100 };
101
102
103 int
104 agp_amd64_match(const struct pci_attach_args *pa)
105 {
106
107 switch (PCI_VENDOR(pa->pa_id)) {
108 case PCI_VENDOR_AMD:
109 switch (PCI_PRODUCT(pa->pa_id)) {
110 case PCI_PRODUCT_AMD_AGP8151_DEV:
111 return 1;
112 }
113 break;
114
115 case PCI_VENDOR_SIS:
116 switch (PCI_PRODUCT(pa->pa_id)) {
117 case PCI_PRODUCT_SIS_755:
118 case PCI_PRODUCT_SIS_760:
119 return 1;
120 }
121 break;
122
123 case PCI_VENDOR_ALI:
124 switch (PCI_PRODUCT(pa->pa_id)) {
125 case PCI_PRODUCT_ALI_M1689:
126 return 1;
127 }
128 break;
129
130 case PCI_VENDOR_NVIDIA:
131 switch (PCI_PRODUCT(pa->pa_id)) {
132 case PCI_PRODUCT_NVIDIA_NFORCE3_PCHB:
133 return agp_amd64_nvidia_match(pa,
134 PCI_PRODUCT_NVIDIA_NFORCE3_PPB2);
135
136 /* NOTREACHED */
137
138 case PCI_PRODUCT_NVIDIA_NFORCE3_250_PCHB:
139 return agp_amd64_nvidia_match(pa,
140 PCI_PRODUCT_NVIDIA_NFORCE3_250_AGP);
141
142 /* NOTREACHED */
143 }
144 break;
145
146 case PCI_VENDOR_VIATECH:
147 switch (PCI_PRODUCT(pa->pa_id)) {
148 case PCI_PRODUCT_VIATECH_K8M800_0:
149 case PCI_PRODUCT_VIATECH_K8T890_0:
150 case PCI_PRODUCT_VIATECH_K8HTB_0:
151 case PCI_PRODUCT_VIATECH_K8HTB:
152 return 1;
153 }
154 break;
155 }
156
157 return 0;
158 }
159
160 static int
161 agp_amd64_nvidia_match(const struct pci_attach_args *pa, uint16_t devid)
162 {
163 pcitag_t tag;
164 pcireg_t reg;
165
166 tag = AGP_AMD64_NVIDIA_PCITAG(pa->pa_pc);
167
168 reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
169 if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
170 PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI)
171 return 0;
172
173 reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
174 if (PCI_VENDOR(reg) != PCI_VENDOR_NVIDIA || PCI_PRODUCT(reg) != devid)
175 return 0;
176
177 return 1;
178 }
179
180 static int
181 agp_amd64_via_match(const struct pci_attach_args *pa)
182 {
183 pcitag_t tag;
184 pcireg_t reg;
185
186 tag = AGP_AMD64_VIA_PCITAG(pa->pa_pc);
187
188 reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
189 if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
190 PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI)
191 return 0;
192
193 reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
194 if (PCI_VENDOR(reg) != PCI_VENDOR_VIATECH ||
195 PCI_PRODUCT(reg) != PCI_PRODUCT_VIATECH_K8HTB_AGP)
196 return 0;
197
198 return 1;
199 }
200
201 int
202 agp_amd64_attach(device_t parent, device_t self, void *aux)
203 {
204 struct agp_softc *sc = device_private(self);
205 struct agp_amd64_softc *asc;
206 struct pci_attach_args *pa = aux;
207 struct agp_gatt *gatt;
208 pcitag_t tag;
209 pcireg_t id, attbase, apctrl;
210 int maxdevs, i, n;
211
212 asc = malloc(sizeof(struct agp_amd64_softc), M_AGP, M_NOWAIT | M_ZERO);
213 if (asc == NULL) {
214 aprint_error(": can't allocate softc\n");
215 return ENOMEM;
216 }
217
218 if (agp_map_aperture(pa, sc, AGP_APBASE) != 0) {
219 aprint_error(": can't map aperture\n");
220 free(asc, M_AGP);
221 return ENXIO;
222 }
223
224 maxdevs = pci_bus_maxdevs(pa->pa_pc, 0);
225 for (i = 0, n = 0; i < maxdevs && n < AMD64_MAX_MCTRL; i++) {
226 tag = pci_make_tag(pa->pa_pc, 0, i, 3);
227 id = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
228 if (PCI_VENDOR(id) == PCI_VENDOR_AMD &&
229 PCI_PRODUCT(id) == PCI_PRODUCT_AMD_AMD64_MISC) {
230 asc->mctrl_tag[n] = tag;
231 n++;
232 }
233 }
234 if (n == 0)
235 return ENXIO;
236 asc->n_mctrl = n;
237
238 aprint_normal(": %d Miscellaneous Control unit(s) found.\n",
239 asc->n_mctrl);
240 aprint_normal("%s", device_xname(self));
241
242 sc->as_chipc = asc;
243 sc->as_methods = &agp_amd64_methods;
244 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff,
245 NULL);
246 asc->initial_aperture = AGP_GET_APERTURE(sc);
247
248 for (;;) {
249 gatt = agp_alloc_gatt(sc);
250 if (gatt)
251 break;
252
253 /*
254 * Probably contigmalloc failure. Try reducing the
255 * aperture so that the gatt size reduces.
256 */
257 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) {
258 agp_generic_detach(sc);
259 return ENOMEM;
260 }
261 }
262 asc->gatt = gatt;
263
264 switch (PCI_VENDOR(sc->as_id)) {
265 case PCI_VENDOR_ALI:
266 agp_amd64_uli_init(sc);
267 if (agp_amd64_uli_set_aperture(sc, asc->initial_aperture))
268 return ENXIO;
269 break;
270
271 case PCI_VENDOR_NVIDIA:
272 asc->ctrl_tag = AGP_AMD64_NVIDIA_PCITAG(pa->pa_pc);
273 agp_amd64_nvidia_init(sc);
274 if (agp_amd64_nvidia_set_aperture(sc, asc->initial_aperture))
275 return ENXIO;
276 break;
277
278 case PCI_VENDOR_VIATECH:
279 asc->via_agp = agp_amd64_via_match(pa);
280 if (asc->via_agp) {
281 asc->ctrl_tag = AGP_AMD64_VIA_PCITAG(pa->pa_pc);
282 agp_amd64_via_init(sc);
283 if (agp_amd64_via_set_aperture(sc,
284 asc->initial_aperture))
285 return ENXIO;
286 }
287 break;
288 }
289
290 /* Install the gatt and enable aperture. */
291 attbase = (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK;
292 for (i = 0; i < asc->n_mctrl; i++) {
293 pci_conf_write(pa->pa_pc, asc->mctrl_tag[i], AGP_AMD64_ATTBASE,
294 attbase);
295 apctrl = pci_conf_read(pa->pa_pc, asc->mctrl_tag[i],
296 AGP_AMD64_APCTRL);
297 apctrl |= AGP_AMD64_APCTRL_GARTEN;
298 apctrl &=
299 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO);
300 pci_conf_write(pa->pa_pc, asc->mctrl_tag[i], AGP_AMD64_APCTRL,
301 apctrl);
302 }
303
304 agp_flush_cache();
305
306 return 0;
307 }
308
309
310 static uint32_t agp_amd64_table[] = {
311 0x02000000, /* 32 MB */
312 0x04000000, /* 64 MB */
313 0x08000000, /* 128 MB */
314 0x10000000, /* 256 MB */
315 0x20000000, /* 512 MB */
316 0x40000000, /* 1024 MB */
317 0x80000000, /* 2048 MB */
318 };
319
320 #define AGP_AMD64_TABLE_SIZE \
321 (sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0]))
322
323 static uint32_t
324 agp_amd64_get_aperture(struct agp_softc *sc)
325 {
326 struct agp_amd64_softc *asc = sc->as_chipc;
327 uint32_t i;
328
329 i = (pci_conf_read(sc->as_pc, asc->mctrl_tag[0], AGP_AMD64_APCTRL) &
330 AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
331
332 if (i >= AGP_AMD64_TABLE_SIZE)
333 return 0;
334
335 return agp_amd64_table[i];
336 }
337
338 static int
339 agp_amd64_set_aperture(struct agp_softc *sc, uint32_t aperture)
340 {
341 struct agp_amd64_softc *asc = sc->as_chipc;
342 uint32_t i;
343 pcireg_t apctrl;
344 int j;
345
346 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
347 if (agp_amd64_table[i] == aperture)
348 break;
349 if (i >= AGP_AMD64_TABLE_SIZE)
350 return EINVAL;
351
352 for (j = 0; j < asc->n_mctrl; j++) {
353 apctrl = pci_conf_read(sc->as_pc, asc->mctrl_tag[0],
354 AGP_AMD64_APCTRL);
355 pci_conf_write(sc->as_pc, asc->mctrl_tag[0], AGP_AMD64_APCTRL,
356 (apctrl & ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1));
357 }
358
359 switch (PCI_VENDOR(sc->as_id)) {
360 case PCI_VENDOR_ALI:
361 return agp_amd64_uli_set_aperture(sc, aperture);
362 break;
363
364 case PCI_VENDOR_NVIDIA:
365 return agp_amd64_nvidia_set_aperture(sc, aperture);
366 break;
367
368 case PCI_VENDOR_VIATECH:
369 if (asc->via_agp)
370 return agp_amd64_via_set_aperture(sc, aperture);
371 break;
372 }
373
374 return 0;
375 }
376
377 static int
378 agp_amd64_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical)
379 {
380 struct agp_amd64_softc *asc = sc->as_chipc;
381
382 if (offset < 0 || offset >= (asc->gatt->ag_entries << AGP_PAGE_SHIFT))
383 return EINVAL;
384
385 asc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] =
386 (physical & 0xfffff000) | ((physical >> 28) & 0x00000ff0) | 3;
387
388 return 0;
389 }
390
391 static int
392 agp_amd64_unbind_page(struct agp_softc *sc, off_t offset)
393 {
394 struct agp_amd64_softc *asc = sc->as_chipc;
395
396 if (offset < 0 || offset >= (asc->gatt->ag_entries << AGP_PAGE_SHIFT))
397 return EINVAL;
398
399 asc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
400
401 return 0;
402 }
403
404 static void
405 agp_amd64_flush_tlb(struct agp_softc *sc)
406 {
407 struct agp_amd64_softc *asc = sc->as_chipc;
408 pcireg_t cachectrl;
409 int i;
410
411 for (i = 0; i < asc->n_mctrl; i++) {
412 cachectrl = pci_conf_read(sc->as_pc, asc->mctrl_tag[i],
413 AGP_AMD64_CACHECTRL);
414 pci_conf_write(sc->as_pc, asc->mctrl_tag[i],
415 AGP_AMD64_CACHECTRL,
416 cachectrl | AGP_AMD64_CACHECTRL_INVGART);
417 }
418 }
419
420 static void
421 agp_amd64_apbase_fixup(struct agp_softc *sc)
422 {
423 struct agp_amd64_softc *asc = sc->as_chipc;
424 uint32_t apbase;
425 int i;
426
427 apbase = pci_conf_read(sc->as_pc, sc->as_tag, AGP_APBASE);
428 asc->apbase = PCI_MAPREG_MEM_ADDR(apbase);
429 apbase = (asc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
430 for (i = 0; i < asc->n_mctrl; i++)
431 pci_conf_write(sc->as_pc, asc->mctrl_tag[i], AGP_AMD64_APBASE,
432 apbase);
433 }
434
435 static void
436 agp_amd64_uli_init(struct agp_softc *sc)
437 {
438 struct agp_amd64_softc *asc = sc->as_chipc;
439 pcireg_t apbase;
440
441 agp_amd64_apbase_fixup(sc);
442 apbase = pci_conf_read(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_APBASE);
443 pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_APBASE,
444 (apbase & 0x0000000f) | asc->apbase);
445 pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_HTT_FEATURE,
446 asc->apbase);
447 }
448
449 static int
450 agp_amd64_uli_set_aperture(struct agp_softc *sc, uint32_t aperture)
451 {
452 struct agp_amd64_softc *asc = sc->as_chipc;
453
454 switch (aperture) {
455 case 0x02000000: /* 32 MB */
456 case 0x04000000: /* 64 MB */
457 case 0x08000000: /* 128 MB */
458 case 0x10000000: /* 256 MB */
459 break;
460 default:
461 return EINVAL;
462 }
463
464 pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_ENU_SCR,
465 asc->apbase + aperture - 1);
466
467 return 0;
468 }
469
470 static void
471 agp_amd64_nvidia_init(struct agp_softc *sc)
472 {
473 struct agp_amd64_softc *asc = sc->as_chipc;
474 pcireg_t apbase;
475
476 agp_amd64_apbase_fixup(sc);
477 apbase =
478 pci_conf_read(sc->as_pc, sc->as_tag, AGP_AMD64_NVIDIA_0_APBASE);
479 pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_NVIDIA_0_APBASE,
480 (apbase & 0x0000000f) | asc->apbase);
481 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APBASE1,
482 asc->apbase);
483 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APBASE2,
484 asc->apbase);
485 }
486
487 static int
488 agp_amd64_nvidia_set_aperture(struct agp_softc *sc, uint32_t aperture)
489 {
490 struct agp_amd64_softc *asc = sc->as_chipc;
491 uint32_t apsize;
492
493 switch (aperture) {
494 case 0x02000000: apsize = 0x0f; break; /* 32 MB */
495 case 0x04000000: apsize = 0x0e; break; /* 64 MB */
496 case 0x08000000: apsize = 0x0c; break; /* 128 MB */
497 case 0x10000000: apsize = 0x08; break; /* 256 MB */
498 case 0x20000000: apsize = 0x00; break; /* 512 MB */
499 default:
500 return EINVAL;
501 }
502
503 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APSIZE,
504 (pci_conf_read(sc->as_pc, asc->ctrl_tag,
505 AGP_AMD64_NVIDIA_1_APSIZE) & 0xfffffff0) | apsize);
506 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APLIMIT1,
507 asc->apbase + aperture - 1);
508 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APLIMIT2,
509 asc->apbase + aperture - 1);
510
511 return 0;
512 }
513
514 static void
515 agp_amd64_via_init(struct agp_softc *sc)
516 {
517 struct agp_amd64_softc *asc = sc->as_chipc;
518
519 agp_amd64_apbase_fixup(sc);
520 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_ATTBASE,
521 asc->gatt->ag_physical);
522 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_GARTCTRL,
523 pci_conf_read(sc->as_pc, asc->ctrl_tag, AGP3_VIA_ATTBASE) | 0x180);
524 }
525
526 static int
527 agp_amd64_via_set_aperture(struct agp_softc *sc, uint32_t aperture)
528 {
529 struct agp_amd64_softc *asc = sc->as_chipc;
530 uint32_t apsize;
531
532 apsize = ((aperture - 1) >> 20) ^ 0xff;
533 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
534 return EINVAL;
535 pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_APSIZE,
536 (pci_conf_read(sc->as_pc, asc->ctrl_tag, AGP3_VIA_APSIZE) & ~0xff) |
537 apsize);
538
539 return 0;
540 }
NetBSD on the FriendlyARM MINI2440