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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / pci / ahc_pci.c
blob85f6a662cf8e3205e80959246516d039eb4ac508
1 /*
2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
5 *
6 * Copyright (c) 1994-2001 Justin T. Gibbs.
7 * Copyright (c) 2000-2001 Adaptec Inc.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
28 *
29 * NO WARRANTY
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
41 *
42 * $Id: ahc_pci.c,v 1.68 2009/11/26 15:17:08 njoly Exp $
43 *
44 * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $
45 *
46 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $
47 */
48 /*
49 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
50 */
51
52 #include <sys/cdefs.h>
53 __KERNEL_RCSID(0, "$NetBSD: ahc_pci.c,v 1.67 2009/09/02 11:10:37 tsutsui Exp $");
54
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/malloc.h>
58 #include <sys/kernel.h>
59 #include <sys/queue.h>
60 #include <sys/device.h>
61 #include <sys/reboot.h>
62
63 #include <sys/bus.h>
64 #include <sys/intr.h>
65
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
68
69
70 /* XXXX some i386 on-board chips act weird when memory-mapped */
71 #ifndef __i386__
72 #define AHC_ALLOW_MEMIO
73 #endif
74
75 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */
76 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */
77
78 #include <dev/ic/aic7xxx_osm.h>
79 #include <dev/ic/aic7xxx_inline.h>
80
81 #include <dev/ic/smc93cx6var.h>
82
83
84 static inline uint64_t
85 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
86 {
87 uint64_t id;
88
89 id = subvendor
90 | (subdevice << 16)
91 | ((uint64_t)vendor << 32)
92 | ((uint64_t)device << 48);
93
94 return (id);
95 }
96
97 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
98 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
99 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
100 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull
101 #define ID_9005_SISL_ID 0x0005900500000000ull
102 #define ID_AIC7850 0x5078900400000000ull
103 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull
104 #define ID_AIC7855 0x5578900400000000ull
105 #define ID_AIC7859 0x3860900400000000ull
106 #define ID_AHA_2930CU 0x3860900438699004ull
107 #define ID_AIC7860 0x6078900400000000ull
108 #define ID_AIC7860C 0x6078900478609004ull
109 #define ID_AHA_1480A 0x6075900400000000ull
110 #define ID_AHA_2940AU_0 0x6178900400000000ull
111 #define ID_AHA_2940AU_1 0x6178900478619004ull
112 #define ID_AHA_2940AU_CN 0x2178900478219004ull
113 #define ID_AHA_2930C_VAR 0x6038900438689004ull
114
115 #define ID_AIC7870 0x7078900400000000ull
116 #define ID_AHA_2940 0x7178900400000000ull
117 #define ID_AHA_3940 0x7278900400000000ull
118 #define ID_AHA_398X 0x7378900400000000ull
119 #define ID_AHA_2944 0x7478900400000000ull
120 #define ID_AHA_3944 0x7578900400000000ull
121 #define ID_AHA_4944 0x7678900400000000ull
122
123 #define ID_AIC7880 0x8078900400000000ull
124 #define ID_AIC7880_B 0x8078900478809004ull
125 #define ID_AHA_2940U 0x8178900400000000ull
126 #define ID_AHA_3940U 0x8278900400000000ull
127 #define ID_AHA_2944U 0x8478900400000000ull
128 #define ID_AHA_3944U 0x8578900400000000ull
129 #define ID_AHA_398XU 0x8378900400000000ull
130 #define ID_AHA_4944U 0x8678900400000000ull
131 #define ID_AHA_2940UB 0x8178900478819004ull
132 #define ID_AHA_2930U 0x8878900478889004ull
133 #define ID_AHA_2940U_PRO 0x8778900478879004ull
134 #define ID_AHA_2940U_CN 0x0078900478009004ull
135
136 #define ID_AIC7895 0x7895900478959004ull
137 #define ID_AIC7895_ARO 0x7890900478939004ull
138 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull
139 #define ID_AHA_2940U_DUAL 0x7895900478919004ull
140 #define ID_AHA_3940AU 0x7895900478929004ull
141 #define ID_AHA_3944AU 0x7895900478949004ull
142
143 #define ID_AIC7890 0x001F9005000F9005ull
144 #define ID_AIC7890_ARO 0x00139005000F9005ull
145 #define ID_AAA_131U2 0x0013900500039005ull
146 #define ID_AHA_2930U2 0x0011900501819005ull
147 #define ID_AHA_2940U2B 0x00109005A1009005ull
148 #define ID_AHA_2940U2_OEM 0x0010900521809005ull
149 #define ID_AHA_2940U2 0x00109005A1809005ull
150 #define ID_AHA_2950U2B 0x00109005E1009005ull
151
152 #define ID_AIC7892 0x008F9005FFFF9005ull
153 #define ID_AIC7892_ARO 0x00839005FFFF9005ull
154 #define ID_AHA_2915LP 0x0082900502109005ull
155 #define ID_AHA_29160 0x00809005E2A09005ull
156 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull
157 #define ID_AHA_29160N 0x0080900562A09005ull
158 #define ID_AHA_29160C 0x0080900562209005ull
159 #define ID_AHA_29160B 0x00809005E2209005ull
160 #define ID_AHA_19160B 0x0081900562A19005ull
161
162 #define ID_AIC7896 0x005F9005FFFF9005ull
163 #define ID_AIC7896_ARO 0x00539005FFFF9005ull
164 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull
165 #define ID_AHA_3950U2B_1 0x00509005F5009005ull
166 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull
167 #define ID_AHA_3950U2D_1 0x00519005B5009005ull
168
169 #define ID_AIC7899 0x00CF9005FFFF9005ull
170 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull
171 #define ID_AHA_3960D 0x00C09005F6209005ull
172 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull
173
174 #define ID_AIC7810 0x1078900400000000ull
175 #define ID_AIC7815 0x7815900400000000ull
176
177 #define DEVID_9005_TYPE(id) ((id) & 0xF)
178 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
179 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
180 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
181 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
182
183 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
184 #define DEVID_9005_MAXRATE_U160 0x0
185 #define DEVID_9005_MAXRATE_ULTRA2 0x1
186 #define DEVID_9005_MAXRATE_ULTRA 0x2
187 #define DEVID_9005_MAXRATE_FAST 0x3
188
189 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
190
191 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
192 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
193
194 #define SUBID_9005_TYPE(id) ((id) & 0xF)
195 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
196 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
197 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
198 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
199
200 #define SUBID_9005_TYPE_KNOWN(id) \
201 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
202 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
203 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
204 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
205
206 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
207 #define SUBID_9005_MAXRATE_ULTRA2 0x0
208 #define SUBID_9005_MAXRATE_ULTRA 0x1
209 #define SUBID_9005_MAXRATE_U160 0x2
210 #define SUBID_9005_MAXRATE_RESERVED 0x3
211
212 #define SUBID_9005_SEEPTYPE(id) \
213 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
214 ? ((id) & 0xC0) >> 6 \
215 : ((id) & 0x300) >> 8)
216 #define SUBID_9005_SEEPTYPE_NONE 0x0
217 #define SUBID_9005_SEEPTYPE_1K 0x1
218 #define SUBID_9005_SEEPTYPE_2K_4K 0x2
219 #define SUBID_9005_SEEPTYPE_RESERVED 0x3
220 #define SUBID_9005_AUTOTERM(id) \
221 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
222 ? (((id) & 0x400) >> 10) == 0 \
223 : (((id) & 0x40) >> 6) == 0)
224
225 #define SUBID_9005_NUMCHAN(id) \
226 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
227 ? ((id) & 0x300) >> 8 \
228 : ((id) & 0xC00) >> 10)
229
230 #define SUBID_9005_LEGACYCONN(id) \
231 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
232 ? 0 \
233 : ((id) & 0x80) >> 7)
234
235 #define SUBID_9005_MFUNCENB(id) \
236 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
237 ? ((id) & 0x800) >> 11 \
238 : ((id) & 0x1000) >> 12)
239 /*
240 * Informational only. Should use chip register to be
241 * certain, but may be use in identification strings.
242 */
243 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
244 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
245 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
246
247 static ahc_device_setup_t ahc_aic785X_setup;
248 static ahc_device_setup_t ahc_aic7860_setup;
249 static ahc_device_setup_t ahc_apa1480_setup;
250 static ahc_device_setup_t ahc_aic7870_setup;
251 static ahc_device_setup_t ahc_aha394X_setup;
252 static ahc_device_setup_t ahc_aha494X_setup;
253 static ahc_device_setup_t ahc_aha398X_setup;
254 static ahc_device_setup_t ahc_aic7880_setup;
255 static ahc_device_setup_t ahc_aha2940Pro_setup;
256 static ahc_device_setup_t ahc_aha394XU_setup;
257 static ahc_device_setup_t ahc_aha398XU_setup;
258 static ahc_device_setup_t ahc_aic7890_setup;
259 static ahc_device_setup_t ahc_aic7892_setup;
260 static ahc_device_setup_t ahc_aic7895_setup;
261 static ahc_device_setup_t ahc_aic7896_setup;
262 static ahc_device_setup_t ahc_aic7899_setup;
263 static ahc_device_setup_t ahc_aha29160C_setup;
264 static ahc_device_setup_t ahc_raid_setup;
265 static ahc_device_setup_t ahc_aha394XX_setup;
266 static ahc_device_setup_t ahc_aha494XX_setup;
267 static ahc_device_setup_t ahc_aha398XX_setup;
268
269 static struct ahc_pci_identity ahc_pci_ident_table [] =
270 {
271 /* aic7850 based controllers */
272 {
273 ID_AHA_2902_04_10_15_20_30C,
274 ID_ALL_MASK,
275 "Adaptec 2902/04/10/15/20/30C SCSI adapter",
276 ahc_aic785X_setup
277 },
278 /* aic7860 based controllers */
279 {
280 ID_AHA_2930CU,
281 ID_ALL_MASK,
282 "Adaptec 2930CU SCSI adapter",
283 ahc_aic7860_setup
284 },
285 {
286 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
287 ID_DEV_VENDOR_MASK,
288 "Adaptec 1480A Ultra SCSI adapter",
289 ahc_apa1480_setup
290 },
291 {
292 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
293 ID_DEV_VENDOR_MASK,
294 "Adaptec 2940A Ultra SCSI adapter",
295 ahc_aic7860_setup
296 },
297 {
298 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
299 ID_DEV_VENDOR_MASK,
300 "Adaptec 2940A/CN Ultra SCSI adapter",
301 ahc_aic7860_setup
302 },
303 {
304 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
305 ID_DEV_VENDOR_MASK,
306 "Adaptec 2930C Ultra SCSI adapter (VAR)",
307 ahc_aic7860_setup
308 },
309 /* aic7870 based controllers */
310 {
311 ID_AHA_2940,
312 ID_ALL_MASK,
313 "Adaptec 2940 SCSI adapter",
314 ahc_aic7870_setup
315 },
316 {
317 ID_AHA_3940,
318 ID_ALL_MASK,
319 "Adaptec 3940 SCSI adapter",
320 ahc_aha394X_setup
321 },
322 {
323 ID_AHA_398X,
324 ID_ALL_MASK,
325 "Adaptec 398X SCSI RAID adapter",
326 ahc_aha398X_setup
327 },
328 {
329 ID_AHA_2944,
330 ID_ALL_MASK,
331 "Adaptec 2944 SCSI adapter",
332 ahc_aic7870_setup
333 },
334 {
335 ID_AHA_3944,
336 ID_ALL_MASK,
337 "Adaptec 3944 SCSI adapter",
338 ahc_aha394X_setup
339 },
340 {
341 ID_AHA_4944,
342 ID_ALL_MASK,
343 "Adaptec 4944 SCSI adapter",
344 ahc_aha494X_setup
345 },
346 /* aic7880 based controllers */
347 {
348 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
349 ID_DEV_VENDOR_MASK,
350 "Adaptec 2940 Ultra SCSI adapter",
351 ahc_aic7880_setup
352 },
353 {
354 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
355 ID_DEV_VENDOR_MASK,
356 "Adaptec 3940 Ultra SCSI adapter",
357 ahc_aha394XU_setup
358 },
359 {
360 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
361 ID_DEV_VENDOR_MASK,
362 "Adaptec 2944 Ultra SCSI adapter",
363 ahc_aic7880_setup
364 },
365 {
366 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
367 ID_DEV_VENDOR_MASK,
368 "Adaptec 3944 Ultra SCSI adapter",
369 ahc_aha394XU_setup
370 },
371 {
372 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
373 ID_DEV_VENDOR_MASK,
374 "Adaptec 398X Ultra SCSI RAID adapter",
375 ahc_aha398XU_setup
376 },
377 {
378 /*
379 * XXX Don't know the slot numbers
380 * so we can't identify channels
381 */
382 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
383 ID_DEV_VENDOR_MASK,
384 "Adaptec 4944 Ultra SCSI adapter",
385 ahc_aic7880_setup
386 },
387 {
388 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
389 ID_DEV_VENDOR_MASK,
390 "Adaptec 2930 Ultra SCSI adapter",
391 ahc_aic7880_setup
392 },
393 {
394 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
395 ID_DEV_VENDOR_MASK,
396 "Adaptec 2940 Pro Ultra SCSI adapter",
397 ahc_aha2940Pro_setup
398 },
399 {
400 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
401 ID_DEV_VENDOR_MASK,
402 "Adaptec 2940/CN Ultra SCSI adapter",
403 ahc_aic7880_setup
404 },
405 /* Ignore all SISL (AAC on MB) based controllers. */
406 {
407 ID_9005_SISL_ID,
408 ID_9005_SISL_MASK,
409 NULL,
410 NULL
411 },
412 /* aic7890 based controllers */
413 {
414 ID_AHA_2930U2,
415 ID_ALL_MASK,
416 "Adaptec 2930 Ultra2 SCSI adapter",
417 ahc_aic7890_setup
418 },
419 {
420 ID_AHA_2940U2B,
421 ID_ALL_MASK,
422 "Adaptec 2940B Ultra2 SCSI adapter",
423 ahc_aic7890_setup
424 },
425 {
426 ID_AHA_2940U2_OEM,
427 ID_ALL_MASK,
428 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
429 ahc_aic7890_setup
430 },
431 {
432 ID_AHA_2940U2,
433 ID_ALL_MASK,
434 "Adaptec 2940 Ultra2 SCSI adapter",
435 ahc_aic7890_setup
436 },
437 {
438 ID_AHA_2950U2B,
439 ID_ALL_MASK,
440 "Adaptec 2950 Ultra2 SCSI adapter",
441 ahc_aic7890_setup
442 },
443 {
444 ID_AIC7890_ARO,
445 ID_ALL_MASK,
446 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
447 ahc_aic7890_setup
448 },
449 {
450 ID_AAA_131U2,
451 ID_ALL_MASK,
452 "Adaptec AAA-131 Ultra2 RAID adapter",
453 ahc_aic7890_setup
454 },
455 /* aic7892 based controllers */
456 {
457 ID_AHA_29160,
458 ID_ALL_MASK,
459 "Adaptec 29160 Ultra160 SCSI adapter",
460 ahc_aic7892_setup
461 },
462 {
463 ID_AHA_29160_CPQ,
464 ID_ALL_MASK,
465 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
466 ahc_aic7892_setup
467 },
468 {
469 ID_AHA_29160N,
470 ID_ALL_MASK,
471 "Adaptec 29160N Ultra160 SCSI adapter",
472 ahc_aic7892_setup
473 },
474 {
475 ID_AHA_29160C,
476 ID_ALL_MASK,
477 "Adaptec 29160C Ultra160 SCSI adapter",
478 ahc_aha29160C_setup
479 },
480 {
481 ID_AHA_29160B,
482 ID_ALL_MASK,
483 "Adaptec 29160B Ultra160 SCSI adapter",
484 ahc_aic7892_setup
485 },
486 {
487 ID_AHA_19160B,
488 ID_ALL_MASK,
489 "Adaptec 19160B Ultra160 SCSI adapter",
490 ahc_aic7892_setup
491 },
492 {
493 ID_AIC7892_ARO,
494 ID_ALL_MASK,
495 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
496 ahc_aic7892_setup
497 },
498 {
499 ID_AHA_2915LP,
500 ID_ALL_MASK,
501 "Adaptec 2915LP Ultra160 SCSI adapter",
502 ahc_aic7892_setup
503 },
504 /* aic7895 based controllers */
505 {
506 ID_AHA_2940U_DUAL,
507 ID_ALL_MASK,
508 "Adaptec 2940/DUAL Ultra SCSI adapter",
509 ahc_aic7895_setup
510 },
511 {
512 ID_AHA_3940AU,
513 ID_ALL_MASK,
514 "Adaptec 3940A Ultra SCSI adapter",
515 ahc_aic7895_setup
516 },
517 {
518 ID_AHA_3944AU,
519 ID_ALL_MASK,
520 "Adaptec 3944A Ultra SCSI adapter",
521 ahc_aic7895_setup
522 },
523 {
524 ID_AIC7895_ARO,
525 ID_AIC7895_ARO_MASK,
526 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
527 ahc_aic7895_setup
528 },
529 /* aic7896/97 based controllers */
530 {
531 ID_AHA_3950U2B_0,
532 ID_ALL_MASK,
533 "Adaptec 3950B Ultra2 SCSI adapter",
534 ahc_aic7896_setup
535 },
536 {
537 ID_AHA_3950U2B_1,
538 ID_ALL_MASK,
539 "Adaptec 3950B Ultra2 SCSI adapter",
540 ahc_aic7896_setup
541 },
542 {
543 ID_AHA_3950U2D_0,
544 ID_ALL_MASK,
545 "Adaptec 3950D Ultra2 SCSI adapter",
546 ahc_aic7896_setup
547 },
548 {
549 ID_AHA_3950U2D_1,
550 ID_ALL_MASK,
551 "Adaptec 3950D Ultra2 SCSI adapter",
552 ahc_aic7896_setup
553 },
554 {
555 ID_AIC7896_ARO,
556 ID_ALL_MASK,
557 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
558 ahc_aic7896_setup
559 },
560 /* aic7899 based controllers */
561 {
562 ID_AHA_3960D,
563 ID_ALL_MASK,
564 "Adaptec 3960D Ultra160 SCSI adapter",
565 ahc_aic7899_setup
566 },
567 {
568 ID_AHA_3960D_CPQ,
569 ID_ALL_MASK,
570 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
571 ahc_aic7899_setup
572 },
573 {
574 ID_AIC7899_ARO,
575 ID_ALL_MASK,
576 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
577 ahc_aic7899_setup
578 },
579 /* Generic chip probes for devices we don't know 'exactly' */
580 {
581 ID_AIC7850 & ID_DEV_VENDOR_MASK,
582 ID_DEV_VENDOR_MASK,
583 "Adaptec aic7850 SCSI adapter",
584 ahc_aic785X_setup
585 },
586 {
587 ID_AIC7855 & ID_DEV_VENDOR_MASK,
588 ID_DEV_VENDOR_MASK,
589 "Adaptec aic7855 SCSI adapter",
590 ahc_aic785X_setup
591 },
592 {
593 ID_AIC7859 & ID_DEV_VENDOR_MASK,
594 ID_DEV_VENDOR_MASK,
595 "Adaptec aic7859 SCSI adapter",
596 ahc_aic7860_setup
597 },
598 {
599 ID_AIC7860 & ID_DEV_VENDOR_MASK,
600 ID_DEV_VENDOR_MASK,
601 "Adaptec aic7860 Ultra SCSI adapter",
602 ahc_aic7860_setup
603 },
604 {
605 ID_AIC7870 & ID_DEV_VENDOR_MASK,
606 ID_DEV_VENDOR_MASK,
607 "Adaptec aic7870 SCSI adapter",
608 ahc_aic7870_setup
609 },
610 {
611 ID_AIC7880 & ID_DEV_VENDOR_MASK,
612 ID_DEV_VENDOR_MASK,
613 "Adaptec aic7880 Ultra SCSI adapter",
614 ahc_aic7880_setup
615 },
616 {
617 ID_AIC7890 & ID_9005_GENERIC_MASK,
618 ID_9005_GENERIC_MASK,
619 "Adaptec aic7890/91 Ultra2 SCSI adapter",
620 ahc_aic7890_setup
621 },
622 {
623 ID_AIC7892 & ID_9005_GENERIC_MASK,
624 ID_9005_GENERIC_MASK,
625 "Adaptec aic7892 Ultra160 SCSI adapter",
626 ahc_aic7892_setup
627 },
628 {
629 ID_AIC7895 & ID_DEV_VENDOR_MASK,
630 ID_DEV_VENDOR_MASK,
631 "Adaptec aic7895 Ultra SCSI adapter",
632 ahc_aic7895_setup
633 },
634 {
635 ID_AIC7896 & ID_9005_GENERIC_MASK,
636 ID_9005_GENERIC_MASK,
637 "Adaptec aic7896/97 Ultra2 SCSI adapter",
638 ahc_aic7896_setup
639 },
640 {
641 ID_AIC7899 & ID_9005_GENERIC_MASK,
642 ID_9005_GENERIC_MASK,
643 "Adaptec aic7899 Ultra160 SCSI adapter",
644 ahc_aic7899_setup
645 },
646 {
647 ID_AIC7810 & ID_DEV_VENDOR_MASK,
648 ID_DEV_VENDOR_MASK,
649 "Adaptec aic7810 RAID memory controller",
650 ahc_raid_setup
651 },
652 {
653 ID_AIC7815 & ID_DEV_VENDOR_MASK,
654 ID_DEV_VENDOR_MASK,
655 "Adaptec aic7815 RAID memory controller",
656 ahc_raid_setup
657 }
658 };
659
660 static const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table);
661
662 #define AHC_394X_SLOT_CHANNEL_A 4
663 #define AHC_394X_SLOT_CHANNEL_B 5
664
665 #define AHC_398X_SLOT_CHANNEL_A 4
666 #define AHC_398X_SLOT_CHANNEL_B 8
667 #define AHC_398X_SLOT_CHANNEL_C 12
668
669 #define AHC_494X_SLOT_CHANNEL_A 4
670 #define AHC_494X_SLOT_CHANNEL_B 5
671 #define AHC_494X_SLOT_CHANNEL_C 6
672 #define AHC_494X_SLOT_CHANNEL_D 7
673
674 #define DEVCONFIG 0x40
675 #define PCIERRGENDIS 0x80000000ul
676 #define SCBSIZE32 0x00010000ul /* aic789X only */
677 #define REXTVALID 0x00001000ul /* ultra cards only */
678 #define MPORTMODE 0x00000400ul /* aic7870+ only */
679 #define RAMPSM 0x00000200ul /* aic7870+ only */
680 #define VOLSENSE 0x00000100ul
681 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
682 #define SCBRAMSEL 0x00000080ul
683 #define MRDCEN 0x00000040ul
684 #define EXTSCBTIME 0x00000020ul /* aic7870 only */
685 #define EXTSCBPEN 0x00000010ul /* aic7870 only */
686 #define BERREN 0x00000008ul
687 #define DACEN 0x00000004ul
688 #define STPWLEVEL 0x00000002ul
689 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
690
691 #define CSIZE_LATTIME 0x0c
692 #define CACHESIZE 0x0000003ful /* only 5 bits */
693 #define LATTIME 0x0000ff00ul
694
695 /* PCI STATUS definitions */
696 #define DPE 0x80
697 #define SSE 0x40
698 #define RMA 0x20
699 #define RTA 0x10
700 #define STA 0x08
701 #define DPR 0x01
702
703 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
704 uint16_t subvendor, uint16_t subdevice);
705 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
706 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
707 int pcheck, int fast, int large);
708 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
709
710 static void ahc_pci_intr(struct ahc_softc *);
711
712 static const struct ahc_pci_identity *
713 ahc_find_pci_device(pcireg_t id, pcireg_t subid, u_int func)
714 {
715 u_int64_t full_id;
716 const struct ahc_pci_identity *entry;
717 u_int i;
718
719 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id),
720 PCI_PRODUCT(subid), PCI_VENDOR(subid));
721
722 /*
723 * If the second function is not hooked up, ignore it.
724 * Unfortunately, not all MB vendors implement the
725 * subdevice ID as per the Adaptec spec, so do our best
726 * to sanity check it prior to accepting the subdevice
727 * ID as valid.
728 */
729 if (func > 0
730 && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id),
731 PCI_VENDOR(subid), PCI_PRODUCT(subid))
732 && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0)
733 return (NULL);
734
735 for (i = 0; i < ahc_num_pci_devs; i++) {
736 entry = &ahc_pci_ident_table[i];
737 if (entry->full_id == (full_id & entry->id_mask))
738 return (entry);
739 }
740 return (NULL);
741 }
742
743 static int
744 ahc_pci_probe(device_t parent, cfdata_t match, void *aux)
745 {
746 struct pci_attach_args *pa = aux;
747 const struct ahc_pci_identity *entry;
748 pcireg_t subid;
749
750 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
751 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function);
752 return (entry != NULL && entry->setup != NULL) ? 1 : 0;
753 }
754
755 static void
756 ahc_pci_attach(device_t parent, device_t self, void *aux)
757 {
758 struct pci_attach_args *pa = aux;
759 const struct ahc_pci_identity *entry;
760 struct ahc_softc *ahc = device_private(self);
761 pcireg_t command;
762 u_int our_id = 0;
763 u_int sxfrctl1;
764 u_int scsiseq;
765 u_int sblkctl;
766 uint8_t dscommand0;
767 uint32_t devconfig;
768 int error;
769 pcireg_t subid;
770 int ioh_valid;
771 bus_space_tag_t st, iot;
772 bus_space_handle_t sh, ioh;
773 #ifdef AHC_ALLOW_MEMIO
774 int memh_valid;
775 bus_space_tag_t memt;
776 bus_space_handle_t memh;
777 pcireg_t memtype;
778 #endif
779 pci_intr_handle_t ih;
780 const char *intrstr;
781 struct ahc_pci_busdata *bd;
782 bool override_ultra;
783
784 ahc->sc_dev = self;
785 ahc_set_name(ahc, device_xname(ahc->sc_dev));
786 ahc->parent_dmat = pa->pa_dmat;
787
788 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
789 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
790 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function);
791 if (entry == NULL)
792 return;
793 printf(": %s\n", entry->name);
794
795 /* Keep information about the PCI bus */
796 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_NOWAIT);
797 if (bd == NULL) {
798 printf("%s: unable to allocate bus-specific data\n",
799 ahc_name(ahc));
800 return;
801 }
802 memset(bd, 0, sizeof(struct ahc_pci_busdata));
803
804 bd->pc = pa->pa_pc;
805 bd->tag = pa->pa_tag;
806 bd->func = pa->pa_function;
807 bd->dev = pa->pa_device;
808 bd->class = pa->pa_class;
809
810 ahc->bd = bd;
811
812 ahc->description = entry->name;
813
814 error = entry->setup(ahc);
815 if (error != 0)
816 return;
817
818 ioh_valid = 0;
819
820 #ifdef AHC_ALLOW_MEMIO
821 memh_valid = 0;
822 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR);
823 switch (memtype) {
824 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
825 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
826 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR,
827 memtype, 0, &memt, &memh, NULL, NULL) == 0);
828 break;
829 default:
830 memh_valid = 0;
831 }
832 #endif
833 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR,
834 PCI_MAPREG_TYPE_IO, 0, &iot,
835 &ioh, NULL, NULL) == 0);
836 #if 0
837 printf("%s: bus info: memt 0x%lx, memh 0x%lx, iot 0x%lx, ioh 0x%lx\n",
838 ahc_name(ahc), (u_long)memt, (u_long)memh, (u_long)iot,
839 (u_long)ioh);
840 #endif
841
842 if (ioh_valid) {
843 st = iot;
844 sh = ioh;
845 #ifdef AHC_ALLOW_MEMIO
846 } else if (memh_valid) {
847 st = memt;
848 sh = memh;
849 #endif
850 } else {
851 printf(": unable to map registers\n");
852 return;
853 }
854 ahc->tag = st;
855 ahc->bsh = sh;
856
857 ahc->chip |= AHC_PCI;
858 /*
859 * Before we continue probing the card, ensure that
860 * its interrupts are *disabled*. We don't want
861 * a misstep to hang the machine in an interrupt
862 * storm.
863 */
864 ahc_intr_enable(ahc, FALSE);
865
866 /*
867 * XXX somehow reading this once fails on some sparc64 systems.
868 * This may be a problem in the sparc64 PCI code. Doing it
869 * twice works around it.
870 */
871 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG);
872 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG);
873
874 /*
875 * If we need to support high memory, enable dual
876 * address cycles. This bit must be set to enable
877 * high address bit generation even if we are on a
878 * 64bit bus (PCI64BIT set in devconfig).
879 */
880 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
881
882 if (1/*bootverbose*/)
883 printf("%s: Enabling 39Bit Addressing\n",
884 ahc_name(ahc));
885 devconfig |= DACEN;
886 }
887
888 /* Ensure that pci error generation, a test feature, is disabled. */
889 devconfig |= PCIERRGENDIS;
890
891 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig);
892
893 /* Ensure busmastering is enabled */
894 command |= PCI_COMMAND_MASTER_ENABLE;
895 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
896
897 /*
898 * Disable PCI parity error reporting. Users typically
899 * do this to work around broken PCI chipsets that get
900 * the parity timing wrong and thus generate lots of spurious
901 * errors.
902 */
903 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
904 command &= ~PCI_COMMAND_PARITY_ENABLE;
905 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
906
907 /* On all PCI adapters, we allow SCB paging */
908 ahc->flags |= AHC_PAGESCBS;
909 error = ahc_softc_init(ahc);
910 if (error != 0)
911 goto error_out;
912
913 ahc->bus_intr = ahc_pci_intr;
914
915 /* Remember how the card was setup in case there is no SEEPROM */
916 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
917 ahc_pause(ahc);
918 if ((ahc->features & AHC_ULTRA2) != 0)
919 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
920 else
921 our_id = ahc_inb(ahc, SCSIID) & OID;
922 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
923 scsiseq = ahc_inb(ahc, SCSISEQ);
924 } else {
925 sxfrctl1 = STPWEN;
926 our_id = 7;
927 scsiseq = 0;
928 }
929
930 error = ahc_reset(ahc);
931 if (error != 0)
932 goto error_out;
933
934 if ((ahc->features & AHC_DT) != 0) {
935 u_int sfunct;
936
937 /* Perform ALT-Mode Setup */
938 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
939 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
940 ahc_outb(ahc, OPTIONMODE,
941 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
942 ahc_outb(ahc, SFUNCT, sfunct);
943
944 /* Normal mode setup */
945 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
946 |TARGCRCENDEN);
947 }
948
949 if (pci_intr_map(pa, &ih)) {
950 printf("%s: couldn't map interrupt\n", ahc_name(ahc));
951 ahc_free(ahc);
952 return;
953 }
954 intrstr = pci_intr_string(pa->pa_pc, ih);
955 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc);
956 if (ahc->ih == NULL) {
957 aprint_error_dev(ahc->sc_dev,
958 "couldn't establish interrupt\n");
959 if (intrstr != NULL)
960 aprint_error(" at %s", intrstr);
961 aprint_error("\n");
962 ahc_free(ahc);
963 return;
964 }
965 if (intrstr != NULL)
966 printf("%s: interrupting at %s\n", ahc_name(ahc), intrstr);
967
968 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
969 dscommand0 |= MPARCKEN|CACHETHEN;
970 if ((ahc->features & AHC_ULTRA2) != 0) {
971
972 /*
973 * DPARCKEN doesn't work correctly on
974 * some MBs so don't use it.
975 */
976 dscommand0 &= ~DPARCKEN;
977 }
978
979 /*
980 * Handle chips that must have cache line
981 * streaming (dis/en)abled.
982 */
983 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
984 dscommand0 |= CACHETHEN;
985
986 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
987 dscommand0 &= ~CACHETHEN;
988
989 ahc_outb(ahc, DSCOMMAND0, dscommand0);
990
991 ahc->pci_cachesize =
992 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME) & CACHESIZE;
993 ahc->pci_cachesize *= 4;
994
995 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
996 && ahc->pci_cachesize == 4) {
997 pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME, 0);
998 ahc->pci_cachesize = 0;
999 }
1000
1001 /*
1002 * We cannot perform ULTRA speeds without the presence
1003 * of the external precision resistor.
1004 * Allow override for the SGI O2 though, which has two onboard ahc
1005 * that fail here but are perfectly capable of ultra speeds.
1006 */
1007 override_ultra = FALSE;
1008 prop_dictionary_get_bool(device_properties(self),
1009 "aic7xxx-override-ultra", &override_ultra);
1010
1011 if (((ahc->features & AHC_ULTRA) != 0) && (!override_ultra)) {
1012 uint32_t dvconfig;
1013
1014 dvconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG);
1015 if ((dvconfig & REXTVALID) == 0)
1016 ahc->features &= ~AHC_ULTRA;
1017 }
1018
1019 ahc->seep_config = malloc(sizeof(*ahc->seep_config),
1020 M_DEVBUF, M_NOWAIT);
1021 if (ahc->seep_config == NULL)
1022 goto error_out;
1023
1024 memset(ahc->seep_config, 0, sizeof(*ahc->seep_config));
1025
1026 /* See if we have a SEEPROM and perform auto-term */
1027 ahc_check_extport(ahc, &sxfrctl1);
1028
1029 /*
1030 * Take the LED out of diagnostic mode
1031 */
1032 sblkctl = ahc_inb(ahc, SBLKCTL);
1033 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
1034
1035 if ((ahc->features & AHC_ULTRA2) != 0) {
1036 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
1037 } else {
1038 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
1039 }
1040
1041 if (ahc->flags & AHC_USEDEFAULTS) {
1042 /*
1043 * PCI Adapter default setup
1044 * Should only be used if the adapter does not have
1045 * a SEEPROM.
1046 */
1047 /* See if someone else set us up already */
1048 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
1049 && scsiseq != 0) {
1050 prop_bool_t usetd;
1051
1052 printf("%s: Using left over BIOS settings\n",
1053 ahc_name(ahc));
1054 ahc->flags &= ~AHC_USEDEFAULTS;
1055 /*
1056 * Ignore target device settings and use default
1057 * if BIOS initializes chip's SRAM with some
1058 * conservative settings (async, no tagged
1059 * queuing etc.) and machine dependent device
1060 * property is set.
1061 */
1062 usetd = prop_dictionary_get(
1063 device_properties(ahc->sc_dev),
1064 "aic7xxx-use-target-defaults");
1065 if (usetd != NULL) {
1066 KASSERT(prop_object_type(usetd) ==
1067 PROP_TYPE_BOOL);
1068 if (prop_bool_true(usetd))
1069 ahc->flags |= AHC_USETARGETDEFAULTS;
1070 }
1071 ahc->flags |= AHC_BIOS_ENABLED;
1072 } else {
1073 /*
1074 * Assume only one connector and always turn
1075 * on termination.
1076 */
1077 our_id = 0x07;
1078 sxfrctl1 = STPWEN;
1079 }
1080 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
1081
1082 ahc->our_id = our_id;
1083 }
1084
1085 /*
1086 * Take a look to see if we have external SRAM.
1087 * We currently do not attempt to use SRAM that is
1088 * shared among multiple controllers.
1089 */
1090 ahc_probe_ext_scbram(ahc);
1091
1092 /*
1093 * Record our termination setting for the
1094 * generic initialization routine.
1095 */
1096 if ((sxfrctl1 & STPWEN) != 0)
1097 ahc->flags |= AHC_TERM_ENB_A;
1098
1099 if (ahc_init(ahc))
1100 goto error_out;
1101
1102 ahc_attach(ahc);
1103
1104 return;
1105
1106 error_out:
1107 ahc_free(ahc);
1108 return;
1109 }
1110
1111 CFATTACH_DECL_NEW(ahc_pci, sizeof(struct ahc_softc),
1112 ahc_pci_probe, ahc_pci_attach, NULL, NULL);
1113
1114 static int
1115 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
1116 uint16_t subdevice, uint16_t subvendor)
1117 {
1118 int result;
1119
1120 /* Default to invalid. */
1121 result = 0;
1122 if (vendor == 0x9005
1123 && subvendor == 0x9005
1124 && subdevice != device
1125 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
1126
1127 switch (SUBID_9005_TYPE(subdevice)) {
1128 case SUBID_9005_TYPE_MB:
1129 break;
1130 case SUBID_9005_TYPE_CARD:
1131 case SUBID_9005_TYPE_LCCARD:
1132 /*
1133 * Currently only trust Adaptec cards to
1134 * get the sub device info correct.
1135 */
1136 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
1137 result = 1;
1138 break;
1139 case SUBID_9005_TYPE_RAID:
1140 break;
1141 default:
1142 break;
1143 }
1144 }
1145 return (result);
1146 }
1147
1148
1149 /*
1150 * Test for the presense of external sram in an
1151 * "unshared" configuration.
1152 */
1153 static int
1154 ahc_ext_scbram_present(struct ahc_softc *ahc)
1155 {
1156 u_int chip;
1157 int ramps;
1158 int single_user;
1159 uint32_t devconfig;
1160
1161 chip = ahc->chip & AHC_CHIPID_MASK;
1162 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG);
1163 single_user = (devconfig & MPORTMODE) != 0;
1164
1165 if ((ahc->features & AHC_ULTRA2) != 0)
1166 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
1167 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
1168 /*
1169 * External SCBRAM arbitration is flakey
1170 * on these chips. Unfortunately this means
1171 * we don't use the extra SCB ram space on the
1172 * 3940AUW.
1173 */
1174 ramps = 0;
1175 else if (chip >= AHC_AIC7870)
1176 ramps = (devconfig & RAMPSM) != 0;
1177 else
1178 ramps = 0;
1179
1180 if (ramps && single_user)
1181 return (1);
1182 return (0);
1183 }
1184
1185 /*
1186 * Enable external scbram.
1187 */
1188 static void
1189 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1190 int fast, int large)
1191 {
1192 uint32_t devconfig;
1193
1194 if (ahc->features & AHC_MULTI_FUNC) {
1195 /*
1196 * Set the SCB Base addr (highest address bit)
1197 * depending on which channel we are.
1198 */
1199 ahc_outb(ahc, SCBBADDR, ahc->bd->func);
1200 }
1201
1202 ahc->flags &= ~AHC_LSCBS_ENABLED;
1203 if (large)
1204 ahc->flags |= AHC_LSCBS_ENABLED;
1205 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG);
1206 if ((ahc->features & AHC_ULTRA2) != 0) {
1207 u_int dscommand0;
1208
1209 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1210 if (enable)
1211 dscommand0 &= ~INTSCBRAMSEL;
1212 else
1213 dscommand0 |= INTSCBRAMSEL;
1214 if (large)
1215 dscommand0 &= ~USCBSIZE32;
1216 else
1217 dscommand0 |= USCBSIZE32;
1218 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1219 } else {
1220 if (fast)
1221 devconfig &= ~EXTSCBTIME;
1222 else
1223 devconfig |= EXTSCBTIME;
1224 if (enable)
1225 devconfig &= ~SCBRAMSEL;
1226 else
1227 devconfig |= SCBRAMSEL;
1228 if (large)
1229 devconfig &= ~SCBSIZE32;
1230 else
1231 devconfig |= SCBSIZE32;
1232 }
1233 if (pcheck)
1234 devconfig |= EXTSCBPEN;
1235 else
1236 devconfig &= ~EXTSCBPEN;
1237
1238 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig);
1239 }
1240
1241 /*
1242 * Take a look to see if we have external SRAM.
1243 * We currently do not attempt to use SRAM that is
1244 * shared among multiple controllers.
1245 */
1246 static void
1247 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1248 {
1249 int num_scbs;
1250 int test_num_scbs;
1251 int enable;
1252 int pcheck;
1253 int fast;
1254 int large;
1255
1256 enable = FALSE;
1257 pcheck = FALSE;
1258 fast = FALSE;
1259 large = FALSE;
1260 num_scbs = 0;
1261
1262 if (ahc_ext_scbram_present(ahc) == 0)
1263 goto done;
1264
1265 /*
1266 * Probe for the best parameters to use.
1267 */
1268 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1269 num_scbs = ahc_probe_scbs(ahc);
1270 if (num_scbs == 0) {
1271 /* The SRAM wasn't really present. */
1272 goto done;
1273 }
1274 enable = TRUE;
1275
1276 /*
1277 * Clear any outstanding parity error
1278 * and ensure that parity error reporting
1279 * is enabled.
1280 */
1281 ahc_outb(ahc, SEQCTL, 0);
1282 ahc_outb(ahc, CLRINT, CLRPARERR);
1283 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1284
1285 /* Now see if we can do parity */
1286 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1287 num_scbs = ahc_probe_scbs(ahc);
1288 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1289 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1290 pcheck = TRUE;
1291
1292 /* Clear any resulting parity error */
1293 ahc_outb(ahc, CLRINT, CLRPARERR);
1294 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1295
1296 /* Now see if we can do fast timing */
1297 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1298 test_num_scbs = ahc_probe_scbs(ahc);
1299 if (test_num_scbs == num_scbs
1300 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1301 || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1302 fast = TRUE;
1303
1304 /*
1305 * See if we can use large SCBs and still maintain
1306 * the same overall count of SCBs.
1307 */
1308 if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1309 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1310 test_num_scbs = ahc_probe_scbs(ahc);
1311 if (test_num_scbs >= num_scbs) {
1312 large = TRUE;
1313 num_scbs = test_num_scbs;
1314 if (num_scbs >= 64) {
1315 /*
1316 * We have enough space to move the
1317 * "busy targets table" into SCB space
1318 * and make it qualify all the way to the
1319 * lun level.
1320 */
1321 ahc->flags |= AHC_SCB_BTT;
1322 }
1323 }
1324 }
1325 done:
1326 /*
1327 * Disable parity error reporting until we
1328 * can load instruction ram.
1329 */
1330 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1331 /* Clear any latched parity error */
1332 ahc_outb(ahc, CLRINT, CLRPARERR);
1333 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1334 if (1/*bootverbose*/ && enable) {
1335 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1336 ahc_name(ahc), fast ? "fast" : "slow",
1337 pcheck ? ", parity checking enabled" : "",
1338 large ? 64 : 32);
1339 }
1340 ahc_scbram_config(ahc, enable, pcheck, fast, large);
1341 }
1342
1343 #if 0
1344 /*
1345 * Perform some simple tests that should catch situations where
1346 * our registers are invalidly mapped.
1347 */
1348 static int
1349 ahc_pci_test_register_access(struct ahc_softc *ahc)
1350 {
1351 int error;
1352 u_int status1;
1353 uint32_t cmd;
1354 uint8_t hcntrl;
1355
1356 error = EIO;
1357
1358 /*
1359 * Enable PCI error interrupt status, but suppress NMIs
1360 * generated by SERR raised due to target aborts.
1361 */
1362 cmd = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND);
1363 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND,
1364 cmd & ~PCIM_CMD_SERRESPEN);
1365
1366 /*
1367 * First a simple test to see if any
1368 * registers can be read. Reading
1369 * HCNTRL has no side effects and has
1370 * at least one bit that is guaranteed to
1371 * be zero so it is a good register to
1372 * use for this test.
1373 */
1374 hcntrl = ahc_inb(ahc, HCNTRL);
1375 if (hcntrl == 0xFF)
1376 goto fail;
1377
1378 /*
1379 * Next create a situation where write combining
1380 * or read prefetching could be initiated by the
1381 * CPU or host bridge. Our device does not support
1382 * either, so look for data corruption and/or flagged
1383 * PCI errors.
1384 */
1385 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1386 while (ahc_is_paused(ahc) == 0)
1387 ;
1388 ahc_outb(ahc, SEQCTL, PERRORDIS);
1389 ahc_outb(ahc, SCBPTR, 0);
1390 ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1391 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1392 goto fail;
1393
1394 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag,
1395 PCI_COMMAND_STATUS_REG + 1);
1396 if ((status1 & STA) != 0)
1397 goto fail;
1398
1399 error = 0;
1400
1401 fail:
1402 /* Silently clear any latched errors. */
1403 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag,
1404 PCI_COMMAND_STATUS_REG + 1);
1405 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1406 status1, /*bytes*/1);
1407 ahc_outb(ahc, CLRINT, CLRPARERR);
1408 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1409 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1410 return (error);
1411 }
1412 #endif
1413
1414 static void
1415 ahc_pci_intr(struct ahc_softc *ahc)
1416 {
1417 u_int error;
1418 u_int status1;
1419
1420 error = ahc_inb(ahc, ERROR);
1421 if ((error & PCIERRSTAT) == 0)
1422 return;
1423
1424 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag,
1425 PCI_COMMAND_STATUS_REG);
1426
1427 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
1428 ahc_name(ahc),
1429 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
1430
1431 if (status1 & DPE) {
1432 printf("%s: Data Parity Error Detected during address "
1433 "or write data phase\n", ahc_name(ahc));
1434 }
1435 if (status1 & SSE) {
1436 printf("%s: Signal System Error Detected\n", ahc_name(ahc));
1437 }
1438 if (status1 & RMA) {
1439 printf("%s: Received a Master Abort\n", ahc_name(ahc));
1440 }
1441 if (status1 & RTA) {
1442 printf("%s: Received a Target Abort\n", ahc_name(ahc));
1443 }
1444 if (status1 & STA) {
1445 printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
1446 }
1447 if (status1 & DPR) {
1448 printf("%s: Data Parity Error has been reported via PERR#\n",
1449 ahc_name(ahc));
1450 }
1451
1452 /* Clear latched errors. */
1453 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG,
1454 status1);
1455
1456 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
1457 printf("%s: Latched PCIERR interrupt with "
1458 "no status bits set\n", ahc_name(ahc));
1459 } else {
1460 ahc_outb(ahc, CLRINT, CLRPARERR);
1461 }
1462
1463 ahc_unpause(ahc);
1464 }
1465
1466 static int
1467 ahc_aic785X_setup(struct ahc_softc *ahc)
1468 {
1469 uint8_t rev;
1470
1471 ahc->channel = 'A';
1472 ahc->chip = AHC_AIC7850;
1473 ahc->features = AHC_AIC7850_FE;
1474 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
1475 rev = PCI_REVISION(ahc->bd->class);
1476 if (rev >= 1)
1477 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
1478 return (0);
1479 }
1480
1481 static int
1482 ahc_aic7860_setup(struct ahc_softc *ahc)
1483 {
1484 uint8_t rev;
1485
1486 ahc->channel = 'A';
1487 ahc->chip = AHC_AIC7860;
1488 ahc->features = AHC_AIC7860_FE;
1489 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
1490 rev = PCI_REVISION(ahc->bd->class);
1491 if (rev >= 1)
1492 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
1493 return (0);
1494 }
1495
1496 static int
1497 ahc_apa1480_setup(struct ahc_softc *ahc)
1498 {
1499 int error;
1500
1501 error = ahc_aic7860_setup(ahc);
1502 if (error != 0)
1503 return (error);
1504 ahc->features |= AHC_REMOVABLE;
1505 return (0);
1506 }
1507
1508 static int
1509 ahc_aic7870_setup(struct ahc_softc *ahc)
1510 {
1511
1512 ahc->channel = 'A';
1513 ahc->chip = AHC_AIC7870;
1514 ahc->features = AHC_AIC7870_FE;
1515 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
1516 return (0);
1517 }
1518
1519 static int
1520 ahc_aha394X_setup(struct ahc_softc *ahc)
1521 {
1522 int error;
1523
1524 error = ahc_aic7870_setup(ahc);
1525 if (error == 0)
1526 error = ahc_aha394XX_setup(ahc);
1527 return (error);
1528 }
1529
1530 static int
1531 ahc_aha398X_setup(struct ahc_softc *ahc)
1532 {
1533 int error;
1534
1535 error = ahc_aic7870_setup(ahc);
1536 if (error == 0)
1537 error = ahc_aha398XX_setup(ahc);
1538 return (error);
1539 }
1540
1541 static int
1542 ahc_aha494X_setup(struct ahc_softc *ahc)
1543 {
1544 int error;
1545
1546 error = ahc_aic7870_setup(ahc);
1547 if (error == 0)
1548 error = ahc_aha494XX_setup(ahc);
1549 return (error);
1550 }
1551
1552 static int
1553 ahc_aic7880_setup(struct ahc_softc *ahc)
1554 {
1555 uint8_t rev;
1556
1557 ahc->channel = 'A';
1558 ahc->chip = AHC_AIC7880;
1559 ahc->features = AHC_AIC7880_FE;
1560 ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
1561 rev = PCI_REVISION(ahc->bd->class);
1562 if (rev >= 1) {
1563 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
1564 } else {
1565 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
1566 }
1567 return (0);
1568 }
1569
1570 static int
1571 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
1572 {
1573
1574 ahc->flags |= AHC_INT50_SPEEDFLEX;
1575 return (ahc_aic7880_setup(ahc));
1576 }
1577
1578 static int
1579 ahc_aha394XU_setup(struct ahc_softc *ahc)
1580 {
1581 int error;
1582
1583 error = ahc_aic7880_setup(ahc);
1584 if (error == 0)
1585 error = ahc_aha394XX_setup(ahc);
1586 return (error);
1587 }
1588
1589 static int
1590 ahc_aha398XU_setup(struct ahc_softc *ahc)
1591 {
1592 int error;
1593
1594 error = ahc_aic7880_setup(ahc);
1595 if (error == 0)
1596 error = ahc_aha398XX_setup(ahc);
1597 return (error);
1598 }
1599
1600 static int
1601 ahc_aic7890_setup(struct ahc_softc *ahc)
1602 {
1603 uint8_t rev;
1604
1605 ahc->channel = 'A';
1606 ahc->chip = AHC_AIC7890;
1607 ahc->features = AHC_AIC7890_FE;
1608 ahc->flags |= AHC_NEWEEPROM_FMT;
1609 rev = PCI_REVISION(ahc->bd->class);
1610 if (rev == 0)
1611 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
1612 return (0);
1613 }
1614
1615 static int
1616 ahc_aic7892_setup(struct ahc_softc *ahc)
1617 {
1618
1619 ahc->channel = 'A';
1620 ahc->chip = AHC_AIC7892;
1621 ahc->features = AHC_AIC7892_FE;
1622 ahc->flags |= AHC_NEWEEPROM_FMT;
1623 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
1624 return (0);
1625 }
1626
1627 static int
1628 ahc_aic7895_setup(struct ahc_softc *ahc)
1629 {
1630 uint8_t rev;
1631
1632 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A';
1633 /*
1634 * The 'C' revision of the aic7895 has a few additional features.
1635 */
1636 rev = PCI_REVISION(ahc->bd->class);
1637 if (rev >= 4) {
1638 ahc->chip = AHC_AIC7895C;
1639 ahc->features = AHC_AIC7895C_FE;
1640 } else {
1641 u_int command;
1642
1643 ahc->chip = AHC_AIC7895;
1644 ahc->features = AHC_AIC7895_FE;
1645
1646 /*
1647 * The BIOS disables the use of MWI transactions
1648 * since it does not have the MWI bug work around
1649 * we have. Disabling MWI reduces performance, so
1650 * turn it on again.
1651 */
1652 command = pci_conf_read(ahc->bd->pc, ahc->bd->tag,
1653 PCI_COMMAND_STATUS_REG);
1654 command |= PCI_COMMAND_INVALIDATE_ENABLE;
1655 pci_conf_write(ahc->bd->pc, ahc->bd->tag,
1656 PCI_COMMAND_STATUS_REG, command);
1657 ahc->bugs |= AHC_PCI_MWI_BUG;
1658 }
1659 /*
1660 * XXX Does CACHETHEN really not work??? What about PCI retry?
1661 * on C level chips. Need to test, but for now, play it safe.
1662 */
1663 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
1664 | AHC_CACHETHEN_BUG;
1665
1666 #if 0
1667 uint32_t devconfig;
1668
1669 /*
1670 * Cachesize must also be zero due to stray DAC
1671 * problem when sitting behind some bridges.
1672 */
1673 pci_conf_write(ahc->bd->pc, ahc->bd->tag, CSIZE_LATTIME, 0);
1674 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG);
1675 devconfig |= MRDCEN;
1676 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig);
1677 #endif
1678 ahc->flags |= AHC_NEWEEPROM_FMT;
1679 return (0);
1680 }
1681
1682 static int
1683 ahc_aic7896_setup(struct ahc_softc *ahc)
1684 {
1685 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A';
1686 ahc->chip = AHC_AIC7896;
1687 ahc->features = AHC_AIC7896_FE;
1688 ahc->flags |= AHC_NEWEEPROM_FMT;
1689 ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
1690 return (0);
1691 }
1692
1693 static int
1694 ahc_aic7899_setup(struct ahc_softc *ahc)
1695 {
1696 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A';
1697 ahc->chip = AHC_AIC7899;
1698 ahc->features = AHC_AIC7899_FE;
1699 ahc->flags |= AHC_NEWEEPROM_FMT;
1700 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
1701 return (0);
1702 }
1703
1704 static int
1705 ahc_aha29160C_setup(struct ahc_softc *ahc)
1706 {
1707 int error;
1708
1709 error = ahc_aic7899_setup(ahc);
1710 if (error != 0)
1711 return (error);
1712 ahc->features |= AHC_REMOVABLE;
1713 return (0);
1714 }
1715
1716 static int
1717 ahc_raid_setup(struct ahc_softc *ahc)
1718 {
1719 aprint_normal_dev(ahc->sc_dev, "RAID functionality unsupported\n");
1720 return (ENXIO);
1721 }
1722
1723 static int
1724 ahc_aha394XX_setup(struct ahc_softc *ahc)
1725 {
1726
1727 switch (ahc->bd->dev) {
1728 case AHC_394X_SLOT_CHANNEL_A:
1729 ahc->channel = 'A';
1730 break;
1731 case AHC_394X_SLOT_CHANNEL_B:
1732 ahc->channel = 'B';
1733 break;
1734 default:
1735 printf("adapter at unexpected slot %d\n"
1736 "unable to map to a channel\n",
1737 ahc->bd->dev);
1738 ahc->channel = 'A';
1739 }
1740 return (0);
1741 }
1742
1743 static int
1744 ahc_aha398XX_setup(struct ahc_softc *ahc)
1745 {
1746
1747 switch (ahc->bd->dev) {
1748 case AHC_398X_SLOT_CHANNEL_A:
1749 ahc->channel = 'A';
1750 break;
1751 case AHC_398X_SLOT_CHANNEL_B:
1752 ahc->channel = 'B';
1753 break;
1754 case AHC_398X_SLOT_CHANNEL_C:
1755 ahc->channel = 'C';
1756 break;
1757 default:
1758 printf("adapter at unexpected slot %d\n"
1759 "unable to map to a channel\n",
1760 ahc->bd->dev);
1761 ahc->channel = 'A';
1762 break;
1763 }
1764 ahc->flags |= AHC_LARGE_SEEPROM;
1765 return (0);
1766 }
1767
1768 static int
1769 ahc_aha494XX_setup(struct ahc_softc *ahc)
1770 {
1771
1772 switch (ahc->bd->dev) {
1773 case AHC_494X_SLOT_CHANNEL_A:
1774 ahc->channel = 'A';
1775 break;
1776 case AHC_494X_SLOT_CHANNEL_B:
1777 ahc->channel = 'B';
1778 break;
1779 case AHC_494X_SLOT_CHANNEL_C:
1780 ahc->channel = 'C';
1781 break;
1782 case AHC_494X_SLOT_CHANNEL_D:
1783 ahc->channel = 'D';
1784 break;
1785 default:
1786 printf("adapter at unexpected slot %d\n"
1787 "unable to map to a channel\n",
1788 ahc->bd->dev);
1789 ahc->channel = 'A';
1790 }
1791 ahc->flags |= AHC_LARGE_SEEPROM;
1792 return (0);
1793 }
NetBSD on the FriendlyARM MINI2440