sys/dev/pci/amdpm_smbusreg.h

   1 /*      $NetBSD: amdpm_smbusreg.h,v 1.1 2006/02/19 02:24:20 tls Exp $ */
   2
   3 /*
   4  * Copyright (c) 2005 Anil Gopinath (anil_public@yahoo.com)
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The name of the author may not be used to endorse or promote products
  16  *    derived from this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  23  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  24  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  25  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  26  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  */
  30
  31 /* driver for SMBUS 1.0 host controller found in the
  32  * AMD-8111 HyperTransport I/O Hub
  33  */
  34
  35 #ifndef _DEV_PCI_AMDPMSMBUSREG_H_
  36 #define _DEV_PCI_AMDPMSMBUSREG_H_
  37
  38 #define AMDPM_8111_SMBUS_STAT        0xE0  /* SMBus 1.x global status register */
  39 #define AMDPM_8111_SMBUS_CTRL        0xE2  /* SMBus 1.x global control register */
  40 #define AMDPM_8111_SMBUS_HOSTADDR    0xE4  /* SMBus 1.x Host address register */
  41 #define AMDPM_8111_SMBUS_HOSTDATA    0xE6  /* SMBus 1.x Host data register */
  42 #define AMDPM_8111_SMBUS_HOSTCMD     0xE8  /* SMBus 1.x Host command field register */
  43
  44 #define AMDPM_8111_SMBUS_GSR_QUICK   0x0008 /* GSR contents for quick op */
  45 #define AMDPM_8111_SMBUS_GSR_SB      0x0009 /* GSR contents to send a byte */
  46 #define AMDPM_8111_SMBUS_GSR_RXB     0x0009 /* GSR contents to receive a byte */
  47 #define AMDPM_8111_SMBUS_GSR_RB      0x000A /* GSR contents to read a byte */
  48 #define AMDPM_8111_SMBUS_GSR_WB      0x000A /* GSR contents to write a byte */
  49
  50 #define AMDPM_8111_GSR_CYCLE_DONE    0x0010 /* indicates cycle done successfuly */
  51
  52 #define AMDPM_8111_SMBUS_READ        0x0001 /* smbus read cycle indicator */
  53 #define AMDPM_8111_SMBUS_RX          0x0001 /* smbus receive cycle indicator */
  54 #define AMDPM_8111_SMBUS_WRITE       0x0000 /* smbus write cycle indicator */
  55 #define AMDPM_8111_SMBUS_SEND        0x0000 /* smbus send cycle indicator */
  56
  57 void      amdpm_smbus_attach(struct amdpm_softc *sc);
  58
  59 #endif