1 /* $NetBSD: auixpreg.h,v 1.2.4.1 2005/01/17 19:31:23 skrll Exp $ */
4 * Copyright (c) 2004, 2005 Reinoud Zandijk <reinoud@netbsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the NetBSD
17 * Foundation, Inc. and its contributors.
18 * 4. Neither the name of The NetBSD Foundation nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * NetBSD audio driver for ATI IXP-{150,200,...} audio driver hardware.
38 * Thanks are due to Takashi Iwai for the constants.
42 #define ATI_IXP_CODECS 3
45 typedef struct atiixp_dma_desc
{
46 uint32_t addr
; /* DMA buffer address */
47 uint16_t status
; /* status bits; function unknown */
48 uint16_t size
; /* size of this DMA packet in dwords */
49 uint32_t next
; /* phys pointer to next packet descriptor */
50 } __packed atiixp_dma_desc_t
;
53 #define ATI_REG_ISR 0x00 /* interrupt source */
54 #define ATI_REG_ISR_IN_XRUN (1U<<0)
55 #define ATI_REG_ISR_IN_STATUS (1U<<1)
56 #define ATI_REG_ISR_OUT_XRUN (1U<<2)
57 #define ATI_REG_ISR_OUT_STATUS (1U<<3)
58 #define ATI_REG_ISR_SPDF_XRUN (1U<<4)
59 #define ATI_REG_ISR_SPDF_STATUS (1U<<5)
60 #define ATI_REG_ISR_PHYS_INTR (1U<<8)
61 #define ATI_REG_ISR_PHYS_MISMATCH (1U<<9)
62 #define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10)
63 #define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11)
64 #define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12)
65 #define ATI_REG_ISR_NEW_FRAME (1U<<13)
67 #define ATI_REG_IER 0x04 /* interrupt enable */
68 #define ATI_REG_IER_IN_XRUN_EN (1U<<0)
69 #define ATI_REG_IER_IO_STATUS_EN (1U<<1)
70 #define ATI_REG_IER_OUT_XRUN_EN (1U<<2)
71 #define ATI_REG_IER_OUT_XRUN_COND (1U<<3)
72 #define ATI_REG_IER_SPDF_XRUN_EN (1U<<4)
73 #define ATI_REG_IER_SPDF_STATUS_EN (1U<<5)
74 #define ATI_REG_IER_PHYS_INTR_EN (1U<<8)
75 #define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9)
76 #define ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
77 #define ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
78 #define ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
79 #define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO) */
80 #define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */
82 #define ATI_REG_CMD 0x08 /* command */
83 #define ATI_REG_CMD_POWERDOWN (1U<<0)
84 #define ATI_REG_CMD_RECEIVE_EN (1U<<1)
85 #define ATI_REG_CMD_SEND_EN (1U<<2)
86 #define ATI_REG_CMD_STATUS_MEM (1U<<3)
87 #define ATI_REG_CMD_SPDF_OUT_EN (1U<<4)
88 #define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5)
89 #define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6)
90 #define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6
91 #define ATI_REG_CMD_IN_DMA_EN (1U<<8)
92 #define ATI_REG_CMD_OUT_DMA_EN (1U<<9)
93 #define ATI_REG_CMD_SPDF_DMA_EN (1U<<10)
94 #define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11)
95 #define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12)
96 #define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12)
97 #define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12)
98 #define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12)
99 #define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12)
100 #define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16)
101 #define ATI_REG_CMD_AUDIO_PRESENT (1U<<20)
102 #define ATI_REG_CMD_INTERLEAVE_IN (1U<<21)
103 #define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22)
104 #define ATI_REG_CMD_LOOPBACK_EN (1U<<23)
105 #define ATI_REG_CMD_PACKED_DIS (1U<<24)
106 #define ATI_REG_CMD_BURST_EN (1U<<25)
107 #define ATI_REG_CMD_PANIC_EN (1U<<26)
108 #define ATI_REG_CMD_MODEM_PRESENT (1U<<27)
109 #define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28)
110 #define ATI_REG_CMD_AC_SOFT_RESET (1U<<29)
111 #define ATI_REG_CMD_AC_SYNC (1U<<30)
112 #define ATI_REG_CMD_AC_RESET (1U<<31)
114 #define ATI_REG_PHYS_OUT_ADDR 0x0c
115 #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
116 #define ATI_REG_PHYS_OUT_RW (1U<<2)
117 #define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8)
118 #define ATI_REG_PHYS_OUT_ADDR_SHIFT 9
119 #define ATI_REG_PHYS_OUT_DATA_SHIFT 16
121 #define ATI_REG_PHYS_IN_ADDR 0x10
122 #define ATI_REG_PHYS_IN_READ_FLAG (1U<<8)
123 #define ATI_REG_PHYS_IN_ADDR_SHIFT 9
124 #define ATI_REG_PHYS_IN_DATA_SHIFT 16
126 #define ATI_REG_SLOTREQ 0x14
128 #define ATI_REG_COUNTER 0x18
129 #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
130 #define ATI_REG_COUNTER_BITCLOCK (31U<<8)
132 #define ATI_REG_IN_FIFO_THRESHOLD 0x1c
134 #define ATI_REG_IN_DMA_LINKPTR 0x20
135 #define ATI_REG_IN_DMA_DT_START 0x24 /* RO */
136 #define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */
137 #define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */
138 #define ATI_REG_IN_DMA_DT_SIZE 0x30
140 #define ATI_REG_OUT_DMA_SLOT 0x34
141 #define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3))
142 #define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff
143 #define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800
144 #define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11
146 #define ATI_REG_OUT_DMA_LINKPTR 0x38
147 #define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */
148 #define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */
149 #define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */
150 #define ATI_REG_OUT_DMA_DT_SIZE 0x48
152 #define ATI_REG_SPDF_CMD 0x4c
153 #define ATI_REG_SPDF_CMD_LFSR (1U<<4)
154 #define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5)
155 #define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */
157 #define ATI_REG_SPDF_DMA_LINKPTR 0x50
158 #define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */
159 #define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */
160 #define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */
161 #define ATI_REG_SPDF_DMA_DT_SIZE 0x60
163 #define ATI_REG_MODEM_MIRROR 0x7c
164 #define ATI_REG_AUDIO_MIRROR 0x80
166 #define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */
167 #define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
169 #define ATI_REG_FIFO_FLUSH 0x88
170 #define ATI_REG_FIFO_OUT_FLUSH (1U<<0)
171 #define ATI_REG_FIFO_IN_FLUSH (1U<<1)
174 #define ATI_REG_LINKPTR_EN (1U<<0)
176 /* [INT|OUT|SPDIF]_DMA_DT_SIZE */
177 #define ATI_REG_DMA_DT_SIZE (0xffffU<<0)
178 #define ATI_REG_DMA_FIFO_USED (0x1fU<<16)
179 #define ATI_REG_DMA_FIFO_FREE (0x1fU<<21)
180 #define ATI_REG_DMA_STATE (7U<<26)