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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / pci / cs4281.c
blob2d2db21405c38b4cf9d952c96c84d8982f280562
1 /* $NetBSD: cs4281.c,v 1.42 2009/05/12 08:23:00 cegger Exp $ */
2
3 /*
4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Tatoku Ogaito
17 * for the NetBSD Project.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Cirrus Logic CS4281 driver.
35 * Data sheets can be found
36 * http://www.cirrus.com/ftp/pub/4281.pdf
37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf
38 *
39 * TODO:
40 * 1: midi and FM support
41 * 2: ...
42 *
43 */
44
45 #include <sys/cdefs.h>
46 __KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.42 2009/05/12 08:23:00 cegger Exp $");
47
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
51 #include <sys/malloc.h>
52 #include <sys/fcntl.h>
53 #include <sys/device.h>
54 #include <sys/systm.h>
55
56 #include <dev/pci/pcidevs.h>
57 #include <dev/pci/pcivar.h>
58 #include <dev/pci/cs4281reg.h>
59 #include <dev/pci/cs428xreg.h>
60
61 #include <sys/audioio.h>
62 #include <dev/audio_if.h>
63 #include <dev/midi_if.h>
64 #include <dev/mulaw.h>
65 #include <dev/auconv.h>
66
67 #include <dev/ic/ac97reg.h>
68 #include <dev/ic/ac97var.h>
69
70 #include <dev/pci/cs428x.h>
71
72 #include <sys/bus.h>
73
74 #if defined(ENABLE_SECONDARY_CODEC)
75 #define MAX_CHANNELS (4)
76 #define MAX_FIFO_SIZE 32 /* 128/4channels */
77 #else
78 #define MAX_CHANNELS (2)
79 #define MAX_FIFO_SIZE 64 /* 128/2channels */
80 #endif
81
82 /* IF functions for audio driver */
83 static int cs4281_match(device_t, cfdata_t, void *);
84 static void cs4281_attach(device_t, device_t, void *);
85 static int cs4281_intr(void *);
86 static int cs4281_query_encoding(void *, struct audio_encoding *);
87 static int cs4281_set_params(void *, int, int, audio_params_t *,
88 audio_params_t *, stream_filter_list_t *,
89 stream_filter_list_t *);
90 static int cs4281_halt_output(void *);
91 static int cs4281_halt_input(void *);
92 static int cs4281_getdev(void *, struct audio_device *);
93 static int cs4281_trigger_output(void *, void *, void *, int,
94 void (*)(void *), void *,
95 const audio_params_t *);
96 static int cs4281_trigger_input(void *, void *, void *, int,
97 void (*)(void *), void *,
98 const audio_params_t *);
99
100 static int cs4281_reset_codec(void *);
101
102 /* Internal functions */
103 static uint8_t cs4281_sr2regval(int);
104 static void cs4281_set_dac_rate(struct cs428x_softc *, int);
105 static void cs4281_set_adc_rate(struct cs428x_softc *, int);
106 static int cs4281_init(struct cs428x_softc *, int);
107
108 /* Power Management */
109 static bool cs4281_suspend(device_t, pmf_qual_t);
110 static bool cs4281_resume(device_t, pmf_qual_t);
111
112 static const struct audio_hw_if cs4281_hw_if = {
113 NULL, /* open */
114 NULL, /* close */
115 NULL,
116 cs4281_query_encoding,
117 cs4281_set_params,
118 cs428x_round_blocksize,
119 NULL,
120 NULL,
121 NULL,
122 NULL,
123 NULL,
124 cs4281_halt_output,
125 cs4281_halt_input,
126 NULL,
127 cs4281_getdev,
128 NULL,
129 cs428x_mixer_set_port,
130 cs428x_mixer_get_port,
131 cs428x_query_devinfo,
132 cs428x_malloc,
133 cs428x_free,
134 cs428x_round_buffersize,
135 cs428x_mappage,
136 cs428x_get_props,
137 cs4281_trigger_output,
138 cs4281_trigger_input,
139 NULL,
140 NULL,
141 };
142
143 #if NMIDI > 0 && 0
144 /* Midi Interface */
145 static void cs4281_midi_close(void*);
146 static void cs4281_midi_getinfo(void *, struct midi_info *);
147 static int cs4281_midi_open(void *, int, void (*)(void *, int),
148 void (*)(void *), void *);
149 static int cs4281_midi_output(void *, int);
150
151 static const struct midi_hw_if cs4281_midi_hw_if = {
152 cs4281_midi_open,
153 cs4281_midi_close,
154 cs4281_midi_output,
155 cs4281_midi_getinfo,
156 0,
157 };
158 #endif
159
160 CFATTACH_DECL(clct, sizeof(struct cs428x_softc),
161 cs4281_match, cs4281_attach, NULL, NULL);
162
163 static struct audio_device cs4281_device = {
164 "CS4281",
165 "",
166 "cs4281"
167 };
168
169
170 static int
171 cs4281_match(device_t parent, cfdata_t match, void *aux)
172 {
173 struct pci_attach_args *pa;
174
175 pa = (struct pci_attach_args *)aux;
176 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS)
177 return 0;
178 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281)
179 return 1;
180 return 0;
181 }
182
183 static void
184 cs4281_attach(device_t parent, device_t self, void *aux)
185 {
186 struct cs428x_softc *sc;
187 struct pci_attach_args *pa;
188 pci_chipset_tag_t pc;
189 char const *intrstr;
190 pcireg_t reg;
191 char devinfo[256];
192 int error;
193
194 sc = device_private(self);
195 pa = (struct pci_attach_args *)aux;
196 pc = pa->pa_pc;
197 aprint_naive(": Audio controller\n");
198
199 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
200 aprint_normal(": %s (rev. 0x%02x)\n", devinfo,
201 PCI_REVISION(pa->pa_class));
202
203 sc->sc_pc = pa->pa_pc;
204 sc->sc_pt = pa->pa_tag;
205
206 /* Map I/O register */
207 if (pci_mapreg_map(pa, PCI_BA0,
208 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
209 &sc->ba0t, &sc->ba0h, NULL, NULL)) {
210 aprint_error_dev(&sc->sc_dev, "can't map BA0 space\n");
211 return;
212 }
213 if (pci_mapreg_map(pa, PCI_BA1,
214 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
215 &sc->ba1t, &sc->ba1h, NULL, NULL)) {
216 aprint_error_dev(&sc->sc_dev, "can't map BA1 space\n");
217 return;
218 }
219
220 sc->sc_dmatag = pa->pa_dmat;
221
222 /* power up chip */
223 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
224 pci_activate_null)) && error != EOPNOTSUPP) {
225 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", error);
226 return;
227 }
228
229 /* Enable the device (set bus master flag) */
230 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
231 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
232 reg | PCI_COMMAND_MASTER_ENABLE);
233
234 #if 0
235 /* LATENCY_TIMER setting */
236 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
237 if (PCI_LATTIMER(temp1) < 32) {
238 temp1 &= 0xffff00ff;
239 temp1 |= 0x00002000;
240 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1);
241 }
242 #endif
243
244 /* Map and establish the interrupt. */
245 if (pci_intr_map(pa, &sc->intrh)) {
246 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n");
247 return;
248 }
249 intrstr = pci_intr_string(pc, sc->intrh);
250
251 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO,
252 cs4281_intr, sc);
253 if (sc->sc_ih == NULL) {
254 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt");
255 if (intrstr != NULL)
256 aprint_error(" at %s", intrstr);
257 aprint_error("\n");
258 return;
259 }
260 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr);
261
262 /*
263 * Sound System start-up
264 */
265 if (cs4281_init(sc, 1) != 0)
266 return;
267
268 sc->type = TYPE_CS4281;
269 sc->halt_input = cs4281_halt_input;
270 sc->halt_output = cs4281_halt_output;
271
272 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS;
273 sc->dma_align = 0x10;
274 sc->hw_blocksize = sc->dma_size / 2;
275
276 /* AC 97 attachment */
277 sc->host_if.arg = sc;
278 sc->host_if.attach = cs428x_attach_codec;
279 sc->host_if.read = cs428x_read_codec;
280 sc->host_if.write = cs428x_write_codec;
281 sc->host_if.reset = cs4281_reset_codec;
282 if (ac97_attach(&sc->host_if, self) != 0) {
283 aprint_error_dev(&sc->sc_dev, "ac97_attach failed\n");
284 return;
285 }
286 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev);
287
288 #if NMIDI > 0 && 0
289 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev);
290 #endif
291
292 if (!pmf_device_register(self, cs4281_suspend, cs4281_resume))
293 aprint_error_dev(self, "couldn't establish power handler\n");
294 }
295
296 static int
297 cs4281_intr(void *p)
298 {
299 struct cs428x_softc *sc;
300 uint32_t intr, hdsr0, hdsr1;
301 char *empty_dma;
302 int handled;
303
304 sc = p;
305 handled = 0;
306 hdsr0 = 0;
307 hdsr1 = 0;
308
309 /* grab interrupt register */
310 intr = BA0READ4(sc, CS4281_HISR);
311
312 DPRINTF(("cs4281_intr:"));
313 /* not for me */
314 if ((intr & HISR_INTENA) == 0) {
315 /* clear the interrupt register */
316 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV);
317 return 0;
318 }
319
320 if (intr & HISR_DMA0)
321 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */
322 if (intr & HISR_DMA1)
323 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */
324 /* clear the interrupt register */
325 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV);
326
327 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n",
328 intr, hdsr0, hdsr1));
329
330 /* Playback Interrupt */
331 if (intr & HISR_DMA0) {
332 handled = 1;
333 if (sc->sc_prun) {
334 DPRINTF((" PB DMA 0x%x(%d)",
335 (int)BA0READ4(sc, CS4281_DCA0),
336 (int)BA0READ4(sc, CS4281_DCC0)));
337 if ((sc->sc_pi%sc->sc_pcount) == 0)
338 sc->sc_pintr(sc->sc_parg);
339 /* copy buffer */
340 ++sc->sc_pi;
341 empty_dma = sc->sc_pdma->addr;
342 if (sc->sc_pi&1)
343 empty_dma += sc->hw_blocksize;
344 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize);
345 sc->sc_pn += sc->hw_blocksize;
346 if (sc->sc_pn >= sc->sc_pe)
347 sc->sc_pn = sc->sc_ps;
348 } else {
349 aprint_error_dev(&sc->sc_dev, "unexpected play intr\n");
350 }
351 }
352 if (intr & HISR_DMA1) {
353 handled = 1;
354 if (sc->sc_rrun) {
355 /* copy from DMA */
356 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1),
357 (int)BA0READ4(sc, CS4281_DCC1)));
358 ++sc->sc_ri;
359 empty_dma = sc->sc_rdma->addr;
360 if ((sc->sc_ri & 1) == 0)
361 empty_dma += sc->hw_blocksize;
362 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize);
363 sc->sc_rn += sc->hw_blocksize;
364 if (sc->sc_rn >= sc->sc_re)
365 sc->sc_rn = sc->sc_rs;
366 if ((sc->sc_ri % sc->sc_rcount) == 0)
367 sc->sc_rintr(sc->sc_rarg);
368 } else {
369 aprint_error_dev(&sc->sc_dev,
370 "unexpected record intr\n");
371 }
372 }
373 DPRINTF(("\n"));
374
375 return handled;
376 }
377
378 static int
379 cs4281_query_encoding(void *addr, struct audio_encoding *fp)
380 {
381
382 switch (fp->index) {
383 case 0:
384 strcpy(fp->name, AudioEulinear);
385 fp->encoding = AUDIO_ENCODING_ULINEAR;
386 fp->precision = 8;
387 fp->flags = 0;
388 break;
389 case 1:
390 strcpy(fp->name, AudioEmulaw);
391 fp->encoding = AUDIO_ENCODING_ULAW;
392 fp->precision = 8;
393 fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
394 break;
395 case 2:
396 strcpy(fp->name, AudioEalaw);
397 fp->encoding = AUDIO_ENCODING_ALAW;
398 fp->precision = 8;
399 fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
400 break;
401 case 3:
402 strcpy(fp->name, AudioEslinear);
403 fp->encoding = AUDIO_ENCODING_SLINEAR;
404 fp->precision = 8;
405 fp->flags = 0;
406 break;
407 case 4:
408 strcpy(fp->name, AudioEslinear_le);
409 fp->encoding = AUDIO_ENCODING_SLINEAR_LE;
410 fp->precision = 16;
411 fp->flags = 0;
412 break;
413 case 5:
414 strcpy(fp->name, AudioEulinear_le);
415 fp->encoding = AUDIO_ENCODING_ULINEAR_LE;
416 fp->precision = 16;
417 fp->flags = 0;
418 break;
419 case 6:
420 strcpy(fp->name, AudioEslinear_be);
421 fp->encoding = AUDIO_ENCODING_SLINEAR_BE;
422 fp->precision = 16;
423 fp->flags = 0;
424 break;
425 case 7:
426 strcpy(fp->name, AudioEulinear_be);
427 fp->encoding = AUDIO_ENCODING_ULINEAR_BE;
428 fp->precision = 16;
429 fp->flags = 0;
430 break;
431 default:
432 return EINVAL;
433 }
434 return 0;
435 }
436
437 static int
438 cs4281_set_params(void *addr, int setmode, int usemode,
439 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil,
440 stream_filter_list_t *rfil)
441 {
442 audio_params_t hw;
443 struct cs428x_softc *sc;
444 audio_params_t *p;
445 stream_filter_list_t *fil;
446 int mode;
447
448 sc = addr;
449 for (mode = AUMODE_RECORD; mode != -1;
450 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) {
451 if ((setmode & mode) == 0)
452 continue;
453
454 p = mode == AUMODE_PLAY ? play : rec;
455
456 if (p == play) {
457 DPRINTFN(5,
458 ("play: sample=%u precision=%u channels=%u\n",
459 p->sample_rate, p->precision, p->channels));
460 if (p->sample_rate < 6023 || p->sample_rate > 48000 ||
461 (p->precision != 8 && p->precision != 16) ||
462 (p->channels != 1 && p->channels != 2)) {
463 return EINVAL;
464 }
465 } else {
466 DPRINTFN(5,
467 ("rec: sample=%u precision=%u channels=%u\n",
468 p->sample_rate, p->precision, p->channels));
469 if (p->sample_rate < 6023 || p->sample_rate > 48000 ||
470 (p->precision != 8 && p->precision != 16) ||
471 (p->channels != 1 && p->channels != 2)) {
472 return EINVAL;
473 }
474 }
475 hw = *p;
476 fil = mode == AUMODE_PLAY ? pfil : rfil;
477
478 switch (p->encoding) {
479 case AUDIO_ENCODING_SLINEAR_BE:
480 break;
481 case AUDIO_ENCODING_SLINEAR_LE:
482 break;
483 case AUDIO_ENCODING_ULINEAR_BE:
484 break;
485 case AUDIO_ENCODING_ULINEAR_LE:
486 break;
487 case AUDIO_ENCODING_ULAW:
488 hw.encoding = AUDIO_ENCODING_SLINEAR_LE;
489 fil->append(fil, mode == AUMODE_PLAY ? mulaw_to_linear8
490 : linear8_to_mulaw, &hw);
491 break;
492 case AUDIO_ENCODING_ALAW:
493 hw.encoding = AUDIO_ENCODING_SLINEAR_LE;
494 fil->append(fil, mode == AUMODE_PLAY ? alaw_to_linear8
495 : linear8_to_alaw, &hw);
496 break;
497 default:
498 return EINVAL;
499 }
500 }
501
502 /* set sample rate */
503 cs4281_set_dac_rate(sc, play->sample_rate);
504 cs4281_set_adc_rate(sc, rec->sample_rate);
505 return 0;
506 }
507
508 static int
509 cs4281_halt_output(void *addr)
510 {
511 struct cs428x_softc *sc;
512
513 sc = addr;
514 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK);
515 sc->sc_prun = 0;
516 return 0;
517 }
518
519 static int
520 cs4281_halt_input(void *addr)
521 {
522 struct cs428x_softc *sc;
523
524 sc = addr;
525 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK);
526 sc->sc_rrun = 0;
527 return 0;
528 }
529
530 static int
531 cs4281_getdev(void *addr, struct audio_device *retp)
532 {
533
534 *retp = cs4281_device;
535 return 0;
536 }
537
538 static int
539 cs4281_trigger_output(void *addr, void *start, void *end, int blksize,
540 void (*intr)(void *), void *arg,
541 const audio_params_t *param)
542 {
543 struct cs428x_softc *sc;
544 uint32_t fmt;
545 struct cs428x_dma *p;
546 int dma_count;
547
548 sc = addr;
549 fmt = 0;
550 #ifdef DIAGNOSTIC
551 if (sc->sc_prun)
552 printf("cs4281_trigger_output: already running\n");
553 #endif
554 sc->sc_prun = 1;
555
556 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p "
557 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg));
558 sc->sc_pintr = intr;
559 sc->sc_parg = arg;
560
561 /* stop playback DMA */
562 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK);
563
564 DPRINTF(("param: precision=%d channels=%d encoding=%d\n",
565 param->precision, param->channels, param->encoding));
566 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next)
567 continue;
568 if (p == NULL) {
569 printf("cs4281_trigger_output: bad addr %p\n", start);
570 return EINVAL;
571 }
572
573 sc->sc_pcount = blksize / sc->hw_blocksize;
574 sc->sc_ps = (char *)start;
575 sc->sc_pe = (char *)end;
576 sc->sc_pdma = p;
577 sc->sc_pbuf = KERNADDR(p);
578 sc->sc_pi = 0;
579 sc->sc_pn = sc->sc_ps;
580 if (blksize >= sc->dma_size) {
581 sc->sc_pn = sc->sc_ps + sc->dma_size;
582 memcpy(sc->sc_pbuf, start, sc->dma_size);
583 ++sc->sc_pi;
584 } else {
585 sc->sc_pn = sc->sc_ps + sc->hw_blocksize;
586 memcpy(sc->sc_pbuf, start, sc->hw_blocksize);
587 }
588
589 dma_count = sc->dma_size;
590 if (param->precision != 8)
591 dma_count /= 2; /* 16 bit */
592 if (param->channels > 1)
593 dma_count /= 2; /* Stereo */
594
595 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n",
596 (int)DMAADDR(p), dma_count));
597 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p));
598 BA0WRITE4(sc, CS4281_DBC0, dma_count-1);
599
600 /* set playback format */
601 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK;
602 if (param->precision == 8)
603 fmt |= DMRn_SIZE8;
604 if (param->channels == 1)
605 fmt |= DMRn_MONO;
606 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE ||
607 param->encoding == AUDIO_ENCODING_SLINEAR_BE)
608 fmt |= DMRn_BEND;
609 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE ||
610 param->encoding == AUDIO_ENCODING_ULINEAR_LE)
611 fmt |= DMRn_USIGN;
612 BA0WRITE4(sc, CS4281_DMR0, fmt);
613
614 /* set sample rate */
615 sc->sc_prate = param->sample_rate;
616 cs4281_set_dac_rate(sc, param->sample_rate);
617
618 /* start DMA */
619 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK);
620 /* Enable interrupts */
621 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM);
622
623 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR)));
624 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR)));
625 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0)));
626 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0)));
627 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0)));
628 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n",
629 BA0READ4(sc, CS4281_DACSR)));
630 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA)));
631 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n",
632 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN));
633
634 return 0;
635 }
636
637 static int
638 cs4281_trigger_input(void *addr, void *start, void *end, int blksize,
639 void (*intr)(void *), void *arg,
640 const audio_params_t *param)
641 {
642 struct cs428x_softc *sc;
643 struct cs428x_dma *p;
644 uint32_t fmt;
645 int dma_count;
646
647 sc = addr;
648 fmt = 0;
649 #ifdef DIAGNOSTIC
650 if (sc->sc_rrun)
651 printf("cs4281_trigger_input: already running\n");
652 #endif
653 sc->sc_rrun = 1;
654 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p "
655 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg));
656 sc->sc_rintr = intr;
657 sc->sc_rarg = arg;
658
659 /* stop recording DMA */
660 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK);
661
662 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next)
663 continue;
664 if (!p) {
665 printf("cs4281_trigger_input: bad addr %p\n", start);
666 return EINVAL;
667 }
668
669 sc->sc_rcount = blksize / sc->hw_blocksize;
670 sc->sc_rs = (char *)start;
671 sc->sc_re = (char *)end;
672 sc->sc_rdma = p;
673 sc->sc_rbuf = KERNADDR(p);
674 sc->sc_ri = 0;
675 sc->sc_rn = sc->sc_rs;
676
677 dma_count = sc->dma_size;
678 if (param->precision != 8)
679 dma_count /= 2;
680 if (param->channels > 1)
681 dma_count /= 2;
682
683 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n",
684 (int)DMAADDR(p), dma_count));
685 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p));
686 BA0WRITE4(sc, CS4281_DBC1, dma_count-1);
687
688 /* set recording format */
689 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK;
690 if (param->precision == 8)
691 fmt |= DMRn_SIZE8;
692 if (param->channels == 1)
693 fmt |= DMRn_MONO;
694 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE ||
695 param->encoding == AUDIO_ENCODING_SLINEAR_BE)
696 fmt |= DMRn_BEND;
697 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE ||
698 param->encoding == AUDIO_ENCODING_ULINEAR_LE)
699 fmt |= DMRn_USIGN;
700 BA0WRITE4(sc, CS4281_DMR1, fmt);
701
702 /* set sample rate */
703 sc->sc_rrate = param->sample_rate;
704 cs4281_set_adc_rate(sc, param->sample_rate);
705
706 /* Start DMA */
707 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK);
708 /* Enable interrupts */
709 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM);
710
711 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR)));
712 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR)));
713 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1)));
714 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1)));
715
716 return 0;
717 }
718
719 static bool
720 cs4281_suspend(device_t dv, pmf_qual_t qual)
721 {
722 struct cs428x_softc *sc = device_private(dv);
723
724 /* save current playback status */
725 if (sc->sc_prun) {
726 sc->sc_suspend_state.cs4281.dcr0 = BA0READ4(sc, CS4281_DCR0);
727 sc->sc_suspend_state.cs4281.dmr0 = BA0READ4(sc, CS4281_DMR0);
728 sc->sc_suspend_state.cs4281.dbc0 = BA0READ4(sc, CS4281_DBC0);
729 sc->sc_suspend_state.cs4281.dba0 = BA0READ4(sc, CS4281_DBA0);
730 }
731
732 /* save current capture status */
733 if (sc->sc_rrun) {
734 sc->sc_suspend_state.cs4281.dcr1 = BA0READ4(sc, CS4281_DCR1);
735 sc->sc_suspend_state.cs4281.dmr1 = BA0READ4(sc, CS4281_DMR1);
736 sc->sc_suspend_state.cs4281.dbc1 = BA0READ4(sc, CS4281_DBC1);
737 sc->sc_suspend_state.cs4281.dba1 = BA0READ4(sc, CS4281_DBA1);
738 }
739 /* Stop DMA */
740 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK);
741 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK);
742
743 return true;
744 }
745
746 static bool
747 cs4281_resume(device_t dv, pmf_qual_t qual)
748 {
749 struct cs428x_softc *sc = device_private(dv);
750
751 cs4281_init(sc, 0);
752 cs4281_reset_codec(sc);
753
754 /* restore ac97 registers */
755 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if);
756
757 /* restore DMA related status */
758 if (sc->sc_prun) {
759 cs4281_set_dac_rate(sc, sc->sc_prate);
760 BA0WRITE4(sc, CS4281_DBA0, sc->sc_suspend_state.cs4281.dba0);
761 BA0WRITE4(sc, CS4281_DBC0, sc->sc_suspend_state.cs4281.dbc0);
762 BA0WRITE4(sc, CS4281_DMR0, sc->sc_suspend_state.cs4281.dmr0);
763 BA0WRITE4(sc, CS4281_DCR0, sc->sc_suspend_state.cs4281.dcr0);
764 }
765 if (sc->sc_rrun) {
766 cs4281_set_adc_rate(sc, sc->sc_rrate);
767 BA0WRITE4(sc, CS4281_DBA1, sc->sc_suspend_state.cs4281.dba1);
768 BA0WRITE4(sc, CS4281_DBC1, sc->sc_suspend_state.cs4281.dbc1);
769 BA0WRITE4(sc, CS4281_DMR1, sc->sc_suspend_state.cs4281.dmr1);
770 BA0WRITE4(sc, CS4281_DCR1, sc->sc_suspend_state.cs4281.dcr1);
771 }
772 /* enable intterupts */
773 if (sc->sc_prun || sc->sc_rrun)
774 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM);
775
776 return true;
777 }
778
779 /* control AC97 codec */
780 static int
781 cs4281_reset_codec(void *addr)
782 {
783 struct cs428x_softc *sc;
784 uint16_t data;
785 uint32_t dat32;
786 int n;
787
788 sc = addr;
789
790 DPRINTFN(3, ("cs4281_reset_codec\n"));
791
792 /* Reset codec */
793 BA0WRITE4(sc, CS428X_ACCTL, 0);
794 delay(50); /* delay 50us */
795
796 BA0WRITE4(sc, CS4281_SPMC, 0);
797 delay(100); /* delay 100us */
798 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN);
799 #if defined(ENABLE_SECONDARY_CODEC)
800 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E);
801 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID);
802 #endif
803 delay(50000); /* XXX: delay 50ms */
804
805 /* Enable ASYNC generation */
806 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN);
807
808 /* Wait for codec ready. Linux driver waits 50ms here */
809 n = 0;
810 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) {
811 delay(100);
812 if (++n > 1000) {
813 printf("reset_codec: AC97 codec ready timeout\n");
814 return ETIMEDOUT;
815 }
816 }
817 #if defined(ENABLE_SECONDARY_CODEC)
818 /* secondary codec ready*/
819 n = 0;
820 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) {
821 delay(100);
822 if (++n > 1000)
823 return 0;
824 }
825 #endif
826 /* Set the serial timing configuration */
827 /* XXX: undocumented but the Linux driver do this */
828 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97);
829
830 /* Wait for codec ready signal */
831 n = 0;
832 do {
833 delay(1000);
834 if (++n > 1000) {
835 aprint_error_dev(&sc->sc_dev,
836 "timeout waiting for codec ready\n");
837 return ETIMEDOUT;
838 }
839 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY;
840 } while (dat32 == 0);
841
842 /* Enable Valid Frame output on ASDOUT */
843 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM);
844
845 /* Wait until codec calibration is finished. Codec register 26h */
846 n = 0;
847 do {
848 delay(1);
849 if (++n > 1000) {
850 aprint_error_dev(&sc->sc_dev,
851 "timeout waiting for codec calibration\n");
852 return ETIMEDOUT;
853 }
854 cs428x_read_codec(sc, AC97_REG_POWER, &data);
855 } while ((data & 0x0f) != 0x0f);
856
857 /* Set the serial timing configuration again */
858 /* XXX: undocumented but the Linux driver do this */
859 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97);
860
861 /* Wait until we've sampled input slots 3 & 4 as valid */
862 n = 0;
863 do {
864 delay(1000);
865 if (++n > 1000) {
866 aprint_error_dev(&sc->sc_dev, "timeout waiting for "
867 "sampled input slots as valid\n");
868 return ETIMEDOUT;
869 }
870 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ;
871 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4));
872
873 /* Start digital data transfer of audio data to the codec */
874 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4));
875 return 0;
876 }
877
878
879 /* Internal functions */
880
881 /* convert sample rate to register value */
882 static uint8_t
883 cs4281_sr2regval(int rate)
884 {
885 uint8_t retval;
886
887 /* We don't have to change here. but anyway ... */
888 if (rate > 48000)
889 rate = 48000;
890 if (rate < 6023)
891 rate = 6023;
892
893 switch (rate) {
894 case 8000:
895 retval = 5;
896 break;
897 case 11025:
898 retval = 4;
899 break;
900 case 16000:
901 retval = 3;
902 break;
903 case 22050:
904 retval = 2;
905 break;
906 case 44100:
907 retval = 1;
908 break;
909 case 48000:
910 retval = 0;
911 break;
912 default:
913 retval = 1536000/rate; /* == 24576000/(rate*16) */
914 }
915 return retval;
916 }
917
918 static void
919 cs4281_set_adc_rate(struct cs428x_softc *sc, int rate)
920 {
921
922 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate));
923 }
924
925 static void
926 cs4281_set_dac_rate(struct cs428x_softc *sc, int rate)
927 {
928
929 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate));
930 }
931
932 static int
933 cs4281_init(struct cs428x_softc *sc, int init)
934 {
935 int n;
936 uint16_t data;
937 uint32_t dat32;
938
939 /* set "Configuration Write Protect" register to
940 * 0x4281 to allow to write */
941 BA0WRITE4(sc, CS4281_CWPR, 0x4281);
942
943 /*
944 * Unset "Full Power-Down bit of Extended PCI Power Management
945 * Control" register to release the reset state.
946 */
947 dat32 = BA0READ4(sc, CS4281_EPPMC);
948 if (dat32 & EPPMC_FPDN) {
949 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN);
950 }
951
952 /* Start PLL out in known state */
953 BA0WRITE4(sc, CS4281_CLKCR1, 0);
954 /* Start serial ports out in known state */
955 BA0WRITE4(sc, CS4281_SERMC, 0);
956
957 /* Reset codec */
958 BA0WRITE4(sc, CS428X_ACCTL, 0);
959 delay(50); /* delay 50us */
960
961 BA0WRITE4(sc, CS4281_SPMC, 0);
962 delay(100); /* delay 100us */
963 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN);
964 #if defined(ENABLE_SECONDARY_CODEC)
965 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E);
966 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID);
967 #endif
968 delay(50000); /* XXX: delay 50ms */
969
970 /* Turn on Sound System clocks based on ABITCLK */
971 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP);
972 delay(50000); /* XXX: delay 50ms */
973 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP);
974
975 /* Set enables for sections that are needed in the SSPM registers */
976 BA0WRITE4(sc, CS4281_SSPM,
977 SSPM_MIXEN | /* Mixer */
978 SSPM_CSRCEN | /* Capture SRC */
979 SSPM_PSRCEN | /* Playback SRC */
980 SSPM_JSEN | /* Joystick */
981 SSPM_ACLEN | /* AC LINK */
982 SSPM_FMEN /* FM */
983 );
984
985 /* Wait for clock stabilization */
986 n = 0;
987 #if 1
988 /* what document says */
989 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON))
990 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) {
991 delay(100);
992 if (++n > 1000) {
993 aprint_error_dev(&sc->sc_dev,
994 "timeout waiting for clock stabilization\n");
995 return -1;
996 }
997 }
998 #else
999 /* Cirrus driver for Linux does */
1000 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) {
1001 delay(1000);
1002 if (++n > 1000) {
1003 aprint_error_dev(&sc->sc_dev,
1004 "timeout waiting for clock stabilization\n");
1005 return -1;
1006 }
1007 }
1008 #endif
1009
1010 /* Enable ASYNC generation */
1011 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN);
1012
1013 /* Wait for codec ready. Linux driver waits 50ms here */
1014 n = 0;
1015 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) {
1016 delay(100);
1017 if (++n > 1000) {
1018 aprint_error_dev(&sc->sc_dev,
1019 "timeout waiting for codec ready\n");
1020 return -1;
1021 }
1022 }
1023
1024 #if defined(ENABLE_SECONDARY_CODEC)
1025 /* secondary codec ready*/
1026 n = 0;
1027 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) {
1028 delay(100);
1029 if (++n > 1000) {
1030 aprint_error_dev(&sc->sc_dev,
1031 "timeout waiting for secondary codec ready\n");
1032 return -1;
1033 }
1034 }
1035 #endif
1036
1037 /* Set the serial timing configuration */
1038 /* XXX: undocumented but the Linux driver do this */
1039 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97);
1040
1041 /* Wait for codec ready signal */
1042 n = 0;
1043 do {
1044 delay(1000);
1045 if (++n > 1000) {
1046 aprint_error_dev(&sc->sc_dev,
1047 "timeout waiting for codec ready\n");
1048 return -1;
1049 }
1050 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY;
1051 } while (dat32 == 0);
1052
1053 /* Enable Valid Frame output on ASDOUT */
1054 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM);
1055
1056 /* Wait until codec calibration is finished. codec register 26h */
1057 n = 0;
1058 do {
1059 delay(1);
1060 if (++n > 1000) {
1061 aprint_error_dev(&sc->sc_dev,
1062 "timeout waiting for codec calibration\n");
1063 return -1;
1064 }
1065 cs428x_read_codec(sc, AC97_REG_POWER, &data);
1066 } while ((data & 0x0f) != 0x0f);
1067
1068 /* Set the serial timing configuration again */
1069 /* XXX: undocumented but the Linux driver do this */
1070 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97);
1071
1072 /* Wait until we've sampled input slots 3 & 4 as valid */
1073 n = 0;
1074 do {
1075 delay(1000);
1076 if (++n > 1000) {
1077 aprint_error_dev(&sc->sc_dev, "timeout waiting for "
1078 "sampled input slots as valid\n");
1079 return -1;
1080 }
1081 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4);
1082 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4));
1083
1084 /* Start digital data transfer of audio data to the codec */
1085 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4));
1086
1087 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0);
1088 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0);
1089
1090 /* Power on the DAC */
1091 cs428x_read_codec(sc, AC97_REG_POWER, &data);
1092 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff);
1093
1094 /* Wait until we sample a DAC ready state.
1095 * Not documented, but Linux driver does.
1096 */
1097 for (n = 0; n < 32; ++n) {
1098 delay(1000);
1099 cs428x_read_codec(sc, AC97_REG_POWER, &data);
1100 if (data & 0x02)
1101 break;
1102 }
1103
1104 /* Power on the ADC */
1105 cs428x_read_codec(sc, AC97_REG_POWER, &data);
1106 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff);
1107
1108 /* Wait until we sample ADC ready state.
1109 * Not documented, but Linux driver does.
1110 */
1111 for (n = 0; n < 32; ++n) {
1112 delay(1000);
1113 cs428x_read_codec(sc, AC97_REG_POWER, &data);
1114 if (data & 0x01)
1115 break;
1116 }
1117
1118 #if 0
1119 /* Initialize AC-Link features */
1120 /* variable sample-rate support */
1121 mem = BA0READ4(sc, CS4281_SERMC);
1122 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2);
1123 BA0WRITE4(sc, CS4281_SERMC, mem);
1124 /* XXX: more... */
1125
1126 /* Initialize SSCR register features */
1127 /* XXX: hardware volume setting */
1128 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */
1129 #endif
1130
1131 /* disable Sound Blaster Pro emulation */
1132 /* XXX:
1133 * Cannot set since the documents does not describe which bit is
1134 * correspond to SSCR_SB. Since the reset value of SSCR is 0,
1135 * we can ignore it.*/
1136 #if 0
1137 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB);
1138 #endif
1139
1140 /* map AC97 PCM playback to DMA Channel 0 */
1141 /* Reset FEN bit to setup first */
1142 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN));
1143 /*
1144 *| RS[4:0]/| |
1145 *| LS[4:0] | AC97 | Slot Function
1146 *|---------+--------+--------------------
1147 *| 0 | 3 | Left PCM Playback
1148 *| 1 | 4 | Right PCM Playback
1149 *| 2 | 5 | Phone Line 1 DAC
1150 *| 3 | 6 | Center PCM Playback
1151 *....
1152 * quoted from Table 29(p109)
1153 */
1154 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */
1155 0x00 << 16 | /* LS[4:0] = 0 see above */
1156 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */
1157 0x00 << 0 ; /* OF[6:0] = 0 offset */
1158 BA0WRITE4(sc, CS4281_FCR0, dat32);
1159 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN);
1160
1161 /* map AC97 PCM record to DMA Channel 1 */
1162 /* Reset FEN bit to setup first */
1163 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN));
1164 /*
1165 *| RS[4:0]/|
1166 *| LS[4:0] | AC97 | Slot Function
1167 *|---------+------+-------------------
1168 *| 10 | 3 | Left PCM Record
1169 *| 11 | 4 | Right PCM Record
1170 *| 12 | 5 | Phone Line 1 ADC
1171 *| 13 | 6 | Mic ADC
1172 *....
1173 * quoted from Table 30(p109)
1174 */
1175 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */
1176 0x0a << 16 | /* LS[4:0] = 10 See above */
1177 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */
1178 0x10 << 0 ; /* OF[6:0] = 16 offset */
1179
1180 /* XXX: I cannot understand why FCRn_PSH is needed here. */
1181 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH);
1182 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN);
1183
1184 #if 0
1185 /* Disable DMA Channel 2, 3 */
1186 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN));
1187 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN));
1188 #endif
1189
1190 /* Set the SRC Slot Assignment accordingly */
1191 /*| PLSS[4:0]/
1192 *| PRSS[4:0] | AC97 | Slot Function
1193 *|-----------+------+----------------
1194 *| 0 | 3 | Left PCM Playback
1195 *| 1 | 4 | Right PCM Playback
1196 *| 2 | 5 | phone line 1 DAC
1197 *| 3 | 6 | Center PCM Playback
1198 *| 4 | 7 | Left Surround PCM Playback
1199 *| 5 | 8 | Right Surround PCM Playback
1200 *......
1201 *
1202 *| CLSS[4:0]/
1203 *| CRSS[4:0] | AC97 | Codec |Slot Function
1204 *|-----------+------+-------+-----------------
1205 *| 10 | 3 |Primary| Left PCM Record
1206 *| 11 | 4 |Primary| Right PCM Record
1207 *| 12 | 5 |Primary| Phone Line 1 ADC
1208 *| 13 | 6 |Primary| Mic ADC
1209 *|.....
1210 *| 20 | 3 | Sec. | Left PCM Record
1211 *| 21 | 4 | Sec. | Right PCM Record
1212 *| 22 | 5 | Sec. | Phone Line 1 ADC
1213 *| 23 | 6 | Sec. | Mic ADC
1214 */
1215 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */
1216 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */
1217 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */
1218 0x00 << 0; /* PLSS[4:0] Left PCM Playback */
1219 BA0WRITE4(sc, CS4281_SRCSA, dat32);
1220
1221 /* Set interrupt to occurred at Half and Full terminal
1222 * count interrupt enable for DMA channel 0 and 1.
1223 * To keep DMA stop, set MSK.
1224 */
1225 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK;
1226 BA0WRITE4(sc, CS4281_DCR0, dat32);
1227 BA0WRITE4(sc, CS4281_DCR1, dat32);
1228
1229 /* Set Auto-Initialize Contorl enable */
1230 BA0WRITE4(sc, CS4281_DMR0,
1231 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ);
1232 BA0WRITE4(sc, CS4281_DMR1,
1233 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE);
1234
1235 /* Clear DMA Mask in HIMR */
1236 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM;
1237 BA0WRITE4(sc, CS4281_HIMR,
1238 BA0READ4(sc, CS4281_HIMR) & dat32);
1239
1240 /* set current status */
1241 if (init != 0) {
1242 sc->sc_prun = 0;
1243 sc->sc_rrun = 0;
1244 }
1245
1246 /* setup playback volume */
1247 BA0WRITE4(sc, CS4281_PPRVC, 7);
1248 BA0WRITE4(sc, CS4281_PPLVC, 7);
1249
1250 return 0;
1251 }
NetBSD on the FriendlyARM MINI2440