sys/dev/pci/cxgb_firmware_exports.h

   1 /**************************************************************************
   2
   3 Copyright (c) 2007, Chelsio Inc.
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Neither the name of the Chelsio Corporation nor the names of its
  13     contributors may be used to endorse or promote products derived from
  14     this software without specific prior written permission.
  15
  16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  26 POSSIBILITY OF SUCH DAMAGE.
  27
  28 $FreeBSD: src/sys/dev/cxgb/common/cxgb_firmware_exports.h,v 1.2 2007/05/28 22:57:26 kmacy Exp $
  29
  30 ***************************************************************************/
  31 #ifndef _FIRMWARE_EXPORTS_H_
  32 #define _FIRMWARE_EXPORTS_H_
  33
  34 /* WR OPCODES supported by the firmware.
  35  */
  36 #define FW_WROPCODE_FORWARD         0x01
  37 #define FW_WROPCODE_BYPASS          0x05
  38
  39 #define FW_WROPCODE_TUNNEL_TX_PKT       0x03
  40
  41 #define FW_WROPOCDE_ULPTX_DATA_SGL      0x00
  42 #define FW_WROPCODE_ULPTX_MEM_READ      0x02
  43 #define FW_WROPCODE_ULPTX_PKT           0x04
  44 #define FW_WROPCODE_ULPTX_INVALIDATE        0x06
  45
  46 #define FW_WROPCODE_TUNNEL_RX_PKT       0x07
  47
  48 #define FW_WROPCODE_OFLD_GETTCB_RPL     0x08
  49 #define FW_WROPCODE_OFLD_CLOSE_CON      0x09
  50 #define FW_WROPCODE_OFLD_TP_ABORT_CON_REQ   0x0A
  51 #define FW_WROPCODE_OFLD_HOST_ABORT_CON_RPL 0x0F
  52 #define FW_WROPCODE_OFLD_HOST_ABORT_CON_REQ 0x0B
  53 #define FW_WROPCODE_OFLD_TP_ABORT_CON_RPL   0x0C
  54 #define FW_WROPCODE_OFLD_TX_DATA        0x0D
  55 #define FW_WROPCODE_OFLD_TX_DATA_ACK        0x0E
  56
  57 #define FW_WROPCODE_RI_RDMA_INIT        0x10
  58 #define FW_WROPCODE_RI_RDMA_WRITE       0x11
  59 #define FW_WROPCODE_RI_RDMA_READ_REQ        0x12
  60 #define FW_WROPCODE_RI_RDMA_READ_RESP       0x13
  61 #define FW_WROPCODE_RI_SEND         0x14
  62 #define FW_WROPCODE_RI_TERMINATE        0x15
  63 #define FW_WROPCODE_RI_RDMA_READ        0x16
  64 #define FW_WROPCODE_RI_RECEIVE          0x17
  65 #define FW_WROPCODE_RI_BIND_MW          0x18
  66 #define FW_WROPCODE_RI_FASTREGISTER_MR      0x19
  67 #define FW_WROPCODE_RI_LOCAL_INV        0x1A
  68 #define FW_WROPCODE_RI_MODIFY_QP        0x1B
  69 #define FW_WROPCODE_RI_BYPASS           0x1C
  70
  71 #define FW_WROPOCDE_RSVD            0x1E
  72
  73 #define FW_WROPCODE_SGE_EGRESSCONTEXT_RR    0x1F
  74
  75 #define FW_WROPCODE_MNGT            0x1D
  76 #define FW_MNGTOPCODE_PKTSCHED_SET      0x00
  77
  78 /* Maximum size of a WR sent from the host, limited by the SGE.
  79  *
  80  * Note: WR coming from ULP or TP are only limited by CIM.
  81  */
  82 #define FW_WR_SIZE          128
  83
  84 /* Maximum number of outstanding WRs sent from the host. Value must be
  85  * programmed in the CTRL/TUNNEL/QP SGE Egress Context and used by
  86  * offload modules to limit the number of WRs per connection.
  87  */
  88 #define FW_T3_WR_NUM            16
  89 #define FW_N3_WR_NUM            7
  90
  91 #ifndef N3
  92 # define FW_WR_NUM          FW_T3_WR_NUM
  93 #else
  94 # define FW_WR_NUM          FW_N3_WR_NUM
  95 #endif
  96
  97 /* FW_TUNNEL_NUM corresponds to the number of supported TUNNEL Queues. These
  98  * queues must start at SGE Egress Context FW_TUNNEL_SGEEC_START and must
  99  * start at 'TID' (or 'uP Token') FW_TUNNEL_TID_START.
 100  *
 101  * Ingress Traffic (e.g. DMA completion credit)  for TUNNEL Queue[i] is sent
 102  * to RESP Queue[i].
 103  */
 104 #define FW_TUNNEL_NUM           8
 105 #define FW_TUNNEL_SGEEC_START       8
 106 #define FW_TUNNEL_TID_START     65544
 107
 108
 109 /* FW_CTRL_NUM corresponds to the number of supported CTRL Queues. These queues
 110  * must start at SGE Egress Context FW_CTRL_SGEEC_START and must start at 'TID'
 111  * (or 'uP Token') FW_CTRL_TID_START.
 112  *
 113  * Ingress Traffic for CTRL Queue[i] is sent to RESP Queue[i].
 114  */
 115 #define FW_CTRL_NUM         8
 116 #define FW_CTRL_SGEEC_START     65528
 117 #define FW_CTRL_TID_START       65536
 118
 119 /* FW_OFLD_NUM corresponds to the number of supported OFFLOAD Queues. These
 120  * queues must start at SGE Egress Context FW_OFLD_SGEEC_START.
 121  *
 122  * Note: the 'uP Token' in the SGE Egress Context fields is irrelevant for
 123  * OFFLOAD Queues, as the host is responsible for providing the correct TID in
 124  * every WR.
 125  *
 126  * Ingress Trafffic for OFFLOAD Queue[i] is sent to RESP Queue[i].
 127  */
 128 #define FW_OFLD_NUM         8
 129 #define FW_OFLD_SGEEC_START     0
 130
 131 /*
 132  *
 133  */
 134 #define FW_RI_NUM           1
 135 #define FW_RI_SGEEC_START       65527
 136 #define FW_RI_TID_START         65552
 137
 138 /*
 139  * The RX_PKT_TID
 140  */
 141 #define FW_RX_PKT_NUM           1
 142 #define FW_RX_PKT_TID_START     65553
 143
 144 /* FW_WRC_NUM corresponds to the number of Work Request Context that supported
 145  * by the firmware.
 146  */
 147 #define FW_WRC_NUM          \
 148     (65536 + FW_TUNNEL_NUM + FW_CTRL_NUM + FW_RI_NUM + FW_RX_PKT_NUM)
 149
 150 /*
 151  * FW type and version.
 152  */
 153 #define S_FW_VERSION_TYPE       28
 154 #define M_FW_VERSION_TYPE       0xF
 155 #define V_FW_VERSION_TYPE(x)        ((x) << S_FW_VERSION_TYPE)
 156 #define G_FW_VERSION_TYPE(x)        \
 157     (((x) >> S_FW_VERSION_TYPE) & M_FW_VERSION_TYPE)
 158
 159 #define S_FW_VERSION_MAJOR      16
 160 #define M_FW_VERSION_MAJOR      0xFFF
 161 #define V_FW_VERSION_MAJOR(x)       ((x) << S_FW_VERSION_MAJOR)
 162 #define G_FW_VERSION_MAJOR(x)       \
 163     (((x) >> S_FW_VERSION_MAJOR) & M_FW_VERSION_MAJOR)
 164
 165 #define S_FW_VERSION_MINOR      8
 166 #define M_FW_VERSION_MINOR      0xFF
 167 #define V_FW_VERSION_MINOR(x)       ((x) << S_FW_VERSION_MINOR)
 168 #define G_FW_VERSION_MINOR(x)       \
 169     (((x) >> S_FW_VERSION_MINOR) & M_FW_VERSION_MINOR)
 170
 171 #define S_FW_VERSION_MICRO      0
 172 #define M_FW_VERSION_MICRO      0xFF
 173 #define V_FW_VERSION_MICRO(x)       ((x) << S_FW_VERSION_MICRO)
 174 #define G_FW_VERSION_MICRO(x)       \
 175     (((x) >> S_FW_VERSION_MICRO) & M_FW_VERSION_MICRO)
 176
 177 #endif /* _FIRMWARE_EXPORTS_H_ */