sys/dev/pci/hifn7751reg.h

   1 /*      $NetBSD: hifn7751reg.h,v 1.3.2.4 2005/03/04 16:45:17 skrll Exp $        */
   2 /*      $OpenBSD: hifn7751reg.h,v 1.43 2003/06/02 15:58:41 deraadt Exp $        */
   3
   4 /*
   5  * Invertex AEON / Hifn 7751 driver
   6  * Copyright (c) 1999 Invertex Inc. All rights reserved.
   7  * Copyright (c) 1999 Theo de Raadt
   8  * Copyright (c) 2000-2001 Network Security Technologies, Inc.
   9  *                      http://www.netsec.net
  10  *
  11  * Please send any comments, feedback, bug-fixes, or feature requests to
  12  * software@invertex.com.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions
  16  * are met:
  17  *
  18  * 1. Redistributions of source code must retain the above copyright
  19  *    notice, this list of conditions and the following disclaimer.
  20  * 2. Redistributions in binary form must reproduce the above copyright
  21  *    notice, this list of conditions and the following disclaimer in the
  22  *    documentation and/or other materials provided with the distribution.
  23  * 3. The name of the author may not be used to endorse or promote products
  24  *    derived from this software without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  27  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  28  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  29  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  30  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  31  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  35  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Effort sponsored in part by the Defense Advanced Research Projects
  38  * Agency (DARPA) and Air Force Research Laboratory, Air Force
  39  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
  40  *
  41  */
  42 #ifndef __DEV_PCI_HIFN7751REG_H__
  43 #define __DEV_PCI_HIFN7751REG_H__
  44
  45 #include <machine/endian.h>
  46
  47 /*
  48  * Some PCI configuration space offset defines.  The names were made
  49  * identical to the names used by the Linux kernel.
  50  */
  51 #define HIFN_BAR0               (PCI_MAPREG_START + 0)  /* PUC register map */
  52 #define HIFN_BAR1               (PCI_MAPREG_START + 4)  /* DMA register map */
  53 #define HIFN_RETRY_TIMEOUT      0x41
  54 #define HIFN_TRDY_TIMEOUT       0x40
  55
  56 /*
  57  * The values below should multiple of 4 -- and be large enough to handle
  58  * any command the driver implements.
  59  *
  60  * MAX_COMMAND = base command + mac command + encrypt command +
  61  *                      mac-key + rc4-key
  62  * MAX_RESULT  = base result + comp result + mac result + mac + encrypt result
  63  *
  64  *
  65  */
  66 #define HIFN_MAX_COMMAND        (8 + 8 + 8 + 64 + 260)
  67 #define HIFN_MAX_RESULT         (8 + 4 + 4 + 20 + 4)
  68
  69 /*
  70  * hifn_desc_t
  71  *
  72  * Holds an individual descriptor for any of the rings.
  73  */
  74 struct hifn_desc {
  75         volatile u_int32_t l;           /* length and status bits */
  76         volatile u_int32_t p;
  77 };
  78
  79 /*
  80  * Masks for the "length" field of struct hifn_desc.
  81  */
  82 #define HIFN_D_LENGTH           0x0000ffff      /* length bit mask */
  83 #define HIFN_D_MASKDONEIRQ      0x02000000      /* mask the done interrupt */
  84 #define HIFN_D_DESTOVER         0x04000000      /* destination overflow */
  85 #define HIFN_D_OVER             0x08000000      /* overflow */
  86 #define HIFN_D_LAST             0x20000000      /* last descriptor in chain */
  87 #define HIFN_D_JUMP             0x40000000      /* jump descriptor */
  88 #define HIFN_D_VALID            0x80000000      /* valid bit */
  89
  90 /*
  91  * Processing Unit Registers (offset from BASEREG0)
  92  */
  93 #define HIFN_0_PUDATA           0x00    /* Processing Unit Data */
  94 #define HIFN_0_PUCTRL           0x04    /* Processing Unit Control */
  95 #define HIFN_0_PUISR            0x08    /* Processing Unit Interrupt Status */
  96 #define HIFN_0_PUCNFG           0x0c    /* Processing Unit Configuration */
  97 #define HIFN_0_PUIER            0x10    /* Processing Unit Interrupt Enable */
  98 #define HIFN_0_PUSTAT           0x14    /* Processing Unit Status/Chip ID */
  99 #define HIFN_0_FIFOSTAT         0x18    /* FIFO Status */
 100 #define HIFN_0_FIFOCNFG         0x1c    /* FIFO Configuration */
 101 #define HIFN_0_SPACESIZE        0x20    /* Register space size */
 102
 103 /* Processing Unit Control Register (HIFN_0_PUCTRL) */
 104 #define HIFN_PUCTRL_CLRSRCFIFO  0x0010  /* clear source fifo */
 105 #define HIFN_PUCTRL_STOP        0x0008  /* stop pu */
 106 #define HIFN_PUCTRL_LOCKRAM     0x0004  /* lock ram */
 107 #define HIFN_PUCTRL_DMAENA      0x0002  /* enable dma */
 108 #define HIFN_PUCTRL_RESET       0x0001  /* Reset processing unit */
 109
 110 /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
 111 #define HIFN_PUISR_CMDINVAL     0x8000  /* Invalid command interrupt */
 112 #define HIFN_PUISR_DATAERR      0x4000  /* Data error interrupt */
 113 #define HIFN_PUISR_SRCFIFO      0x2000  /* Source FIFO ready interrupt */
 114 #define HIFN_PUISR_DSTFIFO      0x1000  /* Destination FIFO ready interrupt */
 115 #define HIFN_PUISR_DSTOVER      0x0200  /* Destination overrun interrupt */
 116 #define HIFN_PUISR_SRCCMD       0x0080  /* Source command interrupt */
 117 #define HIFN_PUISR_SRCCTX       0x0040  /* Source context interrupt */
 118 #define HIFN_PUISR_SRCDATA      0x0020  /* Source data interrupt */
 119 #define HIFN_PUISR_DSTDATA      0x0010  /* Destination data interrupt */
 120 #define HIFN_PUISR_DSTRESULT    0x0004  /* Destination result interrupt */
 121
 122 /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
 123 #define HIFN_PUCNFG_DRAMMASK    0xe000  /* DRAM size mask */
 124 #define HIFN_PUCNFG_DSZ_256K    0x0000  /* 256k dram */
 125 #define HIFN_PUCNFG_DSZ_512K    0x2000  /* 512k dram */
 126 #define HIFN_PUCNFG_DSZ_1M      0x4000  /* 1m dram */
 127 #define HIFN_PUCNFG_DSZ_2M      0x6000  /* 2m dram */
 128 #define HIFN_PUCNFG_DSZ_4M      0x8000  /* 4m dram */
 129 #define HIFN_PUCNFG_DSZ_8M      0xa000  /* 8m dram */
 130 #define HIFN_PUNCFG_DSZ_16M     0xc000  /* 16m dram */
 131 #define HIFN_PUCNFG_DSZ_32M     0xe000  /* 32m dram */
 132 #define HIFN_PUCNFG_DRAMREFRESH 0x1800  /* DRAM refresh rate mask */
 133 #define HIFN_PUCNFG_DRFR_512    0x0000  /* 512 divisor of ECLK */
 134 #define HIFN_PUCNFG_DRFR_256    0x0800  /* 256 divisor of ECLK */
 135 #define HIFN_PUCNFG_DRFR_128    0x1000  /* 128 divisor of ECLK */
 136 #define HIFN_PUCNFG_TCALLPHASES 0x0200  /* your guess is as good as mine... */
 137 #define HIFN_PUCNFG_TCDRVTOTEM  0x0100  /* your guess is as good as mine... */
 138 #define HIFN_PUCNFG_BIGENDIAN   0x0080  /* DMA big endian mode */
 139 #define HIFN_PUCNFG_BUS32       0x0040  /* Bus width 32bits */
 140 #define HIFN_PUCNFG_BUS16       0x0000  /* Bus width 16 bits */
 141 #define HIFN_PUCNFG_CHIPID      0x0020  /* Allow chipid from PUSTAT */
 142 #define HIFN_PUCNFG_DRAM        0x0010  /* Context RAM is DRAM */
 143 #define HIFN_PUCNFG_SRAM        0x0000  /* Context RAM is SRAM */
 144 #define HIFN_PUCNFG_COMPSING    0x0004  /* Enable single compression context */
 145 #define HIFN_PUCNFG_ENCCNFG     0x0002  /* Encryption configuration */
 146
 147 /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
 148 #define HIFN_PUIER_CMDINVAL     0x8000  /* Invalid command interrupt */
 149 #define HIFN_PUIER_DATAERR      0x4000  /* Data error interrupt */
 150 #define HIFN_PUIER_SRCFIFO      0x2000  /* Source FIFO ready interrupt */
 151 #define HIFN_PUIER_DSTFIFO      0x1000  /* Destination FIFO ready interrupt */
 152 #define HIFN_PUIER_DSTOVER      0x0200  /* Destination overrun interrupt */
 153 #define HIFN_PUIER_SRCCMD       0x0080  /* Source command interrupt */
 154 #define HIFN_PUIER_SRCCTX       0x0040  /* Source context interrupt */
 155 #define HIFN_PUIER_SRCDATA      0x0020  /* Source data interrupt */
 156 #define HIFN_PUIER_DSTDATA      0x0010  /* Destination data interrupt */
 157 #define HIFN_PUIER_DSTRESULT    0x0004  /* Destination result interrupt */
 158
 159 /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
 160 #define HIFN_PUSTAT_CMDINVAL    0x8000  /* Invalid command interrupt */
 161 #define HIFN_PUSTAT_DATAERR     0x4000  /* Data error interrupt */
 162 #define HIFN_PUSTAT_SRCFIFO     0x2000  /* Source FIFO ready interrupt */
 163 #define HIFN_PUSTAT_DSTFIFO     0x1000  /* Destination FIFO ready interrupt */
 164 #define HIFN_PUSTAT_DSTOVER     0x0200  /* Destination overrun interrupt */
 165 #define HIFN_PUSTAT_SRCCMD      0x0080  /* Source command interrupt */
 166 #define HIFN_PUSTAT_SRCCTX      0x0040  /* Source context interrupt */
 167 #define HIFN_PUSTAT_SRCDATA     0x0020  /* Source data interrupt */
 168 #define HIFN_PUSTAT_DSTDATA     0x0010  /* Destination data interrupt */
 169 #define HIFN_PUSTAT_DSTRESULT   0x0004  /* Destination result interrupt */
 170 #define HIFN_PUSTAT_CHIPREV     0x00ff  /* Chip revision mask */
 171 #define HIFN_PUSTAT_CHIPENA     0xff00  /* Chip enabled mask */
 172 #define HIFN_PUSTAT_ENA_2       0x1100  /* Level 2 enabled */
 173 #define HIFN_PUSTAT_ENA_1       0x1000  /* Level 1 enabled */
 174 #define HIFN_PUSTAT_ENA_0       0x3000  /* Level 0 enabled */
 175 #define HIFN_PUSTAT_REV_2       0x0020  /* 7751 PT6/2 */
 176 #define HIFN_PUSTAT_REV_3       0x0030  /* 7751 PT6/3 */
 177
 178 /* FIFO Status Register (HIFN_0_FIFOSTAT) */
 179 #define HIFN_FIFOSTAT_SRC       0x7f00  /* Source FIFO available */
 180 #define HIFN_FIFOSTAT_DST       0x007f  /* Destination FIFO available */
 181
 182 /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
 183 #define HIFN_FIFOCNFG_THRESHOLD 0x0400  /* must be written as 1 */
 184
 185 /*
 186  * DMA Interface Registers (offset from BASEREG1)
 187  */
 188 #define HIFN_1_DMA_CRAR         0x0c    /* DMA Command Ring Address */
 189 #define HIFN_1_DMA_SRAR         0x1c    /* DMA Source Ring Address */
 190 #define HIFN_1_DMA_RRAR         0x2c    /* DMA Result Ring Address */
 191 #define HIFN_1_DMA_DRAR         0x3c    /* DMA Destination Ring Address */
 192 #define HIFN_1_DMA_CSR          0x40    /* DMA Status and Control */
 193 #define HIFN_1_DMA_IER          0x44    /* DMA Interrupt Enable */
 194 #define HIFN_1_DMA_CNFG         0x48    /* DMA Configuration */
 195 #define HIFN_1_PLL              0x4c    /* 795x: PLL config */
 196 #define HIFN_1_7811_RNGENA      0x60    /* 7811: rng enable */
 197 #define HIFN_1_7811_RNGCFG      0x64    /* 7811: rng config */
 198 #define HIFN_1_7811_RNGDAT      0x68    /* 7811: rng data */
 199 #define HIFN_1_7811_RNGSTS      0x6c    /* 7811: rng status */
 200 #define HIFN_1_7811_MIPSRST     0x94    /* 7811: MIPS reset */
 201 #define HIFN_1_REVID            0x98    /* Revision ID */
 202 #define HIFN_1_UNLOCK_SECRET1   0xf4
 203 #define HIFN_1_UNLOCK_SECRET2   0xfc
 204 #define HIFN_1_PUB_RESET        0x204   /* Public/RNG Reset */
 205 #define HIFN_1_PUB_BASE         0x300   /* Public Base Address */
 206 #define HIFN_1_PUB_OPLEN        0x304   /* Public Operand Length */
 207 #define HIFN_1_PUB_OP           0x308   /* Public Operand */
 208 #define HIFN_1_PUB_STATUS       0x30c   /* Public Status */
 209 #define HIFN_1_PUB_IEN          0x310   /* Public Interrupt enable */
 210 #define HIFN_1_RNG_CONFIG       0x314   /* RNG config */
 211 #define HIFN_1_RNG_DATA         0x318   /* RNG data */
 212 #define HIFN_1_PUB_MEM          0x400   /* start of Public key memory */
 213 #define HIFN_1_PUB_MEMEND       0xbff   /* end of Public key memory */
 214
 215 /* DMA Status and Control Register (HIFN_1_DMA_CSR) */
 216 #define HIFN_DMACSR_D_CTRLMASK  0xc0000000      /* Destinition Ring Control */
 217 #define HIFN_DMACSR_D_CTRL_NOP  0x00000000      /* Dest. Control: no-op */
 218 #define HIFN_DMACSR_D_CTRL_DIS  0x40000000      /* Dest. Control: disable */
 219 #define HIFN_DMACSR_D_CTRL_ENA  0x80000000      /* Dest. Control: enable */
 220 #define HIFN_DMACSR_D_ABORT     0x20000000      /* Destinition Ring PCIAbort */
 221 #define HIFN_DMACSR_D_DONE      0x10000000      /* Destinition Ring Done */
 222 #define HIFN_DMACSR_D_LAST      0x08000000      /* Destinition Ring Last */
 223 #define HIFN_DMACSR_D_WAIT      0x04000000      /* Destinition Ring Waiting */
 224 #define HIFN_DMACSR_D_OVER      0x02000000      /* Destinition Ring Overflow */
 225 #define HIFN_DMACSR_R_CTRL      0x00c00000      /* Result Ring Control */
 226 #define HIFN_DMACSR_R_CTRL_NOP  0x00000000      /* Result Control: no-op */
 227 #define HIFN_DMACSR_R_CTRL_DIS  0x00400000      /* Result Control: disable */
 228 #define HIFN_DMACSR_R_CTRL_ENA  0x00800000      /* Result Control: enable */
 229 #define HIFN_DMACSR_R_ABORT     0x00200000      /* Result Ring PCI Abort */
 230 #define HIFN_DMACSR_R_DONE      0x00100000      /* Result Ring Done */
 231 #define HIFN_DMACSR_R_LAST      0x00080000      /* Result Ring Last */
 232 #define HIFN_DMACSR_R_WAIT      0x00040000      /* Result Ring Waiting */
 233 #define HIFN_DMACSR_R_OVER      0x00020000      /* Result Ring Overflow */
 234 #define HIFN_DMACSR_S_CTRL      0x0000c000      /* Source Ring Control */
 235 #define HIFN_DMACSR_S_CTRL_NOP  0x00000000      /* Source Control: no-op */
 236 #define HIFN_DMACSR_S_CTRL_DIS  0x00004000      /* Source Control: disable */
 237 #define HIFN_DMACSR_S_CTRL_ENA  0x00008000      /* Source Control: enable */
 238 #define HIFN_DMACSR_S_ABORT     0x00002000      /* Source Ring PCI Abort */
 239 #define HIFN_DMACSR_S_DONE      0x00001000      /* Source Ring Done */
 240 #define HIFN_DMACSR_S_LAST      0x00000800      /* Source Ring Last */
 241 #define HIFN_DMACSR_S_WAIT      0x00000400      /* Source Ring Waiting */
 242 #define HIFN_DMACSR_ILLW        0x00000200      /* Illegal write (7811 only) */
 243 #define HIFN_DMACSR_ILLR        0x00000100      /* Illegal read (7811 only) */
 244 #define HIFN_DMACSR_C_CTRL      0x000000c0      /* Command Ring Control */
 245 #define HIFN_DMACSR_C_CTRL_NOP  0x00000000      /* Command Control: no-op */
 246 #define HIFN_DMACSR_C_CTRL_DIS  0x00000040      /* Command Control: disable */
 247 #define HIFN_DMACSR_C_CTRL_ENA  0x00000080      /* Command Control: enable */
 248 #define HIFN_DMACSR_C_ABORT     0x00000020      /* Command Ring PCI Abort */
 249 #define HIFN_DMACSR_C_DONE      0x00000010      /* Command Ring Done */
 250 #define HIFN_DMACSR_C_LAST      0x00000008      /* Command Ring Last */
 251 #define HIFN_DMACSR_C_WAIT      0x00000004      /* Command Ring Waiting */
 252 #define HIFN_DMACSR_PUBDONE     0x00000002      /* Public op done (7951 only) */
 253 #define HIFN_DMACSR_ENGINE      0x00000001      /* Command Ring Engine IRQ */
 254
 255 /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
 256 #define HIFN_DMAIER_D_ABORT     0x20000000      /* Destination Ring PCIAbort */
 257 #define HIFN_DMAIER_D_DONE      0x10000000      /* Destination Ring Done */
 258 #define HIFN_DMAIER_D_LAST      0x08000000      /* Destination Ring Last */
 259 #define HIFN_DMAIER_D_WAIT      0x04000000      /* Destination Ring Waiting */
 260 #define HIFN_DMAIER_D_OVER      0x02000000      /* Destination Ring Overflow */
 261 #define HIFN_DMAIER_R_ABORT     0x00200000      /* Result Ring PCI Abort */
 262 #define HIFN_DMAIER_R_DONE      0x00100000      /* Result Ring Done */
 263 #define HIFN_DMAIER_R_LAST      0x00080000      /* Result Ring Last */
 264 #define HIFN_DMAIER_R_WAIT      0x00040000      /* Result Ring Waiting */
 265 #define HIFN_DMAIER_R_OVER      0x00020000      /* Result Ring Overflow */
 266 #define HIFN_DMAIER_S_ABORT     0x00002000      /* Source Ring PCI Abort */
 267 #define HIFN_DMAIER_S_DONE      0x00001000      /* Source Ring Done */
 268 #define HIFN_DMAIER_S_LAST      0x00000800      /* Source Ring Last */
 269 #define HIFN_DMAIER_S_WAIT      0x00000400      /* Source Ring Waiting */
 270 #define HIFN_DMAIER_ILLW        0x00000200      /* Illegal write (7811 only) */
 271 #define HIFN_DMAIER_ILLR        0x00000100      /* Illegal read (7811 only) */
 272 #define HIFN_DMAIER_C_ABORT     0x00000020      /* Command Ring PCI Abort */
 273 #define HIFN_DMAIER_C_DONE      0x00000010      /* Command Ring Done */
 274 #define HIFN_DMAIER_C_LAST      0x00000008      /* Command Ring Last */
 275 #define HIFN_DMAIER_C_WAIT      0x00000004      /* Command Ring Waiting */
 276 #define HIFN_DMAIER_PUBDONE     0x00000002      /* public op done (7951 only) */
 277 #define HIFN_DMAIER_ENGINE      0x00000001      /* Engine IRQ */
 278
 279 /* DMA Configuration Register (HIFN_1_DMA_CNFG) */
 280 #define HIFN_DMACNFG_BIGENDIAN  0x10000000      /* big endian mode */
 281 #define HIFN_DMACNFG_POLLFREQ   0x00ff0000      /* Poll frequency mask */
 282 #define HIFN_DMACNFG_UNLOCK     0x00000800
 283 #define HIFN_DMACNFG_POLLINVAL  0x00000700      /* Invalid Poll Scalar */
 284 #define HIFN_DMACNFG_LAST       0x00000010      /* Host control LAST bit */
 285 #define HIFN_DMACNFG_MODE       0x00000004      /* DMA mode */
 286 #define HIFN_DMACNFG_DMARESET   0x00000002      /* DMA Reset # */
 287 #define HIFN_DMACNFG_MSTRESET   0x00000001      /* Master Reset # */
 288
 289 /* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */
 290 #define HIFN_7811_RNGENA_ENA    0x00000001      /* enable RNG */
 291
 292 /* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */
 293 #define HIFN_7811_RNGCFG_PRE1   0x00000f00      /* first prescalar */
 294 #define HIFN_7811_RNGCFG_OPRE   0x00000080      /* output prescalar */
 295 #define HIFN_7811_RNGCFG_DEFL   0x00000f80      /* 2 words/ 1/100 sec */
 296
 297 /* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */
 298 #define HIFN_7811_RNGSTS_RDY    0x00004000      /* two numbers in FIFO */
 299 #define HIFN_7811_RNGSTS_UFL    0x00001000      /* rng underflow */
 300
 301 /* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */
 302 #define HIFN_MIPSRST_BAR2SIZE   0xffff0000      /* sdram size */
 303 #define HIFN_MIPSRST_GPRAMINIT  0x00008000      /* gpram can be accessed */
 304 #define HIFN_MIPSRST_CRAMINIT   0x00004000      /* ctxram can be accessed */
 305 #define HIFN_MIPSRST_LED2       0x00000400      /* external LED2 */
 306 #define HIFN_MIPSRST_LED1       0x00000200      /* external LED1 */
 307 #define HIFN_MIPSRST_LED0       0x00000100      /* external LED0 */
 308 #define HIFN_MIPSRST_MIPSDIS    0x00000004      /* disable MIPS */
 309 #define HIFN_MIPSRST_MIPSRST    0x00000002      /* warm reset MIPS */
 310 #define HIFN_MIPSRST_MIPSCOLD   0x00000001      /* cold reset MIPS */
 311
 312 /* Revision ID */
 313 #define HIFN_REVID_7811_PB3_2   0x00000002      /* 7811PB3/2 */
 314
 315 /* Public key reset register (HIFN_1_PUB_RESET) */
 316 #define HIFN_PUBRST_RESET       0x00000001      /* reset public/rng unit */
 317
 318 /* Public base address register (HIFN_1_PUB_BASE) */
 319 #define HIFN_PUBBASE_ADDR       0x00003fff      /* base address */
 320
 321 /* Public operand length register (HIFN_1_PUB_OPLEN) */
 322 #define HIFN_PUBOPLEN_MOD_M     0x0000007f      /* modulus length mask */
 323 #define HIFN_PUBOPLEN_MOD_S     0               /* modulus length shift */
 324 #define HIFN_PUBOPLEN_EXP_M     0x0003ff80      /* exponent length mask */
 325 #define HIFN_PUBOPLEN_EXP_S     7               /* exponent length shift */
 326 #define HIFN_PUBOPLEN_RED_M     0x003c0000      /* reducend length mask */
 327 #define HIFN_PUBOPLEN_RED_S     18              /* reducend length shift */
 328
 329 /* Public operation register (HIFN_1_PUB_OP) */
 330 #define HIFN_PUBOP_AOFFSET_M    0x0000007f      /* A offset mask */
 331 #define HIFN_PUBOP_AOFFSET_S    0               /* A offset shift */
 332 #define HIFN_PUBOP_BOFFSET_M    0x00000f80      /* B offset mask */
 333 #define HIFN_PUBOP_BOFFSET_S    7               /* B offset shift */
 334 #define HIFN_PUBOP_MOFFSET_M    0x0003f000      /* M offset mask */
 335 #define HIFN_PUBOP_MOFFSET_S    12              /* M offset shift */
 336 #define HIFN_PUBOP_OP_MASK      0x003c0000      /* Opcode: */
 337 #define HIFN_PUBOP_OP_NOP       0x00000000      /*  NOP */
 338 #define HIFN_PUBOP_OP_ADD       0x00040000      /*  ADD */
 339 #define HIFN_PUBOP_OP_ADDC      0x00080000      /*  ADD w/carry */
 340 #define HIFN_PUBOP_OP_SUB       0x000c0000      /*  SUB */
 341 #define HIFN_PUBOP_OP_SUBC      0x00100000      /*  SUB w/carry */
 342 #define HIFN_PUBOP_OP_MODADD    0x00140000      /*  Modular ADD */
 343 #define HIFN_PUBOP_OP_MODSUB    0x00180000      /*  Modular SUB */
 344 #define HIFN_PUBOP_OP_INCA      0x001c0000      /*  INC A */
 345 #define HIFN_PUBOP_OP_DECA      0x00200000      /*  DEC A */
 346 #define HIFN_PUBOP_OP_MULT      0x00240000      /*  MULT */
 347 #define HIFN_PUBOP_OP_MODMULT   0x00280000      /*  Modular MULT */
 348 #define HIFN_PUBOP_OP_MODRED    0x002c0000      /*  Modular RED */
 349 #define HIFN_PUBOP_OP_MODEXP    0x00300000      /*  Modular EXP */
 350
 351 /* Public status register (HIFN_1_PUB_STATUS) */
 352 #define HIFN_PUBSTS_DONE        0x00000001      /* operation done */
 353 #define HIFN_PUBSTS_CARRY       0x00000002      /* carry */
 354
 355 /* Public interrupt enable register (HIFN_1_PUB_IEN) */
 356 #define HIFN_PUBIEN_DONE        0x00000001      /* operation done interrupt */
 357
 358 /* Random number generator config register (HIFN_1_RNG_CONFIG) */
 359 #define HIFN_RNGCFG_ENA         0x00000001      /* enable rng */
 360
 361 /*
 362  * PLL config register
 363  */
 364 #define HIFN_PLL_7956           0x00001d18      /* 7956 PLL config value */
 365
 366 /*********************************************************************
 367  * Structs for board commands
 368  *
 369  *********************************************************************/
 370
 371 /*
 372  * Structure to help build up the command data structure.
 373  */
 374 struct hifn_base_command {
 375         volatile u_int16_t masks;
 376         volatile u_int16_t session_num;
 377         volatile u_int16_t total_source_count;
 378         volatile u_int16_t total_dest_count;
 379 };
 380
 381 #define HIFN_BASE_CMD_COMP              0x0100  /* enable compression engine */
 382 #define HIFN_BASE_CMD_PAD               0x0200  /* enable padding engine */
 383 #define HIFN_BASE_CMD_MAC               0x0400  /* enable MAC engine */
 384 #define HIFN_BASE_CMD_CRYPT             0x0800  /* enable crypt engine */
 385 #define HIFN_BASE_CMD_DECODE            0x2000
 386 #define HIFN_BASE_CMD_SRCLEN_M          0xc000
 387 #define HIFN_BASE_CMD_SRCLEN_S          14
 388 #define HIFN_BASE_CMD_DSTLEN_M          0x3000
 389 #define HIFN_BASE_CMD_DSTLEN_S          12
 390 #define HIFN_BASE_CMD_LENMASK_HI        0x30000
 391 #define HIFN_BASE_CMD_LENMASK_LO        0x0ffff
 392
 393 /*
 394  * Structure to help build up the command data structure.
 395  */
 396 struct hifn_crypt_command {
 397         volatile u_int16_t masks;
 398         volatile u_int16_t header_skip;
 399         volatile u_int16_t source_count;
 400         volatile u_int16_t reserved;
 401 };
 402
 403 #define HIFN_CRYPT_CMD_ALG_MASK         0x0003          /* algorithm: */
 404 #define HIFN_CRYPT_CMD_ALG_DES          0x0000          /*   DES */
 405 #define HIFN_CRYPT_CMD_ALG_3DES         0x0001          /*   3DES */
 406 #define HIFN_CRYPT_CMD_ALG_RC4          0x0002          /*   RC4 */
 407 #define HIFN_CRYPT_CMD_ALG_AES          0x0003          /*   AES */
 408 #define HIFN_CRYPT_CMD_MODE_MASK        0x0018          /* Encrypt mode: */
 409 #define HIFN_CRYPT_CMD_MODE_ECB         0x0000          /*   ECB */
 410 #define HIFN_CRYPT_CMD_MODE_CBC         0x0008          /*   CBC */
 411 #define HIFN_CRYPT_CMD_MODE_CFB         0x0010          /*   CFB */
 412 #define HIFN_CRYPT_CMD_MODE_OFB         0x0018          /*   OFB */
 413 #define HIFN_CRYPT_CMD_CLR_CTX          0x0040          /* clear context */
 414 #define HIFN_CRYPT_CMD_NEW_KEY          0x0800          /* expect new key */
 415 #define HIFN_CRYPT_CMD_NEW_IV           0x1000          /* expect new iv */
 416
 417 #define HIFN_CRYPT_CMD_SRCLEN_M         0xc000
 418 #define HIFN_CRYPT_CMD_SRCLEN_S         14
 419
 420
 421 #define HIFN_CRYPT_CMD_KSZ_MASK         0x0600          /* AES key size: */
 422 #define HIFN_CRYPT_CMD_KSZ_128          0x0000          /*   128 bit */
 423 #define HIFN_CRYPT_CMD_KSZ_192          0x0200          /*   192 bit */
 424 #define HIFN_CRYPT_CMD_KSZ_256          0x0400          /*   256 bit */
 425
 426 /*
 427  * Structure to help build up the command data structure.
 428  */
 429 struct hifn_mac_command {
 430         volatile u_int16_t masks;
 431         volatile u_int16_t header_skip;
 432         volatile u_int16_t source_count;
 433         volatile u_int16_t reserved;
 434 };
 435
 436 #define HIFN_MAC_CMD_ALG_MASK           0x0001
 437 #define HIFN_MAC_CMD_ALG_SHA1           0x0000
 438 #define HIFN_MAC_CMD_ALG_MD5            0x0001
 439 #define HIFN_MAC_CMD_MODE_MASK          0x000c
 440 #define HIFN_MAC_CMD_MODE_HMAC          0x0000
 441 #define HIFN_MAC_CMD_MODE_SSL_MAC       0x0004
 442 #define HIFN_MAC_CMD_MODE_HASH          0x0008
 443 #define HIFN_MAC_CMD_MODE_FULL          0x0004
 444 #define HIFN_MAC_CMD_TRUNC              0x0010
 445 #define HIFN_MAC_CMD_RESULT             0x0020
 446 #define HIFN_MAC_CMD_APPEND             0x0040
 447 #define HIFN_MAC_CMD_SRCLEN_M           0xc000
 448 #define HIFN_MAC_CMD_SRCLEN_S           14
 449
 450 /*
 451  * MAC POS IPsec initiates authentication after encryption on encodes
 452  * and before decryption on decodes.
 453  */
 454 #define HIFN_MAC_CMD_POS_IPSEC          0x0200
 455 #define HIFN_MAC_CMD_NEW_KEY            0x0800
 456
 457 struct hifn_comp_command {
 458         volatile u_int16_t masks;
 459         volatile u_int16_t header_skip;
 460         volatile u_int16_t source_count;
 461         volatile u_int16_t reserved;
 462 };
 463
 464 #define HIFN_COMP_CMD_SRCLEN_M          0xc000
 465 #define HIFN_COMP_CMD_SRCLEN_S          14
 466 #define HIFN_COMP_CMD_ONE               0x0100  /* must be one */
 467 #define HIFN_COMP_CMD_CLEARHIST         0x0010  /* clear history */
 468 #define HIFN_COMP_CMD_UPDATEHIST        0x0008  /* update history */
 469 #define HIFN_COMP_CMD_LZS_STRIP0        0x0004  /* LZS: strip zero */
 470 #define HIFN_COMP_CMD_MPPC_RESTART      0x0004  /* MPPC: restart */
 471 #define HIFN_COMP_CMD_ALG_MASK          0x0001  /* compression mode: */
 472 #define HIFN_COMP_CMD_ALG_MPPC          0x0001  /*   MPPC */
 473 #define HIFN_COMP_CMD_ALG_LZS           0x0000  /*   LZS */
 474
 475 struct hifn_base_result {
 476         volatile u_int16_t flags;
 477         volatile u_int16_t session;
 478         volatile u_int16_t src_cnt;             /* 15:0 of source count */
 479         volatile u_int16_t dst_cnt;             /* 15:0 of dest count */
 480 };
 481
 482 #define HIFN_BASE_RES_DSTOVERRUN        0x0200  /* destination overrun */
 483 #define HIFN_BASE_RES_SRCLEN_M          0xc000  /* 17:16 of source count */
 484 #define HIFN_BASE_RES_SRCLEN_S          14
 485 #define HIFN_BASE_RES_DSTLEN_M          0x3000  /* 17:16 of dest count */
 486 #define HIFN_BASE_RES_DSTLEN_S          12
 487
 488 struct hifn_comp_result {
 489         volatile u_int16_t flags;
 490         volatile u_int16_t crc;
 491 };
 492
 493 #define HIFN_COMP_RES_LCB_M             0xff00  /* longitudinal check byte */
 494 #define HIFN_COMP_RES_LCB_S             8
 495 #define HIFN_COMP_RES_RESTART           0x0004  /* MPPC: restart */
 496 #define HIFN_COMP_RES_ENDMARKER         0x0002  /* LZS: end marker seen */
 497 #define HIFN_COMP_RES_SRC_NOTZERO       0x0001  /* source expired */
 498
 499 struct hifn_mac_result {
 500         volatile u_int16_t flags;
 501         volatile u_int16_t reserved;
 502         /* followed by 0, 6, 8, or 10 u_int16_t's of the MAC, then crypt */
 503 };
 504
 505 #define HIFN_MAC_RES_MISCOMPARE         0x0002  /* compare failed */
 506 #define HIFN_MAC_RES_SRC_NOTZERO        0x0001  /* source expired */
 507
 508 struct hifn_crypt_result {
 509         volatile u_int16_t flags;
 510         volatile u_int16_t reserved;
 511 };
 512
 513 #define HIFN_CRYPT_RES_SRC_NOTZERO      0x0001  /* source expired */
 514
 515 /*
 516  * The poll frequency and poll scalar defines are unshifted values used
 517  * to set fields in the DMA Configuration Register.
 518  */
 519 #ifndef HIFN_POLL_FREQUENCY
 520 #define HIFN_POLL_FREQUENCY     0x1
 521 #endif
 522
 523 #ifndef HIFN_POLL_SCALAR
 524 #define HIFN_POLL_SCALAR        0x0
 525 #endif
 526
 527 #define HIFN_MAX_SEGLEN         0xffff          /* maximum dma segment len */
 528 #define HIFN_MAX_DMALEN         0x3ffff         /* maximum dma length */
 529 #endif /* __DEV_PCI_HIFN7751REG_H__ */