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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / pci / if_iwnreg.h
blob5a38ba4db971a47c7e5d29ab1808b65202814ebe
1 /* $OpenBSD: if_iwnreg.h,v 1.20 2008/12/12 17:15:40 damien Exp $ */
2 /* $NetBSD: if_iwnreg.h,v 1.5 2008/11/13 12:04:09 blymn Exp $ */
3
4 /*-
5 * Copyright (c) 2007, 2008
6 * Damien Bergamini <damien.bergamini@free.fr>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21 #define IWN_TKIP_MICLEN 8
22
23 #define IWN_TX_RING_COUNT 256
24 #define IWN_TX_RING_LOMARK 192
25 #define IWN_TX_RING_HIMARK 224
26 #define IWN_RX_RING_COUNT_LOG 8
27 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG)
28
29 #define IWN4965_NTXQUEUES 16
30 #define IWN5000_NTXQUEUES 20
31 #define IWN_SRVC_CHNL 9
32
33 /* Maximum number of DMA segments for TX. */
34 #define IWN_MAX_SCATTER 20
35
36 /* RX buffers must be large enough to hold a full 4K A-MPDU. */
37 #define IWN_RBUF_SIZE (4 * 1024)
38
39 #if defined(__LP64__)
40 /* HW supports 36-bit DMA addresses. */
41 #define IWN_LOADDR(paddr) ((uint32_t)(paddr))
42 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf)
43 #else
44 #define IWN_LOADDR(paddr) (paddr)
45 #define IWN_HIADDR(paddr) (0)
46 #endif
47
48 /* Base Address Register. */
49 #define IWN_PCI_BAR0 PCI_MAPREG_START
50
51 /*
52 * Control and status registers.
53 */
54 #define IWN_HW_IF_CONFIG 0x000
55 #define IWN_INT_COALESCING 0x004
56 #define IWN_INT 0x008
57 #define IWN_MASK 0x00c
58 #define IWN_FH_INT 0x010
59 #define IWN_RESET 0x020
60 #define IWN_GP_CNTRL 0x024
61 #define IWN_HW_REV 0x028
62 #define IWN_EEPROM 0x02c
63 #define IWN_EEPROM_GP 0x030
64 #define IWN_GIO 0x03c
65 #define IWN_UCODE_GP1_CLR 0x05c
66 #define IWN_LED 0x094
67 #define IWN_GIO_CHICKEN 0x100
68 #define IWN_ANA_PLL 0x20c
69 #define IWN_DBG_HPET_MEM 0x240
70 #define IWN_MEM_RADDR 0x40c
71 #define IWN_MEM_WADDR 0x410
72 #define IWN_MEM_WDATA 0x418
73 #define IWN_MEM_RDATA 0x41c
74 #define IWN_PRPH_WADDR 0x444
75 #define IWN_PRPH_RADDR 0x448
76 #define IWN_PRPH_WDATA 0x44c
77 #define IWN_PRPH_RDATA 0x450
78 #define IWN_HBUS_TARG_WRPTR 0x460
79
80 /*
81 * Flow-Handler registers.
82 */
83 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8)
84 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8)
85 #define IWN_FH_KW_ADDR 0x197c
86 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4)
87 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4)
88 #define IWN_FH_STATUS_WPTR 0x1bc0
89 #define IWN_FH_RX_BASE 0x1bc4
90 #define IWN_FH_RX_WPTR 0x1bc8
91 #define IWN_FH_RX_CONFIG 0x1c00
92 #define IWN_FH_RX_STATUS 0x1c44
93 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32)
94 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32)
95 #define IWN_FH_TX_CHICKEN 0x1e98
96 #define IWN_FH_TX_STATUS 0x1eb0
97
98 /*
99 * TX scheduler registers.
100 */
101 #define IWN_SCHED_BASE 0xa02c00
102 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000)
103 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008)
104 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010)
105 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010)
106 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c)
107 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4)
108 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4)
109 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0)
110 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4)
111 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8)
112 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4)
113 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108)
114 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4)
115 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248)
116
117 /*
118 * Offsets in TX scheduler's SRAM.
119 */
120 #define IWN4965_SCHED_CTX_OFF 0x380
121 #define IWN4965_SCHED_CTX_LEN 416
122 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8)
123 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2)
124 #define IWN5000_SCHED_CTX_OFF 0x600
125 #define IWN5000_SCHED_CTX_LEN 520
126 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8)
127 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2)
128
129 /*
130 * NIC internal memory offsets.
131 */
132 #define IWN_CLOCK_CTL 0x3000
133 #define IWN_APMG_CLK_CTRL 0x3004
134 #define IWN_APMG_CLK_DIS 0x3008
135 #define IWN_APMG_PS 0x300c
136 #define IWN_APMG_PCI_STT 0x3010
137 #define IWN_BSM_WR_CTRL 0x3400
138 #define IWN_BSM_WR_MEM_SRC 0x3404
139 #define IWN_BSM_WR_MEM_DST 0x3408
140 #define IWN_BSM_WR_DWCOUNT 0x340c
141 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490
142 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494
143 #define IWN_BSM_DRAM_DATA_ADDR 0x3498
144 #define IWN_BSM_DRAM_DATA_SIZE 0x349c
145 #define IWN_BSM_SRAM_BASE 0x3800
146
147 /* Possible values for IWN_APMG_CLK_DIS. */
148 #define IWN_APMG_CLK_DMA_RQT (1 << 9)
149
150 /* Possible flags for register IWN_HW_IF_CONFIG. */
151 #define IWN_HW_IF_CONFIG_4965_R (1 << 4)
152 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8)
153 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9)
154 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21)
155 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23)
156
157 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */
158 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24)
159
160 /* Possible values for IWN_BSM_WR_MEM_DST. */
161 #define IWN_FW_TEXT_BASE 0x00000000
162 #define IWN_FW_DATA_BASE 0x00800000
163
164 /* Possible flags for register IWN_RESET. */
165 #define IWN_RESET_NEVO (1 << 0)
166 #define IWN_RESET_SW (1 << 7)
167 #define IWN_RESET_MASTER_DISABLED (1 << 8)
168 #define IWN_RESET_STOP_MASTER (1 << 9)
169
170 /* Possible flags for register IWN_GP_CNTRL. */
171 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0)
172 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0)
173 #define IWN_GP_CNTRL_INIT_DONE (1 << 2)
174 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3)
175 #define IWN_GP_CNTRL_SLEEP (1 << 4)
176 #define IWN_GP_CNTRL_RFKILL (1 << 27)
177
178 /* Possible flags for register IWN_HW_REV. */
179 #define IWN_HW_REV_TYPE_SHIFT 4
180 #define IWN_HW_REV_TYPE_MASK 0x000000f0
181 #define IWN_HW_REV_TYPE_4965 0
182 #define IWN_HW_REV_TYPE_5300 2
183 #define IWN_HW_REV_TYPE_5350 3
184 #define IWN_HW_REV_TYPE_5150 4
185 #define IWN_HW_REV_TYPE_5100 5
186 #define IWN_HW_REV_TYPE_1000 6
187 #define IWN_HW_REV_TYPE_6000 7
188 #define IWN_HW_REV_TYPE_6050 8
189
190 /* Possible flags for register IWN_GIO_CHICKEN. */
191 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23)
192 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29)
193
194 /* Possible flags for register IWN_GIO. */
195 #define IWN_GIO_L0S_ENA (1 << 1)
196
197 /* Possible flags for register IWN_UCODE_GP1_CLR. */
198 #define IWN_UCODE_GP1_RFKILL (1 << 1)
199 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2)
200 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3)
201
202 /* Possible flags/values for register IWN_LED. */
203 #define IWN_LED_BSM_CTRL (1 << 5)
204 #define IWN_LED_OFF 0x00000038
205 #define IWN_LED_ON 0x00000078
206
207 /* Possible values for register IWN_ANA_PLL. */
208 #define IWN_ANA_PLL_INIT 0x00880300
209
210 /* Possible flags for register IWN_FH_RX_STATUS. */
211 #define IWN_FH_RX_STATUS_IDLE (1 << 24)
212
213 /* Possible flags for register IWN_BSM_WR_CTRL. */
214 #define IWN_BSM_WR_CTRL_START_EN (1 << 30)
215 #define IWN_BSM_WR_CTRL_START (1 << 31)
216
217 /* Possible flags for register IWN_INT. */
218 #define IWN_INT_ALIVE (1 << 0)
219 #define IWN_INT_WAKEUP (1 << 1)
220 #define IWN_INT_SW_RX (1 << 3)
221 #define IWN_INT_CT_REACHED (1 << 6)
222 #define IWN_INT_RF_TOGGLED (1 << 7)
223 #define IWN_INT_SW_ERR (1 << 25)
224 #define IWN_INT_FH_TX (1 << 27)
225 #define IWN_INT_HW_ERR (1 << 29)
226 #define IWN_INT_FH_RX (1 << 31)
227
228 /* Shortcut. */
229 #define IWN_INT_MASK \
230 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \
231 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \
232 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED)
233
234 /* Possible flags for register IWN_FH_INT. */
235 #define IWN_FH_INT_TX_CHNL(x) (1 << (x))
236 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16))
237 #define IWN_FH_INT_HI_PRIOR (1 << 30)
238 /* Shortcuts for the above. */
239 #define IWN_FH_INT_TX \
240 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1))
241 #define IWN_FH_INT_RX \
242 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR)
243
244 /* Possible flags/values for register IWN_FH_TX_CONFIG. */
245 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0
246 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31)
247 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20)
248
249 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */
250 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20)
251 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12)
252 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3
253
254 /* Possible flags for register IWN_FH_TX_CHICKEN. */
255 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1)
256
257 /* Possible flags for register IWN_FH_TX_STATUS. */
258 #define IWN_FH_TX_STATUS_IDLE(chnl) \
259 (1 << ((chnl) + 24) | 1 << ((chnl) + 16))
260
261 /* Possible flags for register IWN_FH_RX_CONFIG. */
262 #define IWN_FH_RX_CONFIG_ENA (1 << 31)
263 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20)
264 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16)
265 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15)
266 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12)
267 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4)
268 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2)
269
270 /* Possible flags for register IWN_FH_TX_CONFIG. */
271 #define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31)
272 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3)
273
274 /* Possible flags for register IWN_EEPROM. */
275 #define IWN_EEPROM_READ_VALID (1 << 0)
276 #define IWN_EEPROM_CMD (1 << 1)
277
278 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */
279 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01
280 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00
281 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8)
282 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10)
283 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018
284 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010
285 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19)
286
287 /* Possible flags for register IWN_APMG_CLK_CTRL. */
288 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9)
289 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11)
290
291 /* Possible flags for register IWN_APMG_PS. */
292 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22)
293 #define IWN_APMG_PS_PWR_SRC_MASK (3 << 24)
294 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24)
295 #define IWN_APMG_PS_PWR_SRC_VMAIN 0
296
297 /* Possible flags for IWN_APMG_PCI_STT. */
298 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11)
299
300 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */
301 #define IWN_FW_UPDATED (1 << 31)
302
303 #define IWN_SCHED_WINSZ 64
304 #define IWN_SCHED_LIMIT 64
305 #define IWN4965_SCHED_COUNT 512
306 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ)
307 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2)
308 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2)
309
310 struct iwn_tx_desc {
311 uint8_t reserved1[3];
312 uint8_t nsegs;
313 struct {
314 uint32_t addr;
315 uint16_t len;
316 } __packed segs[IWN_MAX_SCATTER];
317 /* Pad to 128 bytes. */
318 uint32_t reserved2;
319 } __packed;
320
321 struct iwn_rx_status {
322 uint16_t closed_count;
323 uint16_t closed_rx_count;
324 uint16_t finished_count;
325 uint16_t finished_rx_count;
326 uint32_t reserved[2];
327 } __packed;
328
329 struct iwn_rx_desc {
330 uint32_t len;
331 uint8_t type;
332 #define IWN_UC_READY 1
333 #define IWN_UC_ERROR 2
334 #define IWN_RXON 16
335 #define IWN_RXON_ASSOC 17
336 #define IWN_QOS_PARAM 19
337 #define IWN_RXON_TIMING 20
338 #define IWN_ADD_NODE_DONE 24
339 #define IWN_REMOVE_NODE_DONE 25
340 #define IWN_REMOVE_ALL_NODE_DONE 26
341 #define IWN_TX_DONE 28
342 #define IWN3945_RATE_SCALE 71
343 #define IWN_LEDS_CMD 72
344 #define IWN_4965_TX_LINK_QUALITY 78
345 #define IWN5000_CALIBRATION_RESULT 102
346 #define IWN5000_CALIBRATION_DONE 103
347 #define IWN_RADAR_NOTIFICATION 112
348 #define IWN_QUIET_CMD 113
349 #define IWN_CHANNEL_SWITCH 114
350 #define IWN_CHANNEL_SWITCH_NOTIFICATION 115
351 #define IWN_SPECTRUM_MEASUREMENT_CMD 116
352 #define IWN_SPECTRUM_MEASUREMENT_NOTIFICATION 117
353 #define IWN_POWER_TABLE_CMD 119
354 #define IWN_PM_SLEEP_NOTIFICATION 120
355 #define IWN_DEBUG_STATISTICS_NOTIFICATION 112
356 #define IWN_SCAN_CMD 128
357 #define IWN_SCAN_ABORT_CMD 129
358 #define IWN_SCAN_START_NOTIFICATION 130
359 #define IWN_START_SCAN 130
360 #define IWN_SCAN_RESULTS_NOTIFICATION 131
361 #define IWN_SCAN_COMPLETE_NOTIFICATION 132
362 #define IWN_STOP_SCAN 132
363 #define IWN_BEACON_NOTIFICATION 144
364 #define IWN_TX_BEACON 145
365 #define IWN_WHO_IS_AWAKE_NOTIFICATION 146
366 #define IWN_QUIET_NOTIFICATION 150
367 #define IWN_TX_PWR_TABLE_CMD 151
368 #define IWN_MEASURE_ABORT_CMD 153
369 #define IWN_BT_CONFIG 155
370 #define IWN_RX_STATISTICS 156
371 #define IWN_BEACON_STATISTICS 157
372 #define IWN_CARD_STATE_CMD 160
373 #define IWN_STATE_CHANGED 161
374 #define IWN_BEACON_MISSED 162
375 #define IWN_CT_KILL_CONFIG_CMD 164
376 #define IWN_SENSITIVITY_CMD 168
377 #define IWN_PHY_CALIBRATION_CMD 176
378 #define IWN_RX_PHY 192
379 #define IWN_MPDU_RX_DONE 193
380 #define IWN4965_RX_DONE 195
381 #define IWN_RX_DONE 195
382 #define IWN_COMPRESSED_BA 197
383
384 uint8_t flags;
385 uint8_t idx;
386 uint8_t qid;
387 } __packed;
388
389 /* Possible RX status flags. */
390 #define IWN_RX_NO_CRC_ERR (1 << 0)
391 #define IWN_RX_NO_OVFL_ERR (1 << 1)
392 /* Shortcut for the above. */
393 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR)
394 #define IWN_RX_MPDU_MIC_OK (1 << 6)
395 #define IWN_RX_CIPHER_MASK (7 << 8)
396 #define IWN_RX_CIPHER_CCMP (2 << 8)
397 #define IWN_RX_MPDU_DEC (1 << 11)
398 #define IWN_RX_DECRYPT_MASK (3 << 11)
399 #define IWN_RX_DECRYPT_OK (3 << 11)
400
401 struct iwn_tx_cmd {
402 uint8_t code;
403 #define IWN_CMD_CONFIGURE 16
404 #define IWN_CMD_ASSOCIATE 17
405 #define IWN_CMD_EDCA_PARAMS 19
406 #define IWN_CMD_TIMING 20
407 #define IWN_CMD_ADD_NODE 24
408 #define IWN_CMD_TX_DATA 28
409 #define IWN_CMD_LINK_QUALITY 78
410 #define IWN_CMD_SET_LED 72
411 #define IWN5000_CMD_WIMAX_COEX 90
412 #define IWN5000_CMD_CALIB_CONFIG 101
413 #define IWN_CMD_SET_POWER_MODE 119
414 #define IWN_CMD_SCAN 128
415 #define IWN_CMD_SET_BEACON 145
416 #define IWN_CMD_TXPOWER 151
417 #define IWN_CMD_TXPOWER_DBM 152
418 #define IWN_CMD_BT_COEX 155
419 #define IWN_CMD_GET_STATISTICS 156
420 #define IWN_CMD_SET_CRITICAL_TEMP 164
421 #define IWN_CMD_SET_SENSITIVITY 168
422 #define IWN_CMD_PHY_CALIB 176
423
424 uint8_t flags;
425 uint8_t idx;
426 uint8_t qid;
427 uint8_t data[136];
428 } __packed;
429
430 /* Antenna flags, used in various commands. */
431 #define IWN_ANT_A (1 << 0)
432 #define IWN_ANT_B (1 << 1)
433 #define IWN_ANT_C (1 << 2)
434 /* Shortcut. */
435 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C)
436
437 /* Structure for command IWN_CMD_CONFIGURE. */
438 struct iwn_rxon {
439 uint8_t myaddr[IEEE80211_ADDR_LEN];
440 uint16_t reserved1;
441 uint8_t bssid[IEEE80211_ADDR_LEN];
442 uint16_t reserved2;
443 uint8_t wlap[IEEE80211_ADDR_LEN];
444 uint16_t reserved3;
445 uint8_t mode;
446 #define IWN_MODE_HOSTAP 1
447 #define IWN_MODE_STA 3
448 #define IWN_MODE_IBSS 4
449 #define IWN_MODE_MONITOR 6
450
451 uint8_t air;
452 uint16_t rxchain;
453 #define IWN_RXCHAIN_FORCE (1 << 0)
454 #define IWN_RXCHAIN_VALID(x) ((x) << 1)
455 #define IWN_RXCHAIN_SEL(x) ((x) << 4)
456 #define IWN_RXCHAIN_MIMO(x) ((x) << 7)
457 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10)
458 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12)
459 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14)
460
461 uint8_t ofdm_mask;
462 uint8_t cck_mask;
463 uint16_t associd;
464 uint32_t flags;
465 #define IWN_RXON_24GHZ (1 << 0)
466 #define IWN_RXON_CCK (1 << 1)
467 #define IWN_RXON_AUTO (1 << 2)
468 #define IWN_RXON_SHSLOT (1 << 4)
469 #define IWN_RXON_SHPREAMBLE (1 << 5)
470 #define IWN_RXON_NODIVERSITY (1 << 7)
471 #define IWN_RXON_ANTENNA_A (1 << 8)
472 #define IWN_RXON_ANTENNA_B (1 << 9)
473 #define IWN_RXON_TSF (1 << 15)
474 #define IWN_RXON_CTS_TO_SELF (1 << 30)
475
476 uint32_t filter;
477 #define IWN_FILTER_PROMISC (1 << 0)
478 #define IWN_FILTER_CTL (1 << 1)
479 #define IWN_FILTER_MULTICAST (1 << 2)
480 #define IWN_FILTER_NODECRYPT (1 << 3)
481 #define IWN_FILTER_BSS (1 << 5)
482 #define IWN_FILTER_BEACON (1 << 6)
483
484 uint8_t chan;
485 uint8_t reserved4;
486 uint8_t ht_single_mask;
487 uint8_t ht_dual_mask;
488 /* The following fields are for 5000 Series only. */
489 uint8_t ht_triple_mask;
490 uint8_t reserved5;
491 uint16_t acquisition;
492 uint16_t reserved6;
493 } __packed;
494
495 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6)
496 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon))
497
498 /* Structure for command IWN_CMD_ASSOCIATE. */
499 struct iwn_assoc {
500 uint32_t flags;
501 uint32_t filter;
502 uint8_t ofdm_mask;
503 uint8_t cck_mask;
504 uint16_t reserved;
505 } __packed;
506
507 /* Structure for command IWN_CMD_EDCA_PARAMS. */
508 struct iwn_edca_params {
509 uint32_t flags;
510 #define IWN_EDCA_UPDATE (1 << 0)
511 #define IWN_EDCA_TXOP (1 << 4)
512
513 struct {
514 uint16_t cwmin;
515 uint16_t cwmax;
516 uint8_t aifsn;
517 uint8_t reserved;
518 uint16_t txoplimit;
519 } __packed ac[WME_NUM_AC];
520 } __packed;
521
522 /* Structure for command IWN_CMD_TIMING. */
523 struct iwn_cmd_timing {
524 uint64_t tstamp;
525 uint16_t bintval;
526 uint16_t atim;
527 uint32_t binitval;
528 uint16_t lintval;
529 uint16_t reserved;
530 } __packed;
531
532 /* Structure for command IWN_CMD_ADD_NODE. */
533 struct iwn_node_info {
534 uint8_t control;
535 #define IWN_NODE_UPDATE (1 << 0)
536
537 uint8_t reserved1[3];
538
539 uint8_t macaddr[IEEE80211_ADDR_LEN];
540 uint16_t reserved2;
541 uint8_t id;
542 #define IWN_ID_BSS 0
543 #define IWN5000_ID_BROADCAST 15
544 #define IWN4965_ID_BROADCAST 31
545
546 uint8_t flags;
547 #define IWN_FLAG_SET_KEY (1 << 0)
548 #define IWN_FLAG_SET_DISABLE_TID (1 << 1)
549 #define IWN_FLAG_SET_TXRATE (1 << 2)
550 #define IWN_FLAG_SET_ADDBA (1 << 3)
551 #define IWN_FLAG_SET_DELBA (1 << 4)
552
553 uint16_t reserved3;
554 uint16_t kflags;
555 #define IWN_KFLAG_CCMP (1 << 1)
556 #define IWN_KFLAG_MAP (1 << 3)
557 #define IWN_KFLAG_KID(kid) ((kid) << 8)
558 #define IWN_KFLAG_INVALID (1 << 11)
559 #define IWN_KFLAG_GROUP (1 << 14)
560
561 uint8_t tsc2; /* TKIP TSC2 */
562 uint8_t reserved4;
563 uint16_t ttak[5];
564 uint8_t kid;
565 uint8_t reserved5;
566 uint8_t key[16];
567 /* The following 3 fields are for 5000 Series only. */
568 uint64_t tsc;
569 uint8_t rxmic[IWN_TKIP_MICLEN];
570 uint8_t txmic[IWN_TKIP_MICLEN];
571
572 uint32_t htflags;
573 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19)
574 #define IWN_AMDPU_DENSITY(x) ((x) << 23)
575
576 uint32_t mask;
577 uint16_t disable_tid;
578 uint16_t reserved6;
579 uint8_t addba_tid;
580 uint8_t delba_tid;
581 uint16_t addba_ssn;
582 uint32_t reserved7;
583 } __packed;
584
585 struct iwn4965_node_info {
586 uint8_t control;
587 uint8_t reserved1[3];
588 uint8_t macaddr[IEEE80211_ADDR_LEN];
589 uint16_t reserved2;
590 uint8_t id;
591 uint8_t flags;
592 uint16_t reserved3;
593 uint16_t kflags;
594 uint8_t tsc2; /* TKIP TSC2 */
595 uint8_t reserved4;
596 uint16_t ttak[5];
597 uint8_t kid;
598 uint8_t reserved5;
599 uint8_t key[16];
600 uint32_t htflags;
601 uint32_t mask;
602 uint16_t disable_tid;
603 uint16_t reserved6;
604 uint8_t addba_tid;
605 uint8_t delba_tid;
606 uint16_t addba_ssn;
607 uint32_t reserved7;
608 } __packed;
609
610 #define IWN_RFLAG_CCK (1 << 1)
611 #define IWN_RFLAG_ANT(x) ((x) << 6)
612
613 /* Structure for command IWN_CMD_TX_DATA. */
614 struct iwn_cmd_data {
615 uint16_t len;
616 uint16_t lnext;
617 uint32_t flags;
618 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */
619 #define IWN_TX_NEED_RTS (1 << 1)
620 #define IWN_TX_NEED_CTS (1 << 2)
621 #define IWN_TX_NEED_ACK (1 << 3)
622 #define IWN_TX_LINKQ (1 << 4)
623 #define IWN_TX_IMM_BA (1 << 6)
624 #define IWN_TX_FULL_TXOP (1 << 7)
625 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */
626 #define IWN_TX_AUTO_SEQ (1 << 13)
627 #define IWN_TX_MORE_FRAG (1 << 14)
628 #define IWN_TX_INSERT_TSTAMP (1 << 16)
629 #define IWN_TX_NEED_PADDING (1 << 20)
630
631 uint32_t scratch;
632 uint8_t plcp;
633 uint8_t rflags;
634 uint16_t xrflags;
635
636 uint8_t id;
637 uint8_t security;
638 #define IWN_CIPHER_WEP40 1
639 #define IWN_CIPHER_CCMP 2
640 #define IWN_CIPHER_TKIP 3
641 #define IWN_CIPHER_WEP104 9
642
643 uint8_t linkq;
644 uint8_t reserved2;
645 uint8_t key[16];
646 uint16_t fnext;
647 uint16_t reserved3;
648 uint32_t lifetime;
649 #define IWN_LIFETIME_INFINITE 0xffffffff
650
651 uint32_t loaddr;
652 uint8_t hiaddr;
653 uint8_t rts_ntries;
654 uint8_t data_ntries;
655 uint8_t tid;
656 uint16_t timeout;
657 uint16_t txop;
658 } __packed;
659
660 /* Structure for command IWN_CMD_LINK_QUALITY. */
661 #define IWN_MAX_TX_RETRIES 16
662 struct iwn_cmd_link_quality {
663 uint8_t id;
664 uint8_t reserved1;
665 uint16_t ctl;
666 uint8_t flags;
667 uint8_t mimo;
668 uint8_t antmsk_1stream;
669 uint8_t antmsk_2stream;
670 uint8_t ridx[WME_NUM_AC];
671 uint16_t ampdu_limit;
672 uint8_t ampdu_threshold;
673 uint8_t ampdu_max;
674 uint32_t reserved2;
675 struct {
676 uint8_t plcp;
677 uint8_t rflags;
678 uint16_t xrflags;
679 } __packed retry[IWN_MAX_TX_RETRIES];
680 uint32_t reserved3;
681 } __packed;
682
683 /* Structure for command IWN_CMD_SET_LED. */
684 struct iwn_cmd_led {
685 uint32_t unit; /* multiplier (in usecs) */
686 uint8_t which;
687 #define IWN_LED_ACTIVITY 1
688 #define IWN_LED_LINK 2
689
690 uint8_t off;
691 uint8_t on;
692 uint8_t reserved;
693 } __packed;
694
695 /* Structure for command IWN5000_CMD_WIMAX_COEX. */
696 struct iwn5000_wimax_coex {
697 uint32_t flags;
698 struct {
699 uint8_t request;
700 uint8_t window;
701 uint8_t reserved;
702 uint8_t flags;
703 } __packed events[16];
704 } __packed;
705
706 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */
707 struct iwn5000_calib_elem {
708 uint32_t enable;
709 uint32_t start;
710 uint32_t send;
711 uint32_t apply;
712 uint32_t reserved;
713 } __packed;
714
715 struct iwn5000_calib_status {
716 struct iwn5000_calib_elem once;
717 struct iwn5000_calib_elem perd;
718 uint32_t flags;
719 } __packed;
720
721 struct iwn5000_calib_config {
722 struct iwn5000_calib_status ucode;
723 struct iwn5000_calib_status driver;
724 uint32_t reserved;
725 } __packed;
726
727 /* Structure for command IWN_CMD_SET_POWER_MODE. */
728 struct iwn_pmgt_cmd {
729 uint16_t flags;
730 #define IWN_PS_ALLOW_SLEEP (1 << 0)
731 #define IWN_PS_NOTIFY (1 << 1)
732 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2)
733 #define IWN_PS_PCI_PMGT (1 << 3)
734 #define IWN_PS_FAST_PD (1 << 4)
735
736 uint8_t keepalive;
737 uint8_t debug;
738 uint32_t rxtimeout;
739 uint32_t txtimeout;
740 uint32_t intval[5];
741 uint32_t beacons;
742 } __packed;
743
744 /* Structures for command IWN_CMD_SCAN. */
745 struct iwn_scan_essid {
746 uint8_t id;
747 uint8_t len;
748 uint8_t data[IEEE80211_NWID_LEN];
749 } __packed;
750
751 #define IWN_MAX_PROBES 20
752
753 struct iwn_scan_hdr {
754 uint16_t len;
755 uint8_t reserved1;
756 uint8_t nchan;
757 uint16_t quiet_time;
758 uint16_t quiet_threshold;
759 uint16_t crc_threshold;
760 uint16_t rxchain;
761 uint32_t max_svc; /* background scans */
762 uint32_t pause_svc; /* background scans */
763 uint32_t flags;
764 uint32_t filter;
765 struct iwn_cmd_data tx_cmd;
766 struct iwn_scan_essid scan_essid[IWN_MAX_PROBES];
767 struct ieee80211_frame wh;
768 uint8_t data[0]; /* nchan x struct iwn_scan_chan */
769 } __packed;
770
771 struct iwn_scan_chan {
772 uint32_t flags;
773 #define IWN_CHAN_ACTIVE (1 << 0)
774 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1)
775
776 uint16_t chan;
777 uint8_t rf_gain;
778 uint8_t dsp_gain;
779 uint16_t active; /* msecs */
780 uint16_t passive; /* msecs */
781 } __packed;
782
783 /* Maximum size of a scan command. */
784 #define IWN_SCAN_MAXSZ (MCLBYTES - 4)
785
786 /* structure for command IWN_CMD_SET_BEACON */
787 struct iwn_cmd_beacon {
788 uint16_t len;
789 uint16_t reserved1;
790 uint32_t flags; /* same as iwn_cmd_data */
791 uint8_t try_cnt;
792 uint8_t kill_cnt;
793 uint16_t reserved2;
794 uint8_t rate;
795 uint8_t flags2;
796 uint16_t ext_flags;
797 uint8_t id;
798 uint8_t reserved3[23];
799 uint32_t lifetime;
800 uint32_t reserved4;
801 uint8_t reserved5;
802 uint8_t reserved6;
803 uint8_t reserved7;
804 uint16_t reserved8[9];
805 uint16_t tim;
806 uint8_t timsz;
807 uint8_t reserved9;
808 struct ieee80211_frame wh;
809 } __packed;
810
811
812 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */
813 #define IWN_RIDX_MAX 32
814 struct iwn4965_cmd_txpower {
815 uint8_t band;
816 uint8_t reserved1;
817 uint8_t chan;
818 uint8_t reserved2;
819 struct {
820 uint8_t rf_gain[2];
821 uint8_t dsp_gain[2];
822 } __packed power[IWN_RIDX_MAX + 1];
823 } __packed;
824
825 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */
826 struct iwn5000_cmd_txpower {
827 int8_t global_limit; /* in half-dBm */
828 #define IWN5000_TXPOWER_AUTO 0x7f
829 #define IWN5000_TXPOWER_MAX_DBM 16
830
831 uint8_t flags;
832 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6)
833
834 int8_t srv_limit; /* in half-dBm */
835 uint8_t reserved;
836 } __packed;
837
838 /* Structure for command IWN_CMD_BLUETOOTH. */
839 struct iwn_bluetooth {
840 uint8_t flags;
841 uint8_t lead;
842 uint8_t kill;
843 uint8_t reserved;
844 uint32_t ack;
845 uint32_t cts;
846 } __packed;
847
848 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */
849 struct iwn_critical_temp {
850 uint32_t reserved;
851 uint32_t tempM;
852 uint32_t tempR;
853 /* degK <-> degC conversion macros. */
854 #define IWN_CTOK(c) ((c) + 273)
855 #define IWN_KTOC(k) ((k) - 273)
856 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000)
857 } __packed;
858
859 /* Structure for command IWN_CMD_SET_SENSITIVITY. */
860 struct iwn_sensitivity_cmd {
861 uint16_t which;
862 #define IWN_SENSITIVITY_DEFAULTTBL 0
863 #define IWN_SENSITIVITY_WORKTBL 1
864
865 uint16_t energy_cck;
866 uint16_t energy_ofdm;
867 uint16_t corr_ofdm_x1;
868 uint16_t corr_ofdm_mrc_x1;
869 uint16_t corr_cck_mrc_x4;
870 uint16_t corr_ofdm_x4;
871 uint16_t corr_ofdm_mrc_x4;
872 uint16_t corr_barker;
873 uint16_t corr_barker_mrc;
874 uint16_t corr_cck_x4;
875 uint16_t energy_ofdm_th;
876 } __packed;
877
878 /* Structures for command IWN_CMD_PHY_CALIB. */
879 struct iwn_phy_calib {
880 uint8_t code;
881 #define IWN4965_PHY_CALIB_DIFF_GAIN 7
882 #define IWN5000_PHY_CALIB_DC 8
883 #define IWN5000_PHY_CALIB_LO 9
884 #define IWN5000_PHY_CALIB_TX_IQ 11
885 #define IWN5000_PHY_CALIB_CRYSTAL 15
886 #define IWN5000_PHY_CALIB_BASE_BAND 16
887 #define IWN5000_PHY_CALIB_TX_IQ_PERD 17
888 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18
889 #define IWN5000_PHY_CALIB_NOISE_GAIN 19
890
891 uint8_t group;
892 uint8_t ngroups;
893 uint8_t isvalid;
894 } __packed;
895
896 struct iwn5000_phy_calib_crystal {
897 uint8_t code;
898 uint8_t group;
899 uint8_t ngroups;
900 uint8_t isvalid;
901
902 uint8_t cap_pin[2];
903 uint8_t reserved[2];
904 } __packed;
905
906 struct iwn_phy_calib_gain {
907 uint8_t code;
908 uint8_t group;
909 uint8_t ngroups;
910 uint8_t isvalid;
911
912 int8_t gain[3];
913 uint8_t reserved;
914 } __packed;
915
916 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */
917 struct iwn_spectrum_cmd {
918 uint16_t len;
919 uint8_t token;
920 uint8_t id;
921 uint8_t origin;
922 uint8_t periodic;
923 uint16_t timeout;
924 uint32_t start;
925 uint32_t reserved1;
926 uint32_t flags;
927 uint32_t filter;
928 uint16_t nchan;
929 uint16_t reserved2;
930 struct {
931 uint32_t duration;
932 uint8_t chan;
933 uint8_t type;
934 #define IWN_MEASUREMENT_BASIC (1 << 0)
935 #define IWN_MEASUREMENT_CCA (1 << 1)
936 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2)
937 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3)
938 #define IWN_MEASUREMENT_FRAME (1 << 4)
939 #define IWN_MEASUREMENT_IDLE (1 << 7)
940
941 uint16_t reserved;
942 } __packed chan[10];
943 } __packed;
944
945 /* Structure for IWN_UC_READY notification. */
946 #define IWN_NATTEN_GROUPS 5
947 struct iwn_ucode_info {
948 uint8_t minor;
949 uint8_t major;
950 uint16_t reserved1;
951 uint8_t revision[8];
952 uint8_t type;
953 uint8_t subtype;
954 #define IWN_UCODE_RUNTIME 0
955 #define IWN_UCODE_INIT 9
956
957 uint16_t reserved2;
958 uint32_t logptr;
959 uint32_t errptr;
960 uint32_t tstamp;
961 uint32_t valid;
962
963 /* The following fields are for UCODE_INIT only. */
964 int32_t volt;
965 struct {
966 int32_t chan20MHz;
967 int32_t chan40MHz;
968 } __packed temp[4];
969 int32_t atten[IWN_NATTEN_GROUPS][2];
970 } __packed;
971
972 /* Structures for IWN_TX_DONE notification. */
973 struct iwn4965_tx_stat {
974 uint8_t nframes;
975 uint8_t killcnt;
976 uint8_t rtscnt;
977 uint8_t retrycnt;
978 uint8_t rate;
979 uint8_t rflags;
980 uint16_t xrflags;
981 uint16_t duration;
982 uint16_t reserved;
983 uint32_t power[2];
984 uint32_t status;
985 } __packed;
986
987 struct iwn5000_tx_stat {
988 uint8_t nframes;
989 uint8_t killcnt;
990 uint8_t rtscnt;
991 uint8_t retrycnt;
992 uint8_t rate;
993 uint8_t rflags;
994 uint16_t xrflags;
995 uint16_t duration;
996 uint16_t reserved;
997 uint32_t power[2];
998 uint32_t info;
999 uint16_t seq;
1000 uint16_t len;
1001 uint32_t tlc;
1002 uint16_t status;
1003 uint16_t sequence;
1004 } __packed;
1005
1006 /* Structure for IWN_BEACON_MISSED notification. */
1007 struct iwn_beacon_missed {
1008 uint32_t consecutive;
1009 uint32_t total;
1010 uint32_t expected;
1011 uint32_t received;
1012 } __packed;
1013
1014 /* Structure for IWN_MPDU_RX_DONE notification. */
1015 struct iwn_rx_mpdu {
1016 uint16_t len;
1017 uint16_t reserved;
1018 } __packed;
1019
1020 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */
1021 struct iwn4965_rx_phystat {
1022 uint16_t antenna;
1023 uint16_t agc;
1024 uint8_t rssi[6];
1025 } __packed;
1026
1027 struct iwn5000_rx_phystat {
1028 uint32_t reserved1;
1029 uint32_t agc;
1030 uint16_t rssi[3];
1031 } __packed;
1032
1033 struct iwn_rx_stat {
1034 uint8_t phy_len;
1035 uint8_t cfg_phy_len;
1036 #define IWN_STAT_MAXLEN 20
1037
1038 uint8_t id;
1039 uint8_t reserved1;
1040 uint64_t tstamp;
1041 uint32_t beacon;
1042 uint16_t flags;
1043 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2)
1044
1045 uint16_t chan;
1046 uint8_t phybuf[32];
1047 uint8_t rate;
1048 uint8_t rflags;
1049 uint16_t xrflags;
1050 uint16_t len;
1051 uint16_t reserve3;
1052 } __packed;
1053
1054 #define IWN_RSSI_TO_DBM 44
1055
1056 /* Structure for IWN_START_SCAN notification. */
1057 struct iwn_start_scan {
1058 uint64_t tstamp;
1059 uint32_t tbeacon;
1060 uint8_t chan;
1061 uint8_t band;
1062 uint16_t reserved;
1063 uint32_t status;
1064 } __packed;
1065
1066 /* Structure for IWN_STOP_SCAN notification. */
1067 struct iwn_stop_scan {
1068 uint8_t nchan;
1069 uint8_t status;
1070 uint8_t reserved;
1071 uint8_t chan;
1072 uint64_t tsf;
1073 } __packed;
1074
1075 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */
1076 struct iwn_spectrum_notif {
1077 uint8_t id;
1078 uint8_t token;
1079 uint8_t idx;
1080 uint8_t state;
1081 #define IWN_MEASUREMENT_START 0
1082 #define IWN_MEASUREMENT_STOP 1
1083
1084 uint32_t start;
1085 uint8_t band;
1086 uint8_t chan;
1087 uint8_t type;
1088 uint8_t reserved1;
1089 uint32_t cca_ofdm;
1090 uint32_t cca_cck;
1091 uint32_t cca_time;
1092 uint8_t basic;
1093 uint8_t reserved2[3];
1094 uint32_t ofdm[8];
1095 uint32_t cck[8];
1096 uint32_t stop;
1097 uint32_t status;
1098 #define IWN_MEASUREMENT_OK 0
1099 #define IWN_MEASUREMENT_CONCURRENT 1
1100 #define IWN_MEASUREMENT_CSA_CONFLICT 2
1101 #define IWN_MEASUREMENT_TGH_CONFLICT 3
1102 #define IWN_MEASUREMENT_STOPPED 6
1103 #define IWN_MEASUREMENT_TIMEOUT 7
1104 #define IWN_MEASUREMENT_FAILED 8
1105 } __packed;
1106
1107 /* Structure for IWN_{RX,BEACON}_STATISTICS notification. */
1108 struct iwn_rx_phy_stats {
1109 uint32_t ina;
1110 uint32_t fina;
1111 uint32_t bad_plcp;
1112 uint32_t bad_crc32;
1113 uint32_t overrun;
1114 uint32_t eoverrun;
1115 uint32_t good_crc32;
1116 uint32_t fa;
1117 uint32_t bad_fina_sync;
1118 uint32_t sfd_timeout;
1119 uint32_t fina_timeout;
1120 uint32_t no_rts_ack;
1121 uint32_t rxe_limit;
1122 uint32_t ack;
1123 uint32_t cts;
1124 uint32_t ba_resp;
1125 uint32_t dsp_kill;
1126 uint32_t bad_mh;
1127 uint32_t rssi_sum;
1128 uint32_t reserved;
1129 } __packed;
1130
1131 struct iwn_rx_general_stats {
1132 uint32_t bad_cts;
1133 uint32_t bad_ack;
1134 uint32_t not_bss;
1135 uint32_t filtered;
1136 uint32_t bad_chan;
1137 uint32_t beacons;
1138 uint32_t missed_beacons;
1139 uint32_t adc_saturated; /* time in 0.8us */
1140 uint32_t ina_searched; /* time in 0.8us */
1141 uint32_t noise[3];
1142 uint32_t flags;
1143 uint32_t load;
1144 uint32_t fa;
1145 uint32_t rssi[3];
1146 uint32_t energy[3];
1147 } __packed;
1148
1149 struct iwn_rx_ht_phy_stats {
1150 uint32_t bad_plcp;
1151 uint32_t overrun;
1152 uint32_t eoverrun;
1153 uint32_t good_crc32;
1154 uint32_t bad_crc32;
1155 uint32_t bad_mh;
1156 uint32_t good_ampdu_crc32;
1157 uint32_t ampdu;
1158 uint32_t fragment;
1159 uint32_t reserved;
1160 } __packed;
1161
1162 struct iwn_rx_stats {
1163 struct iwn_rx_phy_stats ofdm;
1164 struct iwn_rx_phy_stats cck;
1165 struct iwn_rx_general_stats general;
1166 struct iwn_rx_ht_phy_stats ht;
1167 } __packed;
1168
1169 struct iwn_tx_stats {
1170 uint32_t preamble;
1171 uint32_t rx_detected;
1172 uint32_t bt_defer;
1173 uint32_t bt_kill;
1174 uint32_t short_len;
1175 uint32_t cts_timeout;
1176 uint32_t ack_timeout;
1177 uint32_t exp_ack;
1178 uint32_t ack;
1179 uint32_t msdu;
1180 uint32_t busrt_err1;
1181 uint32_t burst_err2;
1182 uint32_t cts_collision;
1183 uint32_t ack_collision;
1184 uint32_t ba_timeout;
1185 uint32_t ba_resched;
1186 uint32_t query_ampdu;
1187 uint32_t query;
1188 uint32_t query_ampdu_frag;
1189 uint32_t query_mismatch;
1190 uint32_t not_ready;
1191 uint32_t underrun;
1192 uint32_t bt_ht_kill;
1193 uint32_t rx_ba_resp;
1194 uint32_t reserved[2];
1195 } __packed;
1196
1197 struct iwn_general_stats {
1198 uint32_t temp;
1199 uint32_t temp_m;
1200 uint32_t burst_check;
1201 uint32_t burst;
1202 uint32_t reserved1[4];
1203 uint32_t sleep;
1204 uint32_t slot_out;
1205 uint32_t slot_idle;
1206 uint32_t ttl_tstamp;
1207 uint32_t tx_ant_a;
1208 uint32_t tx_ant_b;
1209 uint32_t exec;
1210 uint32_t probe;
1211 uint32_t reserved2[2];
1212 uint32_t rx_enabled;
1213 uint32_t reserved3[3];
1214 } __packed;
1215
1216 struct iwn_stats {
1217 uint32_t flags;
1218 struct iwn_rx_stats rx;
1219 struct iwn_tx_stats tx;
1220 struct iwn_general_stats general;
1221 } __packed;
1222
1223
1224 /* Firmware error dump. */
1225 struct iwn_fw_dump {
1226 uint32_t valid;
1227 uint32_t id;
1228 uint32_t pc;
1229 uint32_t branch_link[2];
1230 uint32_t interrupt_link[2];
1231 uint32_t error_data[2];
1232 uint32_t src_line;
1233 uint32_t tsf;
1234 uint32_t time[2];
1235 } __packed;
1236
1237 /* Firmware image file header. */
1238 struct iwn_firmware_hdr {
1239 uint32_t version;
1240 uint32_t main_textsz;
1241 uint32_t main_datasz;
1242 uint32_t init_textsz;
1243 uint32_t init_datasz;
1244 uint32_t boot_textsz;
1245 } __packed;
1246
1247 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024)
1248 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024)
1249 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024)
1250 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024)
1251 #define IWN_FW_BOOT_TEXT_MAXSZ 1024
1252 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ)
1253 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ
1254
1255 /*
1256 * Offsets into EEPROM.
1257 */
1258 #define IWN_EEPROM_MAC 0x015
1259 #define IWN_EEPROM_RFCFG 0x048
1260 #define IWN4965_EEPROM_DOMAIN 0x060
1261 #define IWN4965_EEPROM_BAND1 0x063
1262 #define IWN5000_EEPROM_REG 0x066
1263 #define IWN5000_EEPROM_CAL 0x067
1264 #define IWN4965_EEPROM_BAND2 0x072
1265 #define IWN4965_EEPROM_BAND3 0x080
1266 #define IWN4965_EEPROM_BAND4 0x08d
1267 #define IWN4965_EEPROM_BAND5 0x099
1268 #define IWN4965_EEPROM_BAND6 0x0a0
1269 #define IWN4965_EEPROM_BAND7 0x0a8
1270 #define IWN4965_EEPROM_MAXPOW 0x0e8
1271 #define IWN4965_EEPROM_VOLTAGE 0x0e9
1272 #define IWN4965_EEPROM_BANDS 0x0ea
1273 /* Indirect offsets. */
1274 #define IWN5000_EEPROM_DOMAIN 0x001
1275 #define IWN5000_EEPROM_BAND1 0x004
1276 #define IWN5000_EEPROM_BAND2 0x013
1277 #define IWN5000_EEPROM_BAND3 0x021
1278 #define IWN5000_EEPROM_BAND4 0x02e
1279 #define IWN5000_EEPROM_BAND5 0x03a
1280 #define IWN5000_EEPROM_BAND6 0x041
1281 #define IWN5000_EEPROM_BAND7 0x049
1282 #define IWN5000_EEPROM_CRYSTAL 0x128
1283 #define IWN5000_EEPROM_TEMP 0x12a
1284 #define IWN5000_EEPROM_VOLT 0x12b
1285
1286 /* Possible flags for IWN_EEPROM_RFCFG. */
1287 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3)
1288 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3)
1289 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3)
1290 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf)
1291 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf)
1292
1293 struct iwn_eeprom_chan {
1294 uint8_t flags;
1295 #define IWN_EEPROM_CHAN_VALID (1 << 0)
1296 #define IWN_EEPROM_CHAN_IBSS (1 << 1)
1297 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3)
1298 #define IWN_EEPROM_CHAN_RADAR (1 << 4)
1299
1300 int8_t maxpwr;
1301 } __packed;
1302
1303 #define IWN_NSAMPLES 3
1304 struct iwn4965_eeprom_chan_samples {
1305 uint8_t num;
1306 struct {
1307 uint8_t temp;
1308 uint8_t gain;
1309 uint8_t power;
1310 int8_t pa_det;
1311 } samples[2][IWN_NSAMPLES];
1312 } __packed;
1313
1314 #define IWN_NBANDS 8
1315 struct iwn4965_eeprom_band {
1316 uint8_t lo; /* low channel number */
1317 uint8_t hi; /* high channel number */
1318 struct iwn4965_eeprom_chan_samples chans[2];
1319 } __packed;
1320
1321 /*
1322 * Offsets of channels descriptions in EEPROM.
1323 */
1324 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = {
1325 IWN4965_EEPROM_BAND1,
1326 IWN4965_EEPROM_BAND2,
1327 IWN4965_EEPROM_BAND3,
1328 IWN4965_EEPROM_BAND4,
1329 IWN4965_EEPROM_BAND5,
1330 IWN4965_EEPROM_BAND6,
1331 IWN4965_EEPROM_BAND7
1332 };
1333
1334 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = {
1335 IWN5000_EEPROM_BAND1,
1336 IWN5000_EEPROM_BAND2,
1337 IWN5000_EEPROM_BAND3,
1338 IWN5000_EEPROM_BAND4,
1339 IWN5000_EEPROM_BAND5,
1340 IWN5000_EEPROM_BAND6,
1341 IWN5000_EEPROM_BAND7
1342 };
1343
1344 #define IWN_CHAN_BANDS_COUNT 7
1345 #define IWN_MAX_CHAN_PER_BAND 14
1346 static const struct iwn_chan_band {
1347 uint8_t nchan;
1348 uint8_t chan[IWN_MAX_CHAN_PER_BAND];
1349 } iwn_bands[] = {
1350 /* 20MHz channels, 2GHz band. */
1351 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } },
1352 /* 20MHz channels, 5GHz band. */
1353 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } },
1354 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } },
1355 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } },
1356 { 6, { 145, 149, 153, 157, 161, 165 } },
1357 /* 40MHz channels (primary channels), 2GHz band. */
1358 { 7, { 1, 2, 3, 4, 5, 6, 7 } },
1359 /* 40MHz channels (primary channels), 5GHz band. */
1360 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } }
1361 };
1362
1363 /* HW rate indices. */
1364 #define IWN_RIDX_CCK1 0
1365 #define IWN_RIDX_OFDM6 4
1366
1367 static const struct iwn_rate {
1368 uint8_t rate;
1369 uint8_t plcp;
1370 uint8_t flags;
1371 } iwn_rates[IWN_RIDX_MAX + 1] = {
1372 { 2, 10, IWN_RFLAG_CCK },
1373 { 4, 20, IWN_RFLAG_CCK },
1374 { 11, 55, IWN_RFLAG_CCK },
1375 { 22, 110, IWN_RFLAG_CCK },
1376 { 12, 0xd, 0 },
1377 { 18, 0xf, 0 },
1378 { 24, 0x5, 0 },
1379 { 36, 0x7, 0 },
1380 { 48, 0x9, 0 },
1381 { 72, 0xb, 0 },
1382 { 96, 0x1, 0 },
1383 { 108, 0x3, 0 },
1384 { 120, 0x3, 0 }
1385 };
1386
1387 #define IWN4965_MAX_PWR_INDEX 107
1388
1389 /*
1390 * RF Tx gain values from highest to lowest power (values obtained from
1391 * the reference driver.)
1392 */
1393 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = {
1394 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c,
1395 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38,
1396 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35,
1397 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31,
1398 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04,
1399 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01,
1400 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1401 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1402 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1403 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1404 };
1405
1406 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = {
1407 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d,
1408 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39,
1409 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35,
1410 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32,
1411 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24,
1412 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16,
1413 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13,
1414 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05,
1415 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01,
1416 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1417 };
1418
1419 /*
1420 * DSP pre-DAC gain values from highest to lowest power (values obtained
1421 * from the reference driver.)
1422 */
1423 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = {
1424 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1425 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1426 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1427 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1428 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1429 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1430 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a,
1431 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f,
1432 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44,
1433 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b
1434 };
1435
1436 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = {
1437 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1438 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1439 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1440 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1441 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1442 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1443 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
1444 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
1445 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
1446 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e
1447 };
1448
1449 /*
1450 * Power saving settings (values obtained from the reference driver.)
1451 */
1452 #define IWN_NDTIMRANGES 3
1453 #define IWN_NPOWERLEVELS 6
1454 static const struct iwn_pmgt {
1455 uint32_t rxtimeout;
1456 uint32_t txtimeout;
1457 uint32_t intval[5];
1458 int skip_dtim;
1459 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = {
1460 /* DTIM <= 2 */
1461 {
1462 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
1463 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */
1464 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */
1465 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */
1466 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */
1467 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */
1468 },
1469 /* 3 <= DTIM <= 10 */
1470 {
1471 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
1472 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */
1473 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */
1474 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */
1475 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */
1476 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */
1477 },
1478 /* DTIM >= 11 */
1479 {
1480 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
1481 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */
1482 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */
1483 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */
1484 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */
1485 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */
1486 }
1487 };
1488
1489 struct iwn_sensitivity_limits {
1490 uint32_t min_ofdm_x1;
1491 uint32_t max_ofdm_x1;
1492 uint32_t min_ofdm_mrc_x1;
1493 uint32_t max_ofdm_mrc_x1;
1494 uint32_t min_ofdm_x4;
1495 uint32_t max_ofdm_x4;
1496 uint32_t min_ofdm_mrc_x4;
1497 uint32_t max_ofdm_mrc_x4;
1498 uint32_t min_cck_x4;
1499 uint32_t max_cck_x4;
1500 uint32_t min_cck_mrc_x4;
1501 uint32_t max_cck_mrc_x4;
1502 uint32_t min_energy_cck;
1503 uint32_t energy_cck;
1504 uint32_t energy_ofdm;
1505 };
1506
1507 /*
1508 * RX sensitivity limits (values obtained from the reference driver.)
1509 */
1510 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = {
1511 105, 140,
1512 170, 210,
1513 85, 120,
1514 170, 210,
1515 125, 200,
1516 200, 400,
1517 97,
1518 100,
1519 100
1520 };
1521
1522 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = {
1523 120, 155,
1524 240, 290,
1525 90, 120,
1526 170, 210,
1527 125, 200,
1528 170, 400,
1529 95,
1530 95,
1531 95
1532 };
1533
1534 /* Map TID to TX scheduler's FIFO. */
1535 static const uint8_t iwn_tid2fifo[] = {
1536 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3
1537 };
1538
1539 /* Firmware errors. */
1540 static const char * const iwn_fw_errmsg[] = {
1541 "OK",
1542 "FAIL",
1543 "BAD_PARAM",
1544 "BAD_CHECKSUM",
1545 "NMI_INTERRUPT_WDG",
1546 "SYSASSERT",
1547 "FATAL_ERROR",
1548 "BAD_COMMAND",
1549 "HW_ERROR_TUNE_LOCK",
1550 "HW_ERROR_TEMPERATURE",
1551 "ILLEGAL_CHAN_FREQ",
1552 "VCC_NOT_STABLE",
1553 "FH_ERROR",
1554 "NMI_INTERRUPT_HOST",
1555 "NMI_INTERRUPT_ACTION_PT",
1556 "NMI_INTERRUPT_UNKNOWN",
1557 "UCODE_VERSION_MISMATCH",
1558 "HW_ERROR_ABS_LOCK",
1559 "HW_ERROR_CAL_LOCK_FAIL",
1560 "NMI_INTERRUPT_INST_ACTION_PT",
1561 "NMI_INTERRUPT_DATA_ACTION_PT",
1562 "NMI_TRM_HW_ER",
1563 "NMI_INTERRUPT_TRM",
1564 "NMI_INTERRUPT_BREAKPOINT"
1565 "DEBUG_0",
1566 "DEBUG_1",
1567 "DEBUG_2",
1568 "DEBUG_3",
1569 "UNKNOWN"
1570 };
1571
1572 /* Find least significant bit that is set. */
1573 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x))
1574
1575 #define IWN_READ(sc, reg) \
1576 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
1577
1578 #define IWN_WRITE(sc, reg, val) \
1579 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
1580
1581 #define IWN_SETBITS(sc, reg, mask) \
1582 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask))
1583
1584 #define IWN_CLRBITS(sc, reg, mask) \
1585 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask))
NetBSD on the FriendlyARM MINI2440