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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / pci / if_jme.c
blob0bca780c0b1752804923c60eb52608ee0f1f91bd
1 /* $NetBSD: if_jme.c,v 1.11 2009/09/27 12:52:59 tsutsui Exp $ */
2
3 /*
4 * Copyright (c) 2008 Manuel Bouyer. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 /*-
28 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
29 * All rights reserved.
30 *
31 * Redistribution and use in source and binary forms, with or without
32 * modification, are permitted provided that the following conditions
33 * are met:
34 * 1. Redistributions of source code must retain the above copyright
35 * notice unmodified, this list of conditions, and the following
36 * disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
40 *
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
51 * SUCH DAMAGE.
52 */
53
54
55 /*
56 * Driver for JMicron Technologies JMC250 (Giganbit) and JMC260 (Fast)
57 * Ethernet Controllers.
58 */
59
60 #include <sys/cdefs.h>
61 __KERNEL_RCSID(0, "$NetBSD: if_jme.c,v 1.11 2009/09/27 12:52:59 tsutsui Exp $");
62
63
64 #include <sys/param.h>
65 #include <sys/systm.h>
66 #include <sys/mbuf.h>
67 #include <sys/protosw.h>
68 #include <sys/socket.h>
69 #include <sys/ioctl.h>
70 #include <sys/errno.h>
71 #include <sys/malloc.h>
72 #include <sys/kernel.h>
73 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */
74 #include <sys/device.h>
75 #include <sys/syslog.h>
76 #include <sys/sysctl.h>
77
78 #include <net/if.h>
79 #if defined(SIOCSIFMEDIA)
80 #include <net/if_media.h>
81 #endif
82 #include <net/if_types.h>
83 #include <net/if_dl.h>
84 #include <net/route.h>
85 #include <net/netisr.h>
86
87 #include "bpfilter.h"
88 #if NBPFILTER > 0
89 #include <net/bpf.h>
90 #include <net/bpfdesc.h>
91 #endif
92
93 #include "rnd.h"
94 #if NRND > 0
95 #include <sys/rnd.h>
96 #endif
97
98 #include <netinet/in.h>
99 #include <netinet/in_systm.h>
100 #include <netinet/ip.h>
101
102 #ifdef INET
103 #include <netinet/in_var.h>
104 #endif
105
106 #include <netinet/tcp.h>
107
108 #include <net/if_ether.h>
109 #include <uvm/uvm_extern.h>
110 #if defined(INET)
111 #include <netinet/if_inarp.h>
112 #endif
113
114 #include <sys/bus.h>
115 #include <sys/intr.h>
116
117 #include <dev/pci/pcireg.h>
118 #include <dev/pci/pcivar.h>
119 #include <dev/pci/pcidevs.h>
120 #include <dev/pci/if_jmereg.h>
121
122 #include <dev/mii/mii.h>
123 #include <dev/mii/miivar.h>
124
125 struct jme_product_desc {
126 u_int32_t jme_product;
127 const char *jme_desc;
128 };
129
130 /* number of entries in transmit and receive rings */
131 #define JME_NBUFS (PAGE_SIZE / sizeof(struct jme_desc))
132
133 #define JME_DESC_INC(x, y) ((x) = ((x) + 1) % (y))
134
135 /* Water mark to kick reclaiming Tx buffers. */
136 #define JME_TX_DESC_HIWAT (JME_NBUFS - (((JME_NBUFS) * 3) / 10))
137
138
139 struct jme_softc {
140 device_t jme_dev; /* base device */
141 bus_space_tag_t jme_bt_mac;
142 bus_space_handle_t jme_bh_mac; /* Mac registers */
143 bus_space_tag_t jme_bt_phy;
144 bus_space_handle_t jme_bh_phy; /* PHY registers */
145 bus_space_tag_t jme_bt_misc;
146 bus_space_handle_t jme_bh_misc; /* Misc registers */
147 bus_dma_tag_t jme_dmatag;
148 bus_dma_segment_t jme_txseg; /* transmit ring seg */
149 bus_dmamap_t jme_txmap; /* transmit ring DMA map */
150 struct jme_desc* jme_txring; /* transmit ring */
151 bus_dmamap_t jme_txmbufm[JME_NBUFS]; /* transmit mbufs DMA map */
152 struct mbuf *jme_txmbuf[JME_NBUFS]; /* mbufs being transmitted */
153 int jme_tx_cons; /* transmit ring consumer */
154 int jme_tx_prod; /* transmit ring producer */
155 int jme_tx_cnt; /* transmit ring active count */
156 bus_dma_segment_t jme_rxseg; /* receive ring seg */
157 bus_dmamap_t jme_rxmap; /* receive ring DMA map */
158 struct jme_desc* jme_rxring; /* receive ring */
159 bus_dmamap_t jme_rxmbufm[JME_NBUFS]; /* receive mbufs DMA map */
160 struct mbuf *jme_rxmbuf[JME_NBUFS]; /* mbufs being received */
161 int jme_rx_cons; /* receive ring consumer */
162 int jme_rx_prod; /* receive ring producer */
163 void* jme_ih; /* our interrupt */
164 struct ethercom jme_ec;
165 struct callout jme_tick_ch; /* tick callout */
166 u_int8_t jme_enaddr[ETHER_ADDR_LEN];/* hardware address */
167 u_int8_t jme_phyaddr; /* address of integrated phy */
168 u_int8_t jme_chip_rev; /* chip revision */
169 u_int8_t jme_rev; /* PCI revision */
170 mii_data_t jme_mii; /* mii bus */
171 u_int32_t jme_flags; /* device features, see below */
172 uint32_t jme_txcsr; /* TX config register */
173 uint32_t jme_rxcsr; /* RX config register */
174 #if NRND > 0
175 rndsource_element_t rnd_source;
176 #endif
177 /* interrupt coalition parameters */
178 struct sysctllog *jme_clog;
179 int jme_intrxto; /* interrupt RX timeout */
180 int jme_intrxct; /* interrupt RX packets counter */
181 int jme_inttxto; /* interrupt TX timeout */
182 int jme_inttxct; /* interrupt TX packets counter */
183 };
184
185 #define JME_FLAG_FPGA 0x0001 /* FPGA version */
186 #define JME_FLAG_GIGA 0x0002 /* giga Ethernet capable */
187
188
189 #define jme_if jme_ec.ec_if
190 #define jme_bpf jme_if.if_bpf
191
192 typedef struct jme_softc jme_softc_t;
193 typedef u_long ioctl_cmd_t;
194
195 static int jme_pci_match(device_t, cfdata_t, void *);
196 static void jme_pci_attach(device_t, device_t, void *);
197 static void jme_intr_rx(jme_softc_t *);
198 static int jme_intr(void *);
199
200 static int jme_ifioctl(struct ifnet *, ioctl_cmd_t, void *);
201 static int jme_mediachange(struct ifnet *);
202 static void jme_ifwatchdog(struct ifnet *);
203 static bool jme_shutdown(device_t, int);
204
205 static void jme_txeof(struct jme_softc *);
206 static void jme_ifstart(struct ifnet *);
207 static void jme_reset(jme_softc_t *);
208 static int jme_ifinit(struct ifnet *);
209 static int jme_init(struct ifnet *, int);
210 static void jme_stop(struct ifnet *, int);
211 // static void jme_restart(void *);
212 static void jme_ticks(void *);
213 static void jme_mac_config(jme_softc_t *);
214 static void jme_set_filter(jme_softc_t *);
215
216 int jme_mii_read(device_t, int, int);
217 void jme_mii_write(device_t, int, int, int);
218 void jme_statchg(device_t);
219
220 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
221 static int jme_eeprom_macaddr(struct jme_softc *);
222
223 #define JME_TIMEOUT 1000
224 #define JME_PHY_TIMEOUT 1000
225 #define JME_EEPROM_TIMEOUT 1000
226
227 static int jme_sysctl_intrxto(SYSCTLFN_PROTO);
228 static int jme_sysctl_intrxct(SYSCTLFN_PROTO);
229 static int jme_sysctl_inttxto(SYSCTLFN_PROTO);
230 static int jme_sysctl_inttxct(SYSCTLFN_PROTO);
231 static int jme_root_num;
232
233
234 CFATTACH_DECL_NEW(jme, sizeof(jme_softc_t),
235 jme_pci_match, jme_pci_attach, NULL, NULL);
236
237 static const struct jme_product_desc jme_products[] = {
238 { PCI_PRODUCT_JMICRON_JMC250,
239 "JMicron JMC250 Gigabit Ethernet Controller" },
240 { PCI_PRODUCT_JMICRON_JMC260,
241 "JMicron JMC260 Gigabit Ethernet Controller" },
242 { 0, NULL },
243 };
244
245 static const struct jme_product_desc *jme_lookup_product(uint32_t);
246
247 static const struct jme_product_desc *
248 jme_lookup_product(uint32_t id)
249 {
250 const struct jme_product_desc *jp;
251
252 for (jp = jme_products ; jp->jme_desc != NULL; jp++)
253 if (PCI_PRODUCT(id) == jp->jme_product)
254 return jp;
255
256 return NULL;
257 }
258
259 static int
260 jme_pci_match(device_t parent, cfdata_t cf, void *aux)
261 {
262 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
263
264 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_JMICRON)
265 return 0;
266
267 if (jme_lookup_product(pa->pa_id) != NULL)
268 return 1;
269
270 return 0;
271 }
272
273 static void
274 jme_pci_attach(device_t parent, device_t self, void *aux)
275 {
276 jme_softc_t *sc = device_private(self);
277 struct pci_attach_args * const pa = (struct pci_attach_args *)aux;
278 const struct jme_product_desc *jp;
279 struct ifnet * const ifp = &sc->jme_if;
280 bus_space_tag_t iot1, iot2, memt;
281 bus_space_handle_t ioh1, ioh2, memh;
282 bus_size_t size, size2;
283 pci_intr_handle_t intrhandle;
284 const char *intrstr;
285 pcireg_t csr;
286 int nsegs, i;
287 const struct sysctlnode *node;
288 int jme_nodenum;
289
290 sc->jme_dev = self;
291 aprint_normal("\n");
292 callout_init(&sc->jme_tick_ch, 0);
293
294 jp = jme_lookup_product(pa->pa_id);
295 if (jp == NULL)
296 panic("jme_pci_attach: impossible");
297
298 if (jp->jme_product == PCI_PRODUCT_JMICRON_JMC250)
299 sc->jme_flags = JME_FLAG_GIGA;
300
301 /*
302 * Map the card space. Try Mem first.
303 */
304 if (pci_mapreg_map(pa, JME_PCI_BAR0,
305 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
306 0, &memt, &memh, NULL, &size) == 0) {
307 sc->jme_bt_mac = memt;
308 sc->jme_bh_mac = memh;
309 sc->jme_bt_phy = memt;
310 if (bus_space_subregion(memt, memh, JME_PHY_EEPROM_BASE_MEMOFF,
311 JME_PHY_EEPROM_SIZE, &sc->jme_bh_phy) != 0) {
312 aprint_error_dev(self, "can't subregion PHY space\n");
313 bus_space_unmap(memt, memh, size);
314 return;
315 }
316 sc->jme_bt_misc = memt;
317 if (bus_space_subregion(memt, memh, JME_MISC_BASE_MEMOFF,
318 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) {
319 aprint_error_dev(self, "can't subregion misc space\n");
320 bus_space_unmap(memt, memh, size);
321 return;
322 }
323 } else {
324 if (pci_mapreg_map(pa, JME_PCI_BAR1, PCI_MAPREG_TYPE_IO,
325 0, &iot1, &ioh1, NULL, &size) != 0) {
326 aprint_error_dev(self, "can't map I/O space 1\n");
327 return;
328 }
329 sc->jme_bt_mac = iot1;
330 sc->jme_bh_mac = ioh1;
331 if (pci_mapreg_map(pa, JME_PCI_BAR2, PCI_MAPREG_TYPE_IO,
332 0, &iot2, &ioh2, NULL, &size2) != 0) {
333 aprint_error_dev(self, "can't map I/O space 2\n");
334 bus_space_unmap(iot1, ioh1, size);
335 return;
336 }
337 sc->jme_bt_phy = iot2;
338 sc->jme_bh_phy = ioh2;
339 sc->jme_bt_misc = iot2;
340 if (bus_space_subregion(iot2, ioh2, JME_MISC_BASE_IOOFF,
341 JME_MISC_SIZE, &sc->jme_bh_misc) != 0) {
342 aprint_error_dev(self, "can't subregion misc space\n");
343 bus_space_unmap(iot1, ioh1, size);
344 bus_space_unmap(iot2, ioh2, size2);
345 return;
346 }
347 }
348
349 if (pci_dma64_available(pa))
350 sc->jme_dmatag = pa->pa_dmat64;
351 else
352 sc->jme_dmatag = pa->pa_dmat;
353
354 /* Enable the device. */
355 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
356 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
357 csr | PCI_COMMAND_MASTER_ENABLE);
358
359 aprint_normal_dev(self, "%s\n", jp->jme_desc);
360
361 sc->jme_rev = PCI_REVISION(pa->pa_class);
362
363 csr = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_CHIPMODE);
364 if (((csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
365 CHIPMODE_NOT_FPGA)
366 sc->jme_flags |= JME_FLAG_FPGA;
367 sc->jme_chip_rev = (csr & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT;
368 aprint_verbose_dev(self, "PCI device revision : 0x%x, Chip revision: "
369 "0x%x", sc->jme_rev, sc->jme_chip_rev);
370 if (sc->jme_flags & JME_FLAG_FPGA)
371 aprint_verbose(" FPGA revision: 0x%x",
372 (csr & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT);
373 aprint_verbose("\n");
374
375 /*
376 * Save PHY address.
377 * Integrated JR0211 has fixed PHY address whereas FPGA version
378 * requires PHY probing to get correct PHY address.
379 */
380 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) {
381 sc->jme_phyaddr =
382 bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc,
383 JME_GPREG0) & GPREG0_PHY_ADDR_MASK;
384 } else
385 sc->jme_phyaddr = 0;
386
387
388 jme_reset(sc);
389
390 /* read mac addr */
391 if (jme_eeprom_macaddr(sc)) {
392 aprint_error_dev(self, "error reading Ethernet address\n");
393 /* return; */
394 }
395 aprint_normal_dev(self, "Ethernet address %s\n",
396 ether_sprintf(sc->jme_enaddr));
397
398 /* Map and establish interrupts */
399 if (pci_intr_map(pa, &intrhandle)) {
400 aprint_error_dev(self, "couldn't map interrupt\n");
401 return;
402 }
403 intrstr = pci_intr_string(pa->pa_pc, intrhandle);
404 sc->jme_if.if_softc = sc;
405 sc->jme_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET,
406 jme_intr, sc);
407 if (sc->jme_ih == NULL) {
408 aprint_error_dev(self, "couldn't establish interrupt");
409 if (intrstr != NULL)
410 aprint_error(" at %s", intrstr);
411 aprint_error("\n");
412 return;
413 }
414 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
415
416 /* allocate and map DMA-safe memory for transmit ring */
417 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE,
418 &sc->jme_txseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 ||
419 bus_dmamem_map(sc->jme_dmatag, &sc->jme_txseg,
420 nsegs, PAGE_SIZE, (void **)&sc->jme_txring,
421 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 ||
422 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0,
423 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_txmap) != 0 ||
424 bus_dmamap_load(sc->jme_dmatag, sc->jme_txmap, sc->jme_txring,
425 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) {
426 aprint_error_dev(self, "can't allocate DMA memory TX ring\n");
427 return;
428 }
429 /* allocate and map DMA-safe memory for receive ring */
430 if (bus_dmamem_alloc(sc->jme_dmatag, PAGE_SIZE, 0, PAGE_SIZE,
431 &sc->jme_rxseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0 ||
432 bus_dmamem_map(sc->jme_dmatag, &sc->jme_rxseg,
433 nsegs, PAGE_SIZE, (void **)&sc->jme_rxring,
434 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0 ||
435 bus_dmamap_create(sc->jme_dmatag, PAGE_SIZE, 1, PAGE_SIZE, 0,
436 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->jme_rxmap) != 0 ||
437 bus_dmamap_load(sc->jme_dmatag, sc->jme_rxmap, sc->jme_rxring,
438 PAGE_SIZE, NULL, BUS_DMA_NOWAIT) != 0) {
439 aprint_error_dev(self, "can't allocate DMA memory RX ring\n");
440 return;
441 }
442 for (i = 0; i < JME_NBUFS; i++) {
443 sc->jme_txmbuf[i] = sc->jme_rxmbuf[i] = NULL;
444 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_TX_LEN,
445 JME_NBUFS, JME_MAX_TX_LEN, 0, BUS_DMA_NOWAIT,
446 &sc->jme_txmbufm[i]) != 0) {
447 aprint_error_dev(self, "can't allocate DMA TX map\n");
448 return;
449 }
450 if (bus_dmamap_create(sc->jme_dmatag, JME_MAX_RX_LEN,
451 1, JME_MAX_RX_LEN, 0, BUS_DMA_NOWAIT,
452 &sc->jme_rxmbufm[i]) != 0) {
453 aprint_error_dev(self, "can't allocate DMA RX map\n");
454 return;
455 }
456 }
457 /*
458 * Initialize our media structures and probe the MII.
459 *
460 * Note that we don't care about the media instance. We
461 * are expecting to have multiple PHYs on the 10/100 cards,
462 * and on those cards we exclude the internal PHY from providing
463 * 10baseT. By ignoring the instance, it allows us to not have
464 * to specify it on the command line when switching media.
465 */
466 sc->jme_mii.mii_ifp = ifp;
467 sc->jme_mii.mii_readreg = jme_mii_read;
468 sc->jme_mii.mii_writereg = jme_mii_write;
469 sc->jme_mii.mii_statchg = jme_statchg;
470 sc->jme_ec.ec_mii = &sc->jme_mii;
471 ifmedia_init(&sc->jme_mii.mii_media, IFM_IMASK, jme_mediachange,
472 ether_mediastatus);
473 mii_attach(self, &sc->jme_mii, 0xffffffff, MII_PHY_ANY,
474 MII_OFFSET_ANY, 0);
475 if (LIST_FIRST(&sc->jme_mii.mii_phys) == NULL) {
476 ifmedia_add(&sc->jme_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
477 ifmedia_set(&sc->jme_mii.mii_media, IFM_ETHER|IFM_NONE);
478 } else
479 ifmedia_set(&sc->jme_mii.mii_media, IFM_ETHER|IFM_AUTO);
480
481 /*
482 * We can support 802.1Q VLAN-sized frames.
483 */
484 sc->jme_ec.ec_capabilities |=
485 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
486
487 if (sc->jme_flags & JME_FLAG_GIGA)
488 sc->jme_ec.ec_capabilities |= ETHERCAP_JUMBO_MTU;
489
490
491 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
492 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST;
493 ifp->if_ioctl = jme_ifioctl;
494 ifp->if_start = jme_ifstart;
495 ifp->if_watchdog = jme_ifwatchdog;
496 ifp->if_init = jme_ifinit;
497 ifp->if_stop = jme_stop;
498 ifp->if_timer = 0;
499 ifp->if_capabilities |=
500 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
501 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
502 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
503 IFCAP_CSUM_TCPv6_Tx | /* IFCAP_CSUM_TCPv6_Rx | hardware bug */
504 IFCAP_CSUM_UDPv6_Tx | /* IFCAP_CSUM_UDPv6_Rx | hardware bug */
505 IFCAP_TSOv4 | IFCAP_TSOv6;
506 IFQ_SET_READY(&ifp->if_snd);
507 if_attach(ifp);
508 ether_ifattach(&(sc)->jme_if, (sc)->jme_enaddr);
509
510 /*
511 * Add shutdown hook so that DMA is disabled prior to reboot.
512 */
513 if (pmf_device_register1(self, NULL, NULL, jme_shutdown))
514 pmf_class_network_register(self, ifp);
515 else
516 aprint_error_dev(self, "couldn't establish power handler\n");
517
518 #if NRND > 0
519 rnd_attach_source(&sc->rnd_source, device_xname(self),
520 RND_TYPE_NET, 0);
521 #endif
522 sc->jme_intrxto = PCCRX_COAL_TO_DEFAULT;
523 sc->jme_intrxct = PCCRX_COAL_PKT_DEFAULT;
524 sc->jme_inttxto = PCCTX_COAL_TO_DEFAULT;
525 sc->jme_inttxct = PCCTX_COAL_PKT_DEFAULT;
526 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node,
527 0, CTLTYPE_NODE, device_xname(sc->jme_dev),
528 SYSCTL_DESCR("jme per-controller controls"),
529 NULL, 0, NULL, 0, CTL_HW, jme_root_num, CTL_CREATE,
530 CTL_EOL) != 0) {
531 aprint_normal_dev(sc->jme_dev, "couldn't create sysctl node\n");
532 return;
533 }
534 jme_nodenum = node->sysctl_num;
535
536 /* interrupt moderation sysctls */
537 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node,
538 CTLFLAG_READWRITE,
539 CTLTYPE_INT, "int_rxto",
540 SYSCTL_DESCR("jme RX interrupt moderation timer"),
541 jme_sysctl_intrxto, 0, sc,
542 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE,
543 CTL_EOL) != 0) {
544 aprint_normal_dev(sc->jme_dev,
545 "couldn't create int_rxto sysctl node\n");
546 }
547 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node,
548 CTLFLAG_READWRITE,
549 CTLTYPE_INT, "int_rxct",
550 SYSCTL_DESCR("jme RX interrupt moderation packet counter"),
551 jme_sysctl_intrxct, 0, sc,
552 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE,
553 CTL_EOL) != 0) {
554 aprint_normal_dev(sc->jme_dev,
555 "couldn't create int_rxct sysctl node\n");
556 }
557 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node,
558 CTLFLAG_READWRITE,
559 CTLTYPE_INT, "int_txto",
560 SYSCTL_DESCR("jme TX interrupt moderation timer"),
561 jme_sysctl_inttxto, 0, sc,
562 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE,
563 CTL_EOL) != 0) {
564 aprint_normal_dev(sc->jme_dev,
565 "couldn't create int_txto sysctl node\n");
566 }
567 if (sysctl_createv(&sc->jme_clog, 0, NULL, &node,
568 CTLFLAG_READWRITE,
569 CTLTYPE_INT, "int_txct",
570 SYSCTL_DESCR("jme TX interrupt moderation packet counter"),
571 jme_sysctl_inttxct, 0, sc,
572 0, CTL_HW, jme_root_num, jme_nodenum, CTL_CREATE,
573 CTL_EOL) != 0) {
574 aprint_normal_dev(sc->jme_dev,
575 "couldn't create int_txct sysctl node\n");
576 }
577 }
578
579 static void
580 jme_stop_rx(jme_softc_t *sc)
581 {
582 uint32_t reg;
583 int i;
584
585 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR);
586 if ((reg & RXCSR_RX_ENB) == 0)
587 return;
588 reg &= ~RXCSR_RX_ENB;
589 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, reg);
590 for (i = JME_TIMEOUT / 10; i > 0; i--) {
591 DELAY(10);
592 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac,
593 JME_RXCSR) & RXCSR_RX_ENB) == 0)
594 break;
595 }
596 if (i == 0)
597 aprint_error_dev(sc->jme_dev, "stopping recevier timeout!\n");
598
599 }
600
601 static void
602 jme_stop_tx(jme_softc_t *sc)
603 {
604 uint32_t reg;
605 int i;
606
607 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR);
608 if ((reg & TXCSR_TX_ENB) == 0)
609 return;
610 reg &= ~TXCSR_TX_ENB;
611 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, reg);
612 for (i = JME_TIMEOUT / 10; i > 0; i--) {
613 DELAY(10);
614 if ((bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac,
615 JME_TXCSR) & TXCSR_TX_ENB) == 0)
616 break;
617 }
618 if (i == 0)
619 aprint_error_dev(sc->jme_dev,
620 "stopping transmitter timeout!\n");
621 }
622
623 static void
624 jme_reset(jme_softc_t *sc)
625 {
626 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, GHC_RESET);
627 DELAY(10);
628 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, 0);
629 }
630
631 static bool
632 jme_shutdown(device_t self, int howto)
633 {
634 jme_softc_t *sc;
635 struct ifnet *ifp;
636
637 sc = device_private(self);
638 ifp = &sc->jme_if;
639 jme_stop(ifp, 1);
640
641 return true;
642 }
643
644 static void
645 jme_stop(struct ifnet *ifp, int disable)
646 {
647 jme_softc_t *sc = ifp->if_softc;
648 int i;
649 /* Stop receiver, transmitter. */
650 jme_stop_rx(sc);
651 jme_stop_tx(sc);
652 /* free receive mbufs */
653 for (i = 0; i < JME_NBUFS; i++) {
654 if (sc->jme_rxmbuf[i]) {
655 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]);
656 m_freem(sc->jme_rxmbuf[i]);
657 }
658 sc->jme_rxmbuf[i] = NULL;
659 }
660 /* process completed transmits */
661 jme_txeof(sc);
662 /* free abort pending transmits */
663 for (i = 0; i < JME_NBUFS; i++) {
664 if (sc->jme_txmbuf[i]) {
665 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[i]);
666 m_freem(sc->jme_txmbuf[i]);
667 sc->jme_txmbuf[i] = NULL;
668 }
669 }
670 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
671 ifp->if_timer = 0;
672 }
673
674 #if 0
675 static void
676 jme_restart(void *v)
677 {
678
679 jme_init(v);
680 }
681 #endif
682
683 static int
684 jme_add_rxbuf(jme_softc_t *sc, struct mbuf *m)
685 {
686 int error;
687 bus_dmamap_t map;
688 int i = sc->jme_rx_prod;
689
690 if (sc->jme_rxmbuf[i] != NULL) {
691 aprint_error_dev(sc->jme_dev,
692 "mbuf already here: rxprod %d rxcons %d\n",
693 sc->jme_rx_prod, sc->jme_rx_cons);
694 if (m)
695 m_freem(m);
696 return EINVAL;
697 }
698
699 if (m == NULL) {
700 sc->jme_rxmbuf[i] = NULL;
701 MGETHDR(m, M_DONTWAIT, MT_DATA);
702 if (m == NULL)
703 return (ENOBUFS);
704 MCLGET(m, M_DONTWAIT);
705 if ((m->m_flags & M_EXT) == 0) {
706 m_freem(m);
707 return (ENOBUFS);
708 }
709 }
710 map = sc->jme_rxmbufm[i];
711 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
712 error = bus_dmamap_load_mbuf(sc->jme_dmatag, map, m,
713 BUS_DMA_READ|BUS_DMA_NOWAIT);
714 if (error) {
715 sc->jme_rxmbuf[i] = NULL;
716 aprint_error_dev(sc->jme_dev,
717 "unable to load rx DMA map %d, error = %d\n",
718 i, error);
719 m_freem(m);
720 return (error);
721 }
722 bus_dmamap_sync(sc->jme_dmatag, map, 0, map->dm_mapsize,
723 BUS_DMASYNC_PREREAD);
724
725 sc->jme_rxmbuf[i] = m;
726
727 sc->jme_rxring[i].buflen = htole32(map->dm_segs[0].ds_len);
728 sc->jme_rxring[i].addr_lo =
729 htole32(JME_ADDR_LO(map->dm_segs[0].ds_addr));
730 sc->jme_rxring[i].addr_hi =
731 htole32(JME_ADDR_HI(map->dm_segs[0].ds_addr));
732 sc->jme_rxring[i].flags =
733 htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
734 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap,
735 i * sizeof(struct jme_desc), sizeof(struct jme_desc),
736 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
737 JME_DESC_INC(sc->jme_rx_prod, JME_NBUFS);
738 return (0);
739 }
740
741 static int
742 jme_ifinit(struct ifnet *ifp)
743 {
744 return jme_init(ifp, 1);
745 }
746
747 static int
748 jme_init(struct ifnet *ifp, int do_ifinit)
749 {
750 jme_softc_t *sc = ifp->if_softc;
751 int i, s;
752 uint8_t eaddr[ETHER_ADDR_LEN];
753 uint32_t reg;
754
755 s = splnet();
756 /* cancel any pending IO */
757 jme_stop(ifp, 1);
758 jme_reset(sc);
759 if ((sc->jme_if.if_flags & IFF_UP) == 0) {
760 splx(s);
761 return 0;
762 }
763 /* allocate receive ring */
764 sc->jme_rx_prod = 0;
765 for (i = 0; i < JME_NBUFS; i++) {
766 if (jme_add_rxbuf(sc, NULL) < 0) {
767 aprint_error_dev(sc->jme_dev,
768 "can't allocate rx mbuf\n");
769 for (i--; i >= 0; i--) {
770 bus_dmamap_unload(sc->jme_dmatag,
771 sc->jme_rxmbufm[i]);
772 m_freem(sc->jme_rxmbuf[i]);
773 sc->jme_rxmbuf[i] = NULL;
774 }
775 splx(s);
776 return ENOMEM;
777 }
778 }
779 /* init TX ring */
780 memset(sc->jme_txring, 0, JME_NBUFS * sizeof(struct jme_desc));
781 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap,
782 0, JME_NBUFS * sizeof(struct jme_desc),
783 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
784 for (i = 0; i < JME_NBUFS; i++)
785 sc->jme_txmbuf[i] = NULL;
786 sc->jme_tx_cons = sc->jme_tx_prod = sc->jme_tx_cnt = 0;
787
788 /* Reprogram the station address. */
789 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN);
790 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0,
791 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
792 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
793 JME_PAR1, eaddr[5] << 8 | eaddr[4]);
794
795 /*
796 * Configure Tx queue.
797 * Tx priority queue weight value : 0
798 * Tx FIFO threshold for processing next packet : 16QW
799 * Maximum Tx DMA length : 512
800 * Allow Tx DMA burst.
801 */
802 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
803 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
804 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
805 sc->jme_txcsr |= TXCSR_DMA_SIZE_512;
806 sc->jme_txcsr |= TXCSR_DMA_BURST;
807 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
808 JME_TXCSR, sc->jme_txcsr);
809
810 /* Set Tx descriptor counter. */
811 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
812 JME_TXQDC, JME_NBUFS);
813
814 /* Set Tx ring address to the hardware. */
815 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI,
816 JME_ADDR_HI(sc->jme_txmap->dm_segs[0].ds_addr));
817 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO,
818 JME_ADDR_LO(sc->jme_txmap->dm_segs[0].ds_addr));
819
820 /* Configure TxMAC parameters. */
821 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC,
822 TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB |
823 TXMAC_THRESH_1_PKT | TXMAC_CRC_ENB | TXMAC_PAD_ENB);
824
825 /*
826 * Configure Rx queue.
827 * FIFO full threshold for transmitting Tx pause packet : 128T
828 * FIFO threshold for processing next packet : 128QW
829 * Rx queue 0 select
830 * Max Rx DMA length : 128
831 * Rx descriptor retry : 32
832 * Rx descriptor retry time gap : 256ns
833 * Don't receive runt/bad frame.
834 */
835 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
836 /*
837 * Since Rx FIFO size is 4K bytes, receiving frames larger
838 * than 4K bytes will suffer from Rx FIFO overruns. So
839 * decrease FIFO threshold to reduce the FIFO overruns for
840 * frames larger than 4000 bytes.
841 * For best performance of standard MTU sized frames use
842 * maximum allowable FIFO threshold, 128QW.
843 */
844 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
845 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE)
846 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
847 else
848 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
849 sc->jme_rxcsr |= RXCSR_DMA_SIZE_128 | RXCSR_RXQ_N_SEL(RXCSR_RXQ0);
850 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
851 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
852 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
853 JME_RXCSR, sc->jme_rxcsr);
854
855 /* Set Rx descriptor counter. */
856 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
857 JME_RXQDC, JME_NBUFS);
858
859 /* Set Rx ring address to the hardware. */
860 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI,
861 JME_ADDR_HI(sc->jme_rxmap->dm_segs[0].ds_addr));
862 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO,
863 JME_ADDR_LO(sc->jme_rxmap->dm_segs[0].ds_addr));
864
865 /* Clear receive filter. */
866 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, 0);
867 /* Set up the receive filter. */
868 jme_set_filter(sc);
869
870 /*
871 * Disable all WOL bits as WOL can interfere normal Rx
872 * operation. Also clear WOL detection status bits.
873 */
874 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS);
875 reg &= ~PMCS_WOL_ENB_MASK;
876 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS, reg);
877
878 reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC);
879 /*
880 * Pad 10bytes right before received frame. This will greatly
881 * help Rx performance on strict-alignment architectures as
882 * it does not need to copy the frame to align the payload.
883 */
884 reg |= RXMAC_PAD_10BYTES;
885 if ((ifp->if_capenable &
886 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx|
887 IFCAP_CSUM_TCPv6_Rx|IFCAP_CSUM_UDPv6_Rx)) != 0)
888 reg |= RXMAC_CSUM_ENB;
889 reg |= RXMAC_VLAN_ENB; /* enable hardware vlan */
890 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, reg);
891
892 /* Configure general purpose reg0 */
893 reg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0);
894 reg &= ~GPREG0_PCC_UNIT_MASK;
895 /* Set PCC timer resolution to micro-seconds unit. */
896 reg |= GPREG0_PCC_UNIT_US;
897 /*
898 * Disable all shadow register posting as we have to read
899 * JME_INTR_STATUS register in jme_int_task. Also it seems
900 * that it's hard to synchronize interrupt status between
901 * hardware and software with shadow posting due to
902 * requirements of bus_dmamap_sync(9).
903 */
904 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
905 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
906 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
907 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
908 /* Disable posting of DW0. */
909 reg &= ~GPREG0_POST_DW0_ENB;
910 /* Clear PME message. */
911 reg &= ~GPREG0_PME_ENB;
912 /* Set PHY address. */
913 reg &= ~GPREG0_PHY_ADDR_MASK;
914 reg |= sc->jme_phyaddr;
915 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0, reg);
916
917 /* Configure Tx queue 0 packet completion coalescing. */
918 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK;
919 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK;
920 reg |= PCCTX_COAL_TXQ0;
921 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg);
922
923 /* Configure Rx queue 0 packet completion coalescing. */
924 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK;
925 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK;
926 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg);
927
928 /* Disable Timers */
929 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TMCSR, 0);
930 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER1, 0);
931 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_TIMER2, 0);
932
933 /* Configure retry transmit period, retry limit value. */
934 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD,
935 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
936 TXTRHD_RT_PERIOD_MASK) |
937 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
938 TXTRHD_RT_LIMIT_SHIFT));
939
940 /* Disable RSS. */
941 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc,
942 JME_RSSC, RSSC_DIS_RSS);
943
944 /* Initialize the interrupt mask. */
945 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc,
946 JME_INTR_MASK_SET, JME_INTRS_ENABLE);
947 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc,
948 JME_INTR_STATUS, 0xFFFFFFFF);
949
950 /* set media, if not already handling a media change */
951 if (do_ifinit) {
952 int error;
953 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO)
954 error = 0;
955 else if (error != 0) {
956 aprint_error_dev(sc->jme_dev, "could not set media\n");
957 return error;
958 }
959 }
960
961 /* Program MAC with resolved speed/duplex/flow-control. */
962 jme_mac_config(sc);
963
964 /* Start receiver/transmitter. */
965 sc->jme_rx_cons = 0;
966 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR,
967 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START);
968 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR,
969 sc->jme_txcsr | TXCSR_TX_ENB);
970
971 /* start ticks calls */
972 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc);
973 sc->jme_if.if_flags |= IFF_RUNNING;
974 sc->jme_if.if_flags &= ~IFF_OACTIVE;
975 splx(s);
976 return 0;
977 }
978
979
980 int
981 jme_mii_read(device_t self, int phy, int reg)
982 {
983 struct jme_softc *sc = device_private(self);
984 int val, i;
985
986 /* For FPGA version, PHY address 0 should be ignored. */
987 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
988 if (phy == 0)
989 return (0);
990 } else {
991 if (sc->jme_phyaddr != phy)
992 return (0);
993 }
994
995 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI,
996 SMI_OP_READ | SMI_OP_EXECUTE |
997 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
998 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) {
999 delay(10);
1000 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac,
1001 JME_SMI)) & SMI_OP_EXECUTE) == 0)
1002 break;
1003 }
1004
1005 if (i == 0) {
1006 aprint_error_dev(sc->jme_dev, "phy read timeout : %d\n", reg);
1007 return (0);
1008 }
1009
1010 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
1011 }
1012
1013 void
1014 jme_mii_write(device_t self, int phy, int reg, int val)
1015 {
1016 struct jme_softc *sc = device_private(self);
1017 int i;
1018
1019 /* For FPGA version, PHY address 0 should be ignored. */
1020 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
1021 if (phy == 0)
1022 return;
1023 } else {
1024 if (sc->jme_phyaddr != phy)
1025 return;
1026 }
1027
1028 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_SMI,
1029 SMI_OP_WRITE | SMI_OP_EXECUTE |
1030 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
1031 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
1032 for (i = JME_PHY_TIMEOUT / 10; i > 0; i--) {
1033 delay(10);
1034 if (((val = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac,
1035 JME_SMI)) & SMI_OP_EXECUTE) == 0)
1036 break;
1037 }
1038
1039 if (i == 0)
1040 aprint_error_dev(sc->jme_dev, "phy write timeout : %d\n", reg);
1041
1042 return;
1043 }
1044
1045 void
1046 jme_statchg(device_t self)
1047 {
1048 jme_softc_t *sc = device_private(self);
1049 struct ifnet *ifp = &sc->jme_if;
1050 if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == (IFF_UP|IFF_RUNNING))
1051 jme_init(ifp, 0);
1052 }
1053
1054 static void
1055 jme_intr_rx(jme_softc_t *sc) {
1056 struct mbuf *m, *mhead;
1057 struct ifnet *ifp = &sc->jme_if;
1058 uint32_t flags, buflen;
1059 int i, ipackets, nsegs, seg, error;
1060 struct jme_desc *desc;
1061
1062 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmap, 0,
1063 sizeof(struct jme_desc) * JME_NBUFS,
1064 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1065 #ifdef JMEDEBUG_RX
1066 printf("rxintr sc->jme_rx_cons %d flags 0x%x\n",
1067 sc->jme_rx_cons, le32toh(sc->jme_rxring[sc->jme_rx_cons].flags));
1068 #endif
1069 ipackets = 0;
1070 while((le32toh(sc->jme_rxring[ sc->jme_rx_cons].flags) & JME_RD_OWN)
1071 == 0) {
1072 i = sc->jme_rx_cons;
1073 desc = &sc->jme_rxring[i];
1074 #ifdef JMEDEBUG_RX
1075 printf("rxintr i %d flags 0x%x buflen 0x%x\n",
1076 i, le32toh(desc->flags), le32toh(desc->buflen));
1077 #endif
1078 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
1079 break;
1080 bus_dmamap_sync(sc->jme_dmatag, sc->jme_rxmbufm[i], 0,
1081 sc->jme_rxmbufm[i]->dm_mapsize, BUS_DMASYNC_POSTREAD);
1082 bus_dmamap_unload(sc->jme_dmatag, sc->jme_rxmbufm[i]);
1083
1084 buflen = le32toh(desc->buflen);
1085 nsegs = JME_RX_NSEGS(buflen);
1086 flags = le32toh(desc->flags);
1087 if ((buflen & JME_RX_ERR_STAT) != 0 ||
1088 JME_RX_BYTES(buflen) < sizeof(struct ether_header) ||
1089 JME_RX_BYTES(buflen) >
1090 (ifp->if_mtu + ETHER_HDR_LEN + JME_RX_PAD_BYTES)) {
1091 #ifdef JMEDEBUG_RX
1092 printf("rx error flags 0x%x buflen 0x%x\n",
1093 flags, buflen);
1094 #endif
1095 ifp->if_ierrors++;
1096 /* reuse the mbufs */
1097 for (seg = 0; seg < nsegs; seg++) {
1098 m = sc->jme_rxmbuf[i];
1099 sc->jme_rxmbuf[i] = NULL;
1100 if ((error = jme_add_rxbuf(sc, m)) != 0)
1101 aprint_error_dev(sc->jme_dev,
1102 "can't reuse mbuf: %d\n", error);
1103 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS);
1104 i = sc->jme_rx_cons;
1105 }
1106 continue;
1107 }
1108 /* receive this packet */
1109 mhead = m = sc->jme_rxmbuf[i];
1110 sc->jme_rxmbuf[i] = NULL;
1111 /* add a new buffer to chain */
1112 if (jme_add_rxbuf(sc, NULL) == ENOBUFS) {
1113 for (seg = 0; seg < nsegs; seg++) {
1114 m = sc->jme_rxmbuf[i];
1115 sc->jme_rxmbuf[i] = NULL;
1116 if ((error = jme_add_rxbuf(sc, m)) != 0)
1117 aprint_error_dev(sc->jme_dev,
1118 "can't reuse mbuf: %d\n", error);
1119 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS);
1120 i = sc->jme_rx_cons;
1121 }
1122 ifp->if_ierrors++;
1123 continue;
1124 }
1125
1126 /* build mbuf chain: head, then remaining segments */
1127 m->m_pkthdr.rcvif = ifp;
1128 m->m_pkthdr.len = JME_RX_BYTES(buflen) - JME_RX_PAD_BYTES;
1129 m->m_len = (nsegs > 1) ? (MCLBYTES - JME_RX_PAD_BYTES) :
1130 m->m_pkthdr.len;
1131 m->m_data = m->m_ext.ext_buf + JME_RX_PAD_BYTES;
1132 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS);
1133 for (seg = 1; seg < nsegs; seg++) {
1134 i = sc->jme_rx_cons;
1135 m = sc->jme_rxmbuf[i];
1136 sc->jme_rxmbuf[i] = NULL;
1137 (void)jme_add_rxbuf(sc, NULL);
1138 m->m_flags &= ~M_PKTHDR;
1139 m_cat(mhead, m);
1140 JME_DESC_INC(sc->jme_rx_cons, JME_NBUFS);
1141 }
1142 /* and adjust last mbuf's size */
1143 if (nsegs > 1) {
1144 m->m_len =
1145 JME_RX_BYTES(buflen) - (MCLBYTES * (nsegs - 1));
1146 }
1147 ifp->if_ipackets++;
1148 ipackets++;
1149 #if NBPFILTER > 0
1150 if (ifp->if_bpf)
1151 bpf_mtap(ifp->if_bpf, mhead);
1152 #endif /* NBPFILTER > 0 */
1153
1154 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) &&
1155 (flags & JME_RD_IPV4)) {
1156 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1157 if (!(flags & JME_RD_IPCSUM))
1158 mhead->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
1159 }
1160 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) &&
1161 (flags & JME_RD_TCPV4) == JME_RD_TCPV4) {
1162 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1163 if (!(flags & JME_RD_TCPCSUM))
1164 mhead->m_pkthdr.csum_flags |=
1165 M_CSUM_TCP_UDP_BAD;
1166 }
1167 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) &&
1168 (flags & JME_RD_UDPV4) == JME_RD_UDPV4) {
1169 mhead->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1170 if (!(flags & JME_RD_UDPCSUM))
1171 mhead->m_pkthdr.csum_flags |=
1172 M_CSUM_TCP_UDP_BAD;
1173 }
1174 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) &&
1175 (flags & JME_RD_TCPV6) == JME_RD_TCPV6) {
1176 mhead->m_pkthdr.csum_flags |= M_CSUM_TCPv6;
1177 if (!(flags & JME_RD_TCPCSUM))
1178 mhead->m_pkthdr.csum_flags |=
1179 M_CSUM_TCP_UDP_BAD;
1180 }
1181 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) &&
1182 (flags & JME_RD_UDPV6) == JME_RD_UDPV6) {
1183 m->m_pkthdr.csum_flags |= M_CSUM_UDPv6;
1184 if (!(flags & JME_RD_UDPCSUM))
1185 mhead->m_pkthdr.csum_flags |=
1186 M_CSUM_TCP_UDP_BAD;
1187 }
1188 if (flags & JME_RD_VLAN_TAG) {
1189 /* pass to vlan_input() */
1190 VLAN_INPUT_TAG(ifp, mhead,
1191 (flags & JME_RD_VLAN_MASK), continue);
1192 }
1193 (*ifp->if_input)(ifp, mhead);
1194 }
1195 #if NRND > 0
1196 if (ipackets && RND_ENABLED(&sc->rnd_source))
1197 rnd_add_uint32(&sc->rnd_source, ipackets);
1198 #endif /* NRND > 0 */
1199
1200 }
1201
1202 static int
1203 jme_intr(void *v)
1204 {
1205 jme_softc_t *sc = v;
1206 uint32_t istatus;
1207
1208 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc,
1209 JME_INTR_STATUS);
1210 if (istatus == 0 || istatus == 0xFFFFFFFF)
1211 return 0;
1212 /* Disable interrupts. */
1213 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc,
1214 JME_INTR_MASK_CLR, 0xFFFFFFFF);
1215 again:
1216 /* and update istatus */
1217 istatus = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc,
1218 JME_INTR_STATUS);
1219 if ((istatus & JME_INTRS_CHECK) == 0)
1220 goto done;
1221 /* Reset PCC counter/timer and Ack interrupts. */
1222 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0)
1223 istatus |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1224 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0)
1225 istatus |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP;
1226 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc,
1227 JME_INTR_STATUS, istatus);
1228
1229 if ((sc->jme_if.if_flags & IFF_RUNNING) == 0)
1230 goto done;
1231 #ifdef JMEDEBUG_RX
1232 printf("jme_intr 0x%x RXCS 0x%x RXDBA 0x%x 0x%x RXQDC 0x%x RXNDA 0x%x RXMCS 0x%x\n", istatus,
1233 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR),
1234 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_LO),
1235 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXDBA_HI),
1236 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXQDC),
1237 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXNDA),
1238 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC));
1239 printf("jme_intr RXUMA 0x%x 0x%x RXMCHT 0x%x 0x%x GHC 0x%x\n",
1240 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR0),
1241 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PAR1),
1242 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0),
1243 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1),
1244 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC));
1245 #endif
1246 if ((istatus & (INTR_RXQ_COMP | INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0)
1247 jme_intr_rx(sc);
1248 if ((istatus & INTR_RXQ_DESC_EMPTY) != 0) {
1249 /*
1250 * Notify hardware availability of new Rx
1251 * buffers.
1252 * Reading RXCSR takes very long time under
1253 * heavy load so cache RXCSR value and writes
1254 * the ORed value with the kick command to
1255 * the RXCSR. This saves one register access
1256 * cycle.
1257 */
1258 sc->jme_rx_cons = 0;
1259 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
1260 JME_RXCSR,
1261 sc->jme_rxcsr | RXCSR_RX_ENB | RXCSR_RXQ_START);
1262 }
1263 if ((istatus & (INTR_TXQ_COMP | INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0)
1264 jme_ifstart(&sc->jme_if);
1265
1266 goto again;
1267
1268 done:
1269 /* enable interrupts. */
1270 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc,
1271 JME_INTR_MASK_SET, JME_INTRS_ENABLE);
1272 return 1;
1273 }
1274
1275
1276 static int
1277 jme_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data)
1278 {
1279 struct jme_softc *sc = ifp->if_softc;
1280 int s, error;
1281 struct ifreq *ifr;
1282 struct ifcapreq *ifcr;
1283
1284 s = splnet();
1285 /*
1286 * we can't support at the same time jumbo frames and
1287 * TX checksums offload/TSO
1288 */
1289 switch(cmd) {
1290 case SIOCSIFMTU:
1291 ifr = data;
1292 if (ifr->ifr_mtu > JME_TX_FIFO_SIZE &&
1293 (ifp->if_capenable & (
1294 IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx|
1295 IFCAP_CSUM_TCPv6_Tx|IFCAP_CSUM_UDPv6_Tx|
1296 IFCAP_TSOv4|IFCAP_TSOv6)) != 0) {
1297 splx(s);
1298 return EINVAL;
1299 }
1300 break;
1301 case SIOCSIFCAP:
1302 ifcr = data;
1303 if (ifp->if_mtu > JME_TX_FIFO_SIZE &&
1304 (ifcr->ifcr_capenable & (
1305 IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx|
1306 IFCAP_CSUM_TCPv6_Tx|IFCAP_CSUM_UDPv6_Tx|
1307 IFCAP_TSOv4|IFCAP_TSOv6)) != 0) {
1308 splx(s);
1309 return EINVAL;
1310 }
1311 break;
1312 }
1313
1314 error = ether_ioctl(ifp, cmd, data);
1315 if (error == ENETRESET && (ifp->if_flags & IFF_RUNNING)) {
1316 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) {
1317 jme_set_filter(sc);
1318 error = 0;
1319 } else {
1320 error = jme_init(ifp, 0);
1321 }
1322 }
1323 splx(s);
1324 return error;
1325 }
1326
1327 static int
1328 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1329 {
1330 struct jme_desc *txd;
1331 struct jme_desc *desc;
1332 struct mbuf *m;
1333 struct m_tag *mtag;
1334 int error, i, prod, headdsc, nsegs;
1335 uint32_t cflags, tso_segsz;
1336
1337 if (((*m_head)->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6)) != 0){
1338 /*
1339 * Due to the adherence to NDIS specification JMC250
1340 * assumes upper stack computed TCP pseudo checksum
1341 * without including payload length. This breaks
1342 * checksum offload for TSO case so recompute TCP
1343 * pseudo checksum for JMC250. Hopefully this wouldn't
1344 * be much burden on modern CPUs.
1345 */
1346 bool v4 = ((*m_head)->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
1347 int iphl = v4 ?
1348 M_CSUM_DATA_IPv4_IPHL((*m_head)->m_pkthdr.csum_data) :
1349 M_CSUM_DATA_IPv6_HL((*m_head)->m_pkthdr.csum_data);
1350 /*
1351 * note: we support vlan offloading, so we should never have
1352 * a ETHERTYPE_VLAN packet here - so ETHER_HDR_LEN is always
1353 * right.
1354 */
1355 int hlen = ETHER_HDR_LEN + iphl;
1356
1357 if (__predict_false((*m_head)->m_len <
1358 (hlen + sizeof(struct tcphdr)))) {
1359 /*
1360 * TCP/IP headers are not in the first mbuf; we need
1361 * to do this the slow and painful way. Let's just
1362 * hope this doesn't happen very often.
1363 */
1364 struct tcphdr th;
1365
1366 m_copydata((*m_head), hlen, sizeof(th), &th);
1367 if (v4) {
1368 struct ip ip;
1369
1370 m_copydata((*m_head), ETHER_HDR_LEN,
1371 sizeof(ip), &ip);
1372 ip.ip_len = 0;
1373 m_copyback((*m_head),
1374 ETHER_HDR_LEN + offsetof(struct ip, ip_len),
1375 sizeof(ip.ip_len), &ip.ip_len);
1376 th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
1377 ip.ip_dst.s_addr, htons(IPPROTO_TCP));
1378 } else {
1379 #if INET6
1380 struct ip6_hdr ip6;
1381
1382 m_copydata((*m_head), ETHER_HDR_LEN,
1383 sizeof(ip6), &ip6);
1384 ip6.ip6_plen = 0;
1385 m_copyback((*m_head), ETHER_HDR_LEN +
1386 offsetof(struct ip6_hdr, ip6_plen),
1387 sizeof(ip6.ip6_plen), &ip6.ip6_plen);
1388 th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
1389 &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
1390 #endif /* INET6 */
1391 }
1392 m_copyback((*m_head),
1393 hlen + offsetof(struct tcphdr, th_sum),
1394 sizeof(th.th_sum), &th.th_sum);
1395
1396 hlen += th.th_off << 2;
1397 } else {
1398 /*
1399 * TCP/IP headers are in the first mbuf; we can do
1400 * this the easy way.
1401 */
1402 struct tcphdr *th;
1403
1404 if (v4) {
1405 struct ip *ip =
1406 (void *)(mtod((*m_head), char *) +
1407 ETHER_HDR_LEN);
1408 th = (void *)(mtod((*m_head), char *) + hlen);
1409
1410 ip->ip_len = 0;
1411 th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
1412 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1413 } else {
1414 #if INET6
1415 struct ip6_hdr *ip6 =
1416 (void *)(mtod((*m_head), char *) +
1417 ETHER_HDR_LEN);
1418 th = (void *)(mtod((*m_head), char *) + hlen);
1419
1420 ip6->ip6_plen = 0;
1421 th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
1422 &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
1423 #endif /* INET6 */
1424 }
1425 hlen += th->th_off << 2;
1426 }
1427
1428 }
1429
1430 prod = sc->jme_tx_prod;
1431 txd = &sc->jme_txring[prod];
1432
1433 error = bus_dmamap_load_mbuf(sc->jme_dmatag, sc->jme_txmbufm[prod],
1434 *m_head, BUS_DMA_WRITE);
1435 if (error) {
1436 if (error == EFBIG) {
1437 log(LOG_ERR, "%s: Tx packet consumes too many "
1438 "DMA segments, dropping...\n",
1439 device_xname(sc->jme_dev));
1440 m_freem(*m_head);
1441 m_head = NULL;
1442 }
1443 return (error);
1444 }
1445 /*
1446 * Check descriptor overrun. Leave one free descriptor.
1447 * Since we always use 64bit address mode for transmitting,
1448 * each Tx request requires one more dummy descriptor.
1449 */
1450 nsegs = sc->jme_txmbufm[prod]->dm_nsegs;
1451 #ifdef JMEDEBUG_TX
1452 printf("jme_encap prod %d nsegs %d jme_tx_cnt %d\n", prod, nsegs, sc->jme_tx_cnt);
1453 #endif
1454 if (sc->jme_tx_cnt + nsegs + 1 > JME_NBUFS - 1) {
1455 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[prod]);
1456 return (ENOBUFS);
1457 }
1458 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[prod],
1459 0, sc->jme_txmbufm[prod]->dm_mapsize, BUS_DMASYNC_PREWRITE);
1460
1461 m = *m_head;
1462 cflags = 0;
1463 tso_segsz = 0;
1464 /* Configure checksum offload and TSO. */
1465 if ((m->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6)) != 0) {
1466 tso_segsz = (uint32_t)m->m_pkthdr.segsz << JME_TD_MSS_SHIFT;
1467 cflags |= JME_TD_TSO;
1468 } else {
1469 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0)
1470 cflags |= JME_TD_IPCSUM;
1471 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_TCPv6)) != 0)
1472 cflags |= JME_TD_TCPCSUM;
1473 if ((m->m_pkthdr.csum_flags & (M_CSUM_UDPv4|M_CSUM_UDPv6)) != 0)
1474 cflags |= JME_TD_UDPCSUM;
1475 }
1476 /* Configure VLAN. */
1477 if ((mtag = VLAN_OUTPUT_TAG(&sc->jme_ec, m)) != NULL) {
1478 cflags |= (VLAN_TAG_VALUE(mtag) & JME_TD_VLAN_MASK);
1479 cflags |= JME_TD_VLAN_TAG;
1480 }
1481
1482 desc = &sc->jme_txring[prod];
1483 desc->flags = htole32(cflags);
1484 desc->buflen = htole32(tso_segsz);
1485 desc->addr_hi = htole32(m->m_pkthdr.len);
1486 desc->addr_lo = 0;
1487 headdsc = prod;
1488 sc->jme_tx_cnt++;
1489 JME_DESC_INC(prod, JME_NBUFS);
1490 for (i = 0; i < nsegs; i++) {
1491 desc = &sc->jme_txring[prod];
1492 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT);
1493 desc->buflen =
1494 htole32(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_len);
1495 desc->addr_hi = htole32(
1496 JME_ADDR_HI(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr));
1497 desc->addr_lo = htole32(
1498 JME_ADDR_LO(sc->jme_txmbufm[headdsc]->dm_segs[i].ds_addr));
1499 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap,
1500 prod * sizeof(struct jme_desc), sizeof(struct jme_desc),
1501 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1502 sc->jme_txmbuf[prod] = NULL;
1503 sc->jme_tx_cnt++;
1504 JME_DESC_INC(prod, JME_NBUFS);
1505 }
1506
1507 /* Update producer index. */
1508 sc->jme_tx_prod = prod;
1509 #ifdef JMEDEBUG_TX
1510 printf("jme_encap prod now %d\n", sc->jme_tx_prod);
1511 #endif
1512 /*
1513 * Finally request interrupt and give the first descriptor
1514 * owenership to hardware.
1515 */
1516 desc = &sc->jme_txring[headdsc];
1517 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1518 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap,
1519 headdsc * sizeof(struct jme_desc), sizeof(struct jme_desc),
1520 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1521
1522 sc->jme_txmbuf[headdsc] = m;
1523 return (0);
1524 }
1525
1526 static void
1527 jme_txeof(struct jme_softc *sc)
1528 {
1529 struct ifnet *ifp;
1530 struct jme_desc *desc;
1531 uint32_t status;
1532 int cons, cons0, nsegs, seg;
1533
1534 ifp = &sc->jme_if;
1535
1536 #ifdef JMEDEBUG_TX
1537 printf("jme_txeof cons %d prod %d\n",
1538 sc->jme_tx_cons, sc->jme_tx_prod);
1539 printf("jme_txeof JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x "
1540 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x "
1541 "JME_TXTRHD 0x%x\n",
1542 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR),
1543 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO),
1544 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI),
1545 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC),
1546 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA),
1547 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC),
1548 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC),
1549 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD));
1550 for (cons = sc->jme_tx_cons; cons != sc->jme_tx_prod; ) {
1551 desc = &sc->jme_txring[cons];
1552 printf("ring[%d] 0x%x 0x%x 0x%x 0x%x\n", cons,
1553 desc->flags, desc->buflen, desc->addr_hi, desc->addr_lo);
1554 JME_DESC_INC(cons, JME_NBUFS);
1555 }
1556 #endif
1557
1558 cons = sc->jme_tx_cons;
1559 if (cons == sc->jme_tx_prod)
1560 return;
1561
1562 /*
1563 * Go through our Tx list and free mbufs for those
1564 * frames which have been transmitted.
1565 */
1566 for (; cons != sc->jme_tx_prod;) {
1567 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap,
1568 cons * sizeof(struct jme_desc), sizeof(struct jme_desc),
1569 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1570
1571 desc = &sc->jme_txring[cons];
1572 status = le32toh(desc->flags);
1573 #ifdef JMEDEBUG_TX
1574 printf("jme_txeof %i status 0x%x nsegs %d\n", cons, status,
1575 sc->jme_txmbufm[cons]->dm_nsegs);
1576 #endif
1577 if (status & JME_TD_OWN)
1578 break;
1579
1580 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0)
1581 ifp->if_oerrors++;
1582 else {
1583 ifp->if_opackets++;
1584 if ((status & JME_TD_COLLISION) != 0)
1585 ifp->if_collisions +=
1586 le32toh(desc->buflen) &
1587 JME_TD_BUF_LEN_MASK;
1588 }
1589 /*
1590 * Only the first descriptor of multi-descriptor
1591 * transmission is updated so driver have to skip entire
1592 * chained buffers for the transmiited frame. In other
1593 * words, JME_TD_OWN bit is valid only at the first
1594 * descriptor of a multi-descriptor transmission.
1595 */
1596 nsegs = sc->jme_txmbufm[cons]->dm_nsegs;
1597 cons0 = cons;
1598 JME_DESC_INC(cons, JME_NBUFS);
1599 for (seg = 1; seg < nsegs + 1; seg++) {
1600 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmap,
1601 cons * sizeof(struct jme_desc),
1602 sizeof(struct jme_desc),
1603 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1604 sc->jme_txring[cons].flags = 0;
1605 JME_DESC_INC(cons, JME_NBUFS);
1606 }
1607 /* Reclaim transferred mbufs. */
1608 bus_dmamap_sync(sc->jme_dmatag, sc->jme_txmbufm[cons0],
1609 0, sc->jme_txmbufm[cons0]->dm_mapsize,
1610 BUS_DMASYNC_POSTWRITE);
1611 bus_dmamap_unload(sc->jme_dmatag, sc->jme_txmbufm[cons0]);
1612
1613 KASSERT(sc->jme_txmbuf[cons0] != NULL);
1614 m_freem(sc->jme_txmbuf[cons0]);
1615 sc->jme_txmbuf[cons0] = NULL;
1616 sc->jme_tx_cnt -= nsegs + 1;
1617 KASSERT(sc->jme_tx_cnt >= 0);
1618 sc->jme_if.if_flags &= ~IFF_OACTIVE;
1619 }
1620 sc->jme_tx_cons = cons;
1621 /* Unarm watchog timer when there is no pending descriptors in queue. */
1622 if (sc->jme_tx_cnt == 0)
1623 ifp->if_timer = 0;
1624 #ifdef JMEDEBUG_TX
1625 printf("jme_txeof jme_tx_cnt %d\n", sc->jme_tx_cnt);
1626 #endif
1627 }
1628
1629 static void
1630 jme_ifstart(struct ifnet *ifp)
1631 {
1632 jme_softc_t *sc = ifp->if_softc;
1633 struct mbuf *mb_head;
1634 int enq;
1635
1636 /*
1637 * check if we can free some desc.
1638 * Clear TX interrupt status to reset TX coalescing counters.
1639 */
1640 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc,
1641 JME_INTR_STATUS, INTR_TXQ_COMP);
1642 jme_txeof(sc);
1643
1644 if ((sc->jme_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
1645 return;
1646 for (enq = 0;; enq++) {
1647 nexttx:
1648 /* Grab a paquet for output */
1649 IFQ_DEQUEUE(&ifp->if_snd, mb_head);
1650 if (mb_head == NULL) {
1651 #ifdef JMEDEBUG_TX
1652 printf("%s: nothing to send\n", __func__);
1653 #endif
1654 break;
1655 }
1656 /* try to add this mbuf to the TX ring */
1657 if (jme_encap(sc, &mb_head)) {
1658 if (mb_head == NULL) {
1659 ifp->if_oerrors++;
1660 /* packet dropped, try next one */
1661 goto nexttx;
1662 }
1663 /* resource shortage, try again later */
1664 IF_PREPEND(&ifp->if_snd, mb_head);
1665 ifp->if_flags |= IFF_OACTIVE;
1666 break;
1667 }
1668 #if NBPFILTER > 0
1669 /* Pass packet to bpf if there is a listener */
1670 if (ifp->if_bpf)
1671 bpf_mtap(ifp->if_bpf, mb_head);
1672 #endif
1673 }
1674 #ifdef JMEDEBUG_TX
1675 printf("jme_ifstart enq %d\n", enq);
1676 #endif
1677 if (enq) {
1678 /*
1679 * Set a 5 second timer just in case we don't hear from
1680 * the card again.
1681 */
1682 ifp->if_timer = 5;
1683 /*
1684 * Reading TXCSR takes very long time under heavy load
1685 * so cache TXCSR value and writes the ORed value with
1686 * the kick command to the TXCSR. This saves one register
1687 * access cycle.
1688 */
1689 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR,
1690 sc->jme_txcsr | TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0));
1691 #ifdef JMEDEBUG_TX
1692 printf("jme_ifstart JME_TXCSR 0x%x JME_TXDBA_LO 0x%x JME_TXDBA_HI 0x%x "
1693 "JME_TXQDC 0x%x JME_TXNDA 0x%x JME_TXMAC 0x%x JME_TXPFC 0x%x "
1694 "JME_TXTRHD 0x%x\n",
1695 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR),
1696 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_LO),
1697 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXDBA_HI),
1698 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXQDC),
1699 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXNDA),
1700 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC),
1701 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC),
1702 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD));
1703 #endif
1704 }
1705 }
1706
1707 static void
1708 jme_ifwatchdog(struct ifnet *ifp)
1709 {
1710 jme_softc_t *sc = ifp->if_softc;
1711
1712 if ((ifp->if_flags & IFF_RUNNING) == 0)
1713 return;
1714 printf("%s: device timeout\n", device_xname(sc->jme_dev));
1715 ifp->if_oerrors++;
1716 jme_init(ifp, 0);
1717 }
1718
1719 static int
1720 jme_mediachange(struct ifnet *ifp)
1721 {
1722 int error;
1723 jme_softc_t *sc = ifp->if_softc;
1724
1725 if ((error = mii_mediachg(&sc->jme_mii)) == ENXIO)
1726 error = 0;
1727 else if (error != 0) {
1728 aprint_error_dev(sc->jme_dev, "could not set media\n");
1729 return error;
1730 }
1731 return 0;
1732 }
1733
1734 static void
1735 jme_ticks(void *v)
1736 {
1737 jme_softc_t *sc = v;
1738 int s = splnet();
1739
1740 /* Tick the MII. */
1741 mii_tick(&sc->jme_mii);
1742
1743 /* every seconds */
1744 callout_reset(&sc->jme_tick_ch, hz, jme_ticks, sc);
1745 splx(s);
1746 }
1747
1748 static void
1749 jme_mac_config(jme_softc_t *sc)
1750 {
1751 uint32_t ghc, gpreg, rxmac, txmac, txpause;
1752 struct mii_data *mii = &sc->jme_mii;
1753
1754 ghc = 0;
1755 rxmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC);
1756 rxmac &= ~RXMAC_FC_ENB;
1757 txmac = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC);
1758 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1759 txpause = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC);
1760 txpause &= ~TXPFC_PAUSE_ENB;
1761
1762 if (mii->mii_media_active & IFM_FDX) {
1763 ghc |= GHC_FULL_DUPLEX;
1764 rxmac &= ~RXMAC_COLL_DET_ENB;
1765 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1766 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1767 TXMAC_FRAME_BURST);
1768 /* Disable retry transmit timer/retry limit. */
1769 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD,
1770 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD)
1771 & ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1772 } else {
1773 rxmac |= RXMAC_COLL_DET_ENB;
1774 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1775 /* Enable retry transmit timer/retry limit. */
1776 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD,
1777 bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXTRHD) | TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1778 }
1779 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */
1780 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1781 case IFM_10_T:
1782 ghc |= GHC_SPEED_10 | GHC_CLKSRC_10_100;
1783 break;
1784 case IFM_100_TX:
1785 ghc |= GHC_SPEED_100 | GHC_CLKSRC_10_100;
1786 break;
1787 case IFM_1000_T:
1788 ghc |= GHC_SPEED_1000 | GHC_CLKSRC_1000;
1789 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1790 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1791 break;
1792 default:
1793 break;
1794 }
1795 if ((sc->jme_flags & JME_FLAG_GIGA) &&
1796 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) {
1797 /*
1798 * Workaround occasional packet loss issue of JMC250 A2
1799 * when it runs on half-duplex media.
1800 */
1801 #ifdef JMEDEBUG
1802 printf("JME250 A2 workaround\n");
1803 #endif
1804 gpreg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc,
1805 JME_GPREG1);
1806 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1807 gpreg &= ~GPREG1_HDPX_FIX;
1808 else
1809 gpreg |= GPREG1_HDPX_FIX;
1810 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc,
1811 JME_GPREG1, gpreg);
1812 /* Workaround CRC errors at 100Mbps on JMC250 A2. */
1813 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
1814 /* Extend interface FIFO depth. */
1815 jme_mii_write(sc->jme_dev, sc->jme_phyaddr,
1816 0x1B, 0x0000);
1817 } else {
1818 /* Select default interface FIFO depth. */
1819 jme_mii_write(sc->jme_dev, sc->jme_phyaddr,
1820 0x1B, 0x0004);
1821 }
1822 }
1823 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_GHC, ghc);
1824 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxmac);
1825 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXMAC, txmac);
1826 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXPFC, txpause);
1827 }
1828
1829 static void
1830 jme_set_filter(jme_softc_t *sc)
1831 {
1832 struct ifnet *ifp = &sc->jme_if;
1833 struct ether_multistep step;
1834 struct ether_multi *enm;
1835 uint32_t hash[2] = {0, 0};
1836 int i;
1837 uint32_t rxcfg;
1838
1839 rxcfg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC);
1840 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
1841 RXMAC_ALLMULTI);
1842 /* Always accept frames destined to our station address. */
1843 rxcfg |= RXMAC_UNICAST;
1844 if ((ifp->if_flags & IFF_BROADCAST) != 0)
1845 rxcfg |= RXMAC_BROADCAST;
1846 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
1847 if ((ifp->if_flags & IFF_PROMISC) != 0)
1848 rxcfg |= RXMAC_PROMISC;
1849 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
1850 rxcfg |= RXMAC_ALLMULTI;
1851 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
1852 JME_MAR0, 0xFFFFFFFF);
1853 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
1854 JME_MAR1, 0xFFFFFFFF);
1855 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac,
1856 JME_RXMAC, rxcfg);
1857 return;
1858 }
1859 /*
1860 * Set up the multicast address filter by passing all multicast
1861 * addresses through a CRC generator, and then using the low-order
1862 * 6 bits as an index into the 64 bit multicast hash table. The
1863 * high order bits select the register, while the rest of the bits
1864 * select the bit within the register.
1865 */
1866 rxcfg |= RXMAC_MULTICAST;
1867 memset(hash, 0, sizeof(hash));
1868
1869 ETHER_FIRST_MULTI(step, &sc->jme_ec, enm);
1870 while (enm != NULL) {
1871 #ifdef JEMDBUG
1872 printf("%s: addrs %s %s\n", __func__,
1873 ether_sprintf(enm->enm_addrlo),
1874 ether_sprintf(enm->enm_addrhi));
1875 #endif
1876 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) {
1877 i = ether_crc32_be(enm->enm_addrlo, 6);
1878 /* Just want the 6 least significant bits. */
1879 i &= 0x3f;
1880 hash[i / 32] |= 1 << (i%32);
1881 } else {
1882 hash[0] = hash[1] = 0xffffffff;
1883 sc->jme_if.if_flags |= IFF_ALLMULTI;
1884 break;
1885 }
1886 ETHER_NEXT_MULTI(step, enm);
1887 }
1888 #ifdef JMEDEBUG
1889 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]);
1890 #endif
1891 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR0, hash[0]);
1892 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_MAR1, hash[1]);
1893 bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, rxcfg);
1894 }
1895
1896 #if 0
1897 static int
1898 jme_multicast_hash(uint8_t *a)
1899 {
1900 int hash;
1901
1902 #define DA(addr,bit) (addr[5 - (bit / 8)] & (1 << (bit % 8)))
1903 #define xor8(a,b,c,d,e,f,g,h) \
1904 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \
1905 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1)
1906
1907 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30),
1908 DA(a,36), DA(a,42));
1909 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31),
1910 DA(a,37), DA(a,43)) << 1;
1911 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32),
1912 DA(a,38), DA(a,44)) << 2;
1913 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33),
1914 DA(a,39), DA(a,45)) << 3;
1915 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34),
1916 DA(a,40), DA(a,46)) << 4;
1917 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35),
1918 DA(a,41), DA(a,47)) << 5;
1919
1920 return hash;
1921 }
1922 #endif
1923
1924 static int
1925 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
1926 {
1927 uint32_t reg;
1928 int i;
1929
1930 *val = 0;
1931 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) {
1932 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy,
1933 JME_SMBCSR);
1934 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
1935 break;
1936 delay(10);
1937 }
1938
1939 if (i == 0) {
1940 aprint_error_dev(sc->jme_dev, "EEPROM idle timeout!\n");
1941 return (ETIMEDOUT);
1942 }
1943
1944 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
1945 bus_space_write_4(sc->jme_bt_phy, sc->jme_bh_phy,
1946 JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
1947 for (i = JME_EEPROM_TIMEOUT / 10; i > 0; i--) {
1948 delay(10);
1949 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy,
1950 JME_SMBINTF);
1951 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
1952 break;
1953 }
1954
1955 if (i == 0) {
1956 aprint_error_dev(sc->jme_dev, "EEPROM read timeout!\n");
1957 return (ETIMEDOUT);
1958 }
1959
1960 reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, JME_SMBINTF);
1961 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
1962 return (0);
1963 }
1964
1965
1966 static int
1967 jme_eeprom_macaddr(struct jme_softc *sc)
1968 {
1969 uint8_t eaddr[ETHER_ADDR_LEN];
1970 uint8_t fup, reg, val;
1971 uint32_t offset;
1972 int match;
1973
1974 offset = 0;
1975 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
1976 fup != JME_EEPROM_SIG0)
1977 return (ENOENT);
1978 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
1979 fup != JME_EEPROM_SIG1)
1980 return (ENOENT);
1981 match = 0;
1982 do {
1983 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
1984 break;
1985 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1)
1986 == (fup & (JME_EEPROM_FUNC_MASK|JME_EEPROM_PAGE_MASK))) {
1987 if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
1988 break;
1989 if (reg >= JME_PAR0 &&
1990 reg < JME_PAR0 + ETHER_ADDR_LEN) {
1991 if (jme_eeprom_read_byte(sc, offset + 2,
1992 &val) != 0)
1993 break;
1994 eaddr[reg - JME_PAR0] = val;
1995 match++;
1996 }
1997 }
1998 if (fup & JME_EEPROM_DESC_END)
1999 break;
2000
2001 /* Try next eeprom descriptor. */
2002 offset += JME_EEPROM_DESC_BYTES;
2003 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
2004
2005 if (match == ETHER_ADDR_LEN) {
2006 memcpy(sc->jme_enaddr, eaddr, ETHER_ADDR_LEN);
2007 return (0);
2008 }
2009
2010 return (ENOENT);
2011 }
2012
2013 /*
2014 * Set up sysctl(3) MIB, hw.jme.* - Individual controllers will be
2015 * set up in jme_pci_attach()
2016 */
2017 SYSCTL_SETUP(sysctl_jme, "sysctl jme subtree setup")
2018 {
2019 int rc;
2020 const struct sysctlnode *node;
2021
2022 if ((rc = sysctl_createv(clog, 0, NULL, NULL,
2023 0, CTLTYPE_NODE, "hw", NULL,
2024 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) {
2025 goto err;
2026 }
2027
2028 if ((rc = sysctl_createv(clog, 0, NULL, &node,
2029 0, CTLTYPE_NODE, "jme",
2030 SYSCTL_DESCR("jme interface controls"),
2031 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) {
2032 goto err;
2033 }
2034
2035 jme_root_num = node->sysctl_num;
2036 return;
2037
2038 err:
2039 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc);
2040 }
2041
2042 static int
2043 jme_sysctl_intrxto(SYSCTLFN_ARGS)
2044 {
2045 int error, t;
2046 struct sysctlnode node;
2047 struct jme_softc *sc;
2048 uint32_t reg;
2049
2050 node = *rnode;
2051 sc = node.sysctl_data;
2052 t = sc->jme_intrxto;
2053 node.sysctl_data = &t;
2054 error = sysctl_lookup(SYSCTLFN_CALL(&node));
2055 if (error || newp == NULL)
2056 return error;
2057
2058 if (t < PCCRX_COAL_TO_MIN || t > PCCRX_COAL_TO_MAX)
2059 return EINVAL;
2060
2061 /*
2062 * update the softc with sysctl-changed value, and mark
2063 * for hardware update
2064 */
2065 sc->jme_intrxto = t;
2066 /* Configure Rx queue 0 packet completion coalescing. */
2067 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK;
2068 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK;
2069 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg);
2070 return 0;
2071 }
2072
2073 static int
2074 jme_sysctl_intrxct(SYSCTLFN_ARGS)
2075 {
2076 int error, t;
2077 struct sysctlnode node;
2078 struct jme_softc *sc;
2079 uint32_t reg;
2080
2081 node = *rnode;
2082 sc = node.sysctl_data;
2083 t = sc->jme_intrxct;
2084 node.sysctl_data = &t;
2085 error = sysctl_lookup(SYSCTLFN_CALL(&node));
2086 if (error || newp == NULL)
2087 return error;
2088
2089 if (t < PCCRX_COAL_PKT_MIN || t > PCCRX_COAL_PKT_MAX)
2090 return EINVAL;
2091
2092 /*
2093 * update the softc with sysctl-changed value, and mark
2094 * for hardware update
2095 */
2096 sc->jme_intrxct = t;
2097 /* Configure Rx queue 0 packet completion coalescing. */
2098 reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK;
2099 reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK;
2100 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg);
2101 return 0;
2102 }
2103
2104 static int
2105 jme_sysctl_inttxto(SYSCTLFN_ARGS)
2106 {
2107 int error, t;
2108 struct sysctlnode node;
2109 struct jme_softc *sc;
2110 uint32_t reg;
2111
2112 node = *rnode;
2113 sc = node.sysctl_data;
2114 t = sc->jme_inttxto;
2115 node.sysctl_data = &t;
2116 error = sysctl_lookup(SYSCTLFN_CALL(&node));
2117 if (error || newp == NULL)
2118 return error;
2119
2120 if (t < PCCTX_COAL_TO_MIN || t > PCCTX_COAL_TO_MAX)
2121 return EINVAL;
2122
2123 /*
2124 * update the softc with sysctl-changed value, and mark
2125 * for hardware update
2126 */
2127 sc->jme_inttxto = t;
2128 /* Configure Tx queue 0 packet completion coalescing. */
2129 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK;
2130 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK;
2131 reg |= PCCTX_COAL_TXQ0;
2132 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg);
2133 return 0;
2134 }
2135
2136 static int
2137 jme_sysctl_inttxct(SYSCTLFN_ARGS)
2138 {
2139 int error, t;
2140 struct sysctlnode node;
2141 struct jme_softc *sc;
2142 uint32_t reg;
2143
2144 node = *rnode;
2145 sc = node.sysctl_data;
2146 t = sc->jme_inttxct;
2147 node.sysctl_data = &t;
2148 error = sysctl_lookup(SYSCTLFN_CALL(&node));
2149 if (error || newp == NULL)
2150 return error;
2151
2152 if (t < PCCTX_COAL_PKT_MIN || t > PCCTX_COAL_PKT_MAX)
2153 return EINVAL;
2154
2155 /*
2156 * update the softc with sysctl-changed value, and mark
2157 * for hardware update
2158 */
2159 sc->jme_inttxct = t;
2160 /* Configure Tx queue 0 packet completion coalescing. */
2161 reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK;
2162 reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK;
2163 reg |= PCCTX_COAL_TXQ0;
2164 bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg);
2165 return 0;
2166 }
NetBSD on the FriendlyARM MINI2440